diff options
| author | Archana R <aravind5@in.ibm.com> | 2022-03-07 01:54:14 -0600 |
|---|---|---|
| committer | Paul Murphy <murp@ibm.com> | 2022-03-15 15:12:55 +0000 |
| commit | 7b15e297a26842f1f3408ee9d7942f8cfab2e5ea (patch) | |
| tree | 17633f98478f1c10ad240da74cbfa073ad890a86 /src | |
| parent | e475cf2e705d4eda8647426e060898ab3f643610 (diff) | |
| download | go-git-7b15e297a26842f1f3408ee9d7942f8cfab2e5ea.tar.gz | |
cmd/compile: fix PrefetchStreamed builtin implementation on PPC64
This CL fixes encoding of PrefetchStreamed on PPC64 to be consistent
with what is implemented on AMD64 and ARM64 platforms which is
prefetchNTA (prefetch non-temporal access). Looking at the definition
of prefetchNTA, the closest corresponding Touch hint (TH) value to be
used on PPC64 is 16 that states that the address is accessed in a
transient manner. Current usage of TH=8 may cause degraded
performance.
Change-Id: I393bf5a9b971a22f632b3cbfb4fa659062af9a27
Reviewed-on: https://go-review.googlesource.com/c/go/+/390316
Reviewed-by: Paul Murphy <murp@ibm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cmd/compile/internal/ssa/gen/PPC64.rules | 8 | ||||
| -rw-r--r-- | src/cmd/compile/internal/ssa/rewritePPC64.go | 4 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/cmd/compile/internal/ssa/gen/PPC64.rules b/src/cmd/compile/internal/ssa/gen/PPC64.rules index c3f07a4e22..eb9fe3cf72 100644 --- a/src/cmd/compile/internal/ssa/gen/PPC64.rules +++ b/src/cmd/compile/internal/ssa/gen/PPC64.rules @@ -1479,7 +1479,11 @@ && clobber(call) => (Move [sz] dst src mem) -// Prefetch instructions (aux is option: 0 - DCBT ; 8 - DCBT stream) +// Prefetch instructions (TH specified using aux field) +// For DCBT Ra,Rb,TH, A value of TH indicates: +// 0, hint this cache line will be used soon. (PrefetchCache) +// 16, hint this cache line will not be used for long. (PrefetchCacheStreamed) +// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/ (PrefetchCache ptr mem) => (DCBT ptr mem [0]) -(PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [8]) +(PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16]) diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go index 7592b4f505..5da6d9641c 100644 --- a/src/cmd/compile/internal/ssa/rewritePPC64.go +++ b/src/cmd/compile/internal/ssa/rewritePPC64.go @@ -14140,12 +14140,12 @@ func rewriteValuePPC64_OpPrefetchCacheStreamed(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCacheStreamed ptr mem) - // result: (DCBT ptr mem [8]) + // result: (DCBT ptr mem [16]) for { ptr := v_0 mem := v_1 v.reset(OpPPC64DCBT) - v.AuxInt = int64ToAuxInt(8) + v.AuxInt = int64ToAuxInt(16) v.AddArg2(ptr, mem) return true } |