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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-08-20 06:42:24 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-08-22 06:23:37 -0700 |
| commit | 78c9ec9000f873abe7a15a91b87080a2e4308260 (patch) | |
| tree | 1fb85aec1d1f6394f650758f5074130e77fea131 /sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S | |
| parent | c333dcf8d8f9e6e46475d9eff24bd5394b5d3d9e (diff) | |
| download | glibc-78c9ec9000f873abe7a15a91b87080a2e4308260.tar.gz | |
x86-64: Optimize load of all bits set into ZMM register [BZ #28252]
Optimize loads of all bits set into ZMM register in AVX512 SVML codes
by replacing
vpbroadcastq .L_2il0floatpacket.16(%rip), %zmmX
and
vmovups .L_2il0floatpacket.13(%rip), %zmmX
with
vpternlogd $0xff, %zmmX, %zmmX, %zmmX
This fixes BZ #28252.
Diffstat (limited to 'sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S')
| -rw-r--r-- | sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S index 9cf359c86f..a446c504f6 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S @@ -317,7 +317,7 @@ WRAPPER_IMPL_AVX512_fFF _ZGVdN8vvv_sincosf /* Result sign calculations */ vpternlogd $150, %zmm0, %zmm14, %zmm1 - vmovups .L_2il0floatpacket.13(%rip), %zmm14 + vpternlogd $0xff, %zmm14, %zmm14, %zmm14 /* Add correction term 0.5 for cos() part */ vaddps %zmm8, %zmm5, %zmm15 @@ -748,8 +748,3 @@ END (_ZGVeN16vvv_sincosf_knl) ENTRY (_ZGVeN16vvv_sincosf_skx) WRAPPER_AVX512_vvv_vl4l4 _ZGVeN16vl4l4_sincosf_skx END (_ZGVeN16vvv_sincosf_skx) - - .section .rodata, "a" -.L_2il0floatpacket.13: - .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff - .type .L_2il0floatpacket.13,@object |