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| author | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:19:34 +0530 |
|---|---|---|
| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:23:13 +0530 |
| commit | db9bab09a51188bf57afeb47040ce6837b878367 (patch) | |
| tree | c8cf726159cb485d1fa9b755a300404ad90bb7d8 | |
| parent | be080b6c143901d998c91f28ef7b2fe4a25c0237 (diff) | |
| download | glibc-db9bab09a51188bf57afeb47040ce6837b878367.tar.gz | |
Document cache information sysconf variables
Write short descriptions for each of the cache information sysconf
variables.
* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
variables.
Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
| -rw-r--r-- | ChangeLog | 12 | ||||
| -rw-r--r-- | manual/conf.texi | 61 |
2 files changed, 73 insertions, 0 deletions
@@ -1,3 +1,15 @@ +2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org> + + * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, + _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, + _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, + _SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE, + _SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE, + _SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC, + _SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE, + _SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New + variables. + 2017-10-23 Michael Collison <michael.collison@arm.com> * sysdeps/aarch64/fpu/e_sqrt.c (ieee754_sqrt): Replace asm statements diff --git a/manual/conf.texi b/manual/conf.texi index 875862c847..079bdb295e 100644 --- a/manual/conf.texi +++ b/manual/conf.texi @@ -678,6 +678,67 @@ Inquire about the number of available physical pages in the system. Inquire about the number of functions which can be registered as termination functions for @code{atexit}; @pxref{Cleanups on Exit}. +@item _SC_LEVEL1_ICACHE_SIZE +@standards{GNU, unistd.h} +Inquire about the size of the Level 1 instruction cache. + +@item _SC_LEVEL1_ICACHE_ASSOC +@standards{GNU, unistd.h} +Inquire about the associativity of the Level 1 instruction cache. + +@item _SC_LEVEL1_ICACHE_LINESIZE +@standards{GNU, unistd.h} +Inquire about the line length of the Level 1 instruction cache. + +@item _SC_LEVEL1_DCACHE_SIZE +@standards{GNU, unistd.h} +Inquire about the size of the Level 1 data cache. + +@item _SC_LEVEL1_DCACHE_ASSOC +@standards{GNU, unistd.h} +Inquire about the associativity of the Level 1 data cache. + +@item _SC_LEVEL1_DCACHE_LINESIZE +@standards{GNU, unistd.h} +Inquire about the line length of the Level 1 data cache. + +@item _SC_LEVEL2_CACHE_SIZE +@standards{GNU, unistd.h} +Inquire about the size of the Level 2 cache. + +@item _SC_LEVEL2_CACHE_ASSOC +@standards{GNU, unistd.h} +Inquire about the associativity of the Level 2 cache. + +@item _SC_LEVEL2_CACHE_LINESIZE +@standards{GNU, unistd.h} +Inquire about the line length of the Level 2 cache. + +@item _SC_LEVEL3_CACHE_SIZE +@standards{GNU, unistd.h} +Inquire about the size of the Level 3 cache. + +@item _SC_LEVEL3_CACHE_ASSOC +@standards{GNU, unistd.h} +Inquire about the associativity of the Level 3 cache. + +@item _SC_LEVEL3_CACHE_LINESIZE +@standards{GNU, unistd.h} +Inquire about the line length of the Level 3 cache. + +@item _SC_LEVEL4_CACHE_SIZE +@standards{GNU, unistd.h} +Inquire about the size of the Level 4 cache. + +@item _SC_LEVEL4_CACHE_ASSOC +@standards{GNU, unistd.h} +Inquire about the associativity of the Level 4 cache. + +@item _SC_LEVEL4_CACHE_LINESIZE +@standards{GNU, unistd.h} +Inquire about the line length of the Level 4 cache. + + @item _SC_XOPEN_VERSION @standards{X/Open, unistd.h} Inquire about the parameter corresponding to @code{_XOPEN_VERSION}. |