diff options
| author | DJ Delorie <dj@delorie.com> | 2011-11-02 03:08:51 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@delorie.com> | 2011-11-02 03:08:51 +0000 |
| commit | 2faf7b51089e5f8cfc6fa8a77924eba284b1fbd7 (patch) | |
| tree | d055834c437a425b7bf980505aed8ef93701efa5 | |
| parent | 89c604c3b751d615420e32b7a4f82c1f4dffaeff (diff) | |
| download | gdb-2faf7b51089e5f8cfc6fa8a77924eba284b1fbd7.tar.gz | |
[.]
* configure.ac (rl78-*-*) New case.
* configure: Regenerate.
[bfd]
* Makefile.am (ALL_MACHINES): Add cpu-rl78.lo.
(ALL_MACHINES_CFILES): Add cpu-rl78.c.
(BFD32_BACKENDS): Add elf32-rl78.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rl78.c.
(Makefile.in): Regenerate.
* archures.c (bfd_architecture): Define bfd_arch_rl78.
(bfd_archures_list): Add bfd_rl78_arch.
* config.bfd: Add rl78-*-elf.
* configure.in: Add bfd_elf32_rl78_vec.
* reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations.
* targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rl78.c: New file.
* elf32-rl78.c: New file.
[binutils]
* readelf.c: Include elf/rl78.h
(guess_is_rela): Handle EM_RL78.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
* NEWS: Mention addition of RL78 support.
* MAINTAINERS: Add myself as RL78 port maintainer.
[gas]
* Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c.
(TARGET_CPU_HFILES): Add rc-rl78.h.
(EXTRA_DIST): Add rl78-parse.c and rl78-parse.y.
(rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules.
* Makefile.in: Regenerate.
* configure.in: Add rl78 case.
* configure: Regenerate.
* configure.tgt: Add rl78 case.
* config/rl78-defs.h: New file.
* config/rl78-parse.y: New file.
* config/tc-rl78.c: New file.
* config/tc-rl78.h: New file.
* NEWS: Add Renesas RL78.
* doc/Makefile.am (c-rl78.texi): New.
* doc/Makefile.in: Likewise.
* doc/all.texi: Enable it.
* doc/as.texi: Add it.
[include]
* dis-asm.h (print_insn_rl78): Declare.
[include/elf]
* common.h (EM_RL78, EM_78K0R): New.
* rl78.h: New.
[include/opcode]
* rl78.h: New file.
[ld]
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c.
(+eelf32rl78.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Add rl78-*-* case.
* emulparams/elf32rl78.sh: New file.
* NEWS: Mention addition of Renesas RL78 support.
[opcodes]
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
rl78-dis.c.
(MAINTAINERCLEANFILES): Add rl78-decode.c.
(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
* Makefile.in: Regenerate.
* configure.in: Add bfd_rl78_arch case.
* configure: Regenerate.
* disassemble.c: Define ARCH_rl78.
(disassembler): Add ARCH_rl78 case.
* rl78-decode.c: New file.
* rl78-decode.opc: New file.
* rl78-dis.c: New file.
| -rw-r--r-- | ChangeLog | 5 | ||||
| -rw-r--r-- | bfd/ChangeLog | 20 | ||||
| -rw-r--r-- | bfd/Makefile.am | 4 | ||||
| -rw-r--r-- | bfd/Makefile.in | 6 | ||||
| -rw-r--r-- | bfd/archures.c | 4 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 36 | ||||
| -rw-r--r-- | bfd/config.bfd | 4 | ||||
| -rwxr-xr-x | bfd/configure | 1 | ||||
| -rw-r--r-- | bfd/configure.in | 1 | ||||
| -rw-r--r-- | bfd/cpu-rl78.c | 39 | ||||
| -rw-r--r-- | bfd/elf32-rl78.c | 1553 | ||||
| -rw-r--r-- | bfd/libbfd.h | 32 | ||||
| -rw-r--r-- | bfd/reloc.c | 67 | ||||
| -rw-r--r-- | bfd/targets.c | 2 | ||||
| -rwxr-xr-x | configure | 4 | ||||
| -rw-r--r-- | configure.ac | 4 | ||||
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/dis-asm.h | 1 | ||||
| -rw-r--r-- | include/elf/ChangeLog | 5 | ||||
| -rw-r--r-- | include/elf/common.h | 2 | ||||
| -rw-r--r-- | include/elf/rl78.h | 118 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/rl78.h | 168 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 15 | ||||
| -rw-r--r-- | opcodes/Makefile.am | 6 | ||||
| -rw-r--r-- | opcodes/Makefile.in | 8 | ||||
| -rwxr-xr-x | opcodes/configure | 1 | ||||
| -rw-r--r-- | opcodes/configure.in | 1 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 6 | ||||
| -rw-r--r-- | opcodes/rl78-decode.c | 5731 | ||||
| -rw-r--r-- | opcodes/rl78-decode.opc | 1263 | ||||
| -rw-r--r-- | opcodes/rl78-dis.c | 327 |
32 files changed, 9442 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 0aa93d2621b..f795b4bb8a4 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,10 @@ 2011-11-01 DJ Delorie <dj@redhat.com> + * configure.ac (rl78-*-*) New case. + * configure: Regenerate. + +2011-11-01 DJ Delorie <dj@redhat.com> + * config.sub: Update to version 2011-10-29 (added rl78) 2011-10-27 Nick Clifton <nickc@redhat.com> diff --git a/bfd/ChangeLog b/bfd/ChangeLog index ba106c53d72..f20d7cc8369 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,23 @@ +2011-11-01 DJ Delorie <dj@redhat.com> + + * Makefile.am (ALL_MACHINES): Add cpu-rl78.lo. + (ALL_MACHINES_CFILES): Add cpu-rl78.c. + (BFD32_BACKENDS): Add elf32-rl78.lo. + (BFD32_BACKENDS_CFILES): Add elf32-rl78.c. + (Makefile.in): Regenerate. + * archures.c (bfd_architecture): Define bfd_arch_rl78. + (bfd_archures_list): Add bfd_rl78_arch. + * config.bfd: Add rl78-*-elf. + * configure.in: Add bfd_elf32_rl78_vec. + * reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations. + * targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec. + * Makefile.in: Regenerate. + * bfd-in2.h: Regenerate. + * configure: Regenerate. + * libbfd.h: Regenerate. + * cpu-rl78.c: New file. + * elf32-rl78.c: New file. + 2011-10-26 Nick Clifton <nickc@redhat.com> PR ld/13049 diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 46e94a5b30d..8f4fbee8639 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -123,6 +123,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ cpu-score.lo \ @@ -199,6 +200,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ cpu-score.c \ @@ -319,6 +321,7 @@ BFD32_BACKENDS = \ elf32-or32.lo \ elf32-pj.lo \ elf32-ppc.lo \ + elf32-rl78.lo \ elf32-rx.lo \ elf32-s390.lo \ elf32-sh-symbian.lo \ @@ -504,6 +507,7 @@ BFD32_BACKENDS_CFILES = \ elf32-or32.c \ elf32-pj.c \ elf32-ppc.c \ + elf32-rl78.c \ elf32-rx.c \ elf32-s390.c \ elf32-sh-symbian.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 12ec3ee0ba2..437bafcde06 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -422,6 +422,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ cpu-score.lo \ @@ -498,6 +499,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ cpu-score.c \ @@ -619,6 +621,7 @@ BFD32_BACKENDS = \ elf32-or32.lo \ elf32-pj.lo \ elf32-ppc.lo \ + elf32-rl78.lo \ elf32-rx.lo \ elf32-s390.lo \ elf32-sh-symbian.lo \ @@ -804,6 +807,7 @@ BFD32_BACKENDS_CFILES = \ elf32-or32.c \ elf32-pj.c \ elf32-ppc.c \ + elf32-rl78.c \ elf32-rx.c \ elf32-s390.c \ elf32-sh-symbian.c \ @@ -1303,6 +1307,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-s390.Plo@am__quote@ @@ -1383,6 +1388,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-score.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 9781f1eec18..5d0c682d7f0 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -403,6 +403,8 @@ DESCRIPTION .#define bfd_mach_cris_v0_v10 255 .#define bfd_mach_cris_v32 32 .#define bfd_mach_cris_v10_v32 1032 +. bfd_arch_rl78, +.#define bfd_mach_rl78 0x75 . bfd_arch_rx, {* Renesas RX. *} .#define bfd_mach_rx 0x75 . bfd_arch_s390, {* IBM s390 *} @@ -540,6 +542,7 @@ extern const bfd_arch_info_type bfd_plugin_arch; extern const bfd_arch_info_type bfd_powerpc_archs[]; #define bfd_powerpc_arch bfd_powerpc_archs[0] extern const bfd_arch_info_type bfd_rs6000_arch; +extern const bfd_arch_info_type bfd_rl78_arch; extern const bfd_arch_info_type bfd_rx_arch; extern const bfd_arch_info_type bfd_s390_arch; extern const bfd_arch_info_type bfd_score_arch; @@ -618,6 +621,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_pdp11_arch, &bfd_powerpc_arch, &bfd_rs6000_arch, + &bfd_rl78_arch, &bfd_rx_arch, &bfd_s390_arch, &bfd_score_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index f48d2d40eb3..88fd45aee17 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2109,6 +2109,8 @@ enum bfd_architecture #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 #define bfd_mach_cris_v10_v32 1032 + bfd_arch_rl78, +#define bfd_mach_rl78 0x75 bfd_arch_rx, /* Renesas RX. */ #define bfd_mach_rx 0x75 bfd_arch_s390, /* IBM s390 */ @@ -4057,6 +4059,40 @@ instructions */ instructions */ BFD_RELOC_AVR_6_ADIW, +/* Renesas RL78 Relocations. */ + BFD_RELOC_RL78_NEG8, + BFD_RELOC_RL78_NEG16, + BFD_RELOC_RL78_NEG24, + BFD_RELOC_RL78_NEG32, + BFD_RELOC_RL78_16_OP, + BFD_RELOC_RL78_24_OP, + BFD_RELOC_RL78_32_OP, + BFD_RELOC_RL78_8U, + BFD_RELOC_RL78_16U, + BFD_RELOC_RL78_24U, + BFD_RELOC_RL78_DIR3U_PCREL, + BFD_RELOC_RL78_DIFF, + BFD_RELOC_RL78_GPRELB, + BFD_RELOC_RL78_GPRELW, + BFD_RELOC_RL78_GPRELL, + BFD_RELOC_RL78_SYM, + BFD_RELOC_RL78_OP_SUBTRACT, + BFD_RELOC_RL78_OP_NEG, + BFD_RELOC_RL78_OP_AND, + BFD_RELOC_RL78_OP_SHRA, + BFD_RELOC_RL78_ABS8, + BFD_RELOC_RL78_ABS16, + BFD_RELOC_RL78_ABS16_REV, + BFD_RELOC_RL78_ABS32, + BFD_RELOC_RL78_ABS32_REV, + BFD_RELOC_RL78_ABS16U, + BFD_RELOC_RL78_ABS16UW, + BFD_RELOC_RL78_ABS16UL, + BFD_RELOC_RL78_RELAX, + BFD_RELOC_RL78_HI16, + BFD_RELOC_RL78_HI8, + BFD_RELOC_RL78_LO16, + /* Renesas RX Relocations. */ BFD_RELOC_RX_NEG8, BFD_RELOC_RX_NEG16, diff --git a/bfd/config.bfd b/bfd/config.bfd index 1e86dd48fdb..a1fa2b62df6 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -1197,6 +1197,10 @@ case "${targ}" in targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec" ;; + rl78-*-elf) + targ_defvec=bfd_elf32_rl78_vec + ;; + rx-*-elf) targ_defvec=bfd_elf32_rx_le_vec targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec bfd_elf32_rx_be_ns_vec" diff --git a/bfd/configure b/bfd/configure index e6a3a5ab2ca..ec9a7f5807f 100755 --- a/bfd/configure +++ b/bfd/configure @@ -15264,6 +15264,7 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_rl78_vec) tb="$tb elf32-rl78.lo $elf" ;; bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_rx_be_ns_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; diff --git a/bfd/configure.in b/bfd/configure.in index f6d3693aa1b..69ffe53f10c 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -763,6 +763,7 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_rl78_vec) tb="$tb elf32-rl78.lo $elf" ;; bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_rx_be_ns_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-rl78.c b/bfd/cpu-rl78.c new file mode 100644 index 00000000000..66024aee8ad --- /dev/null +++ b/bfd/cpu-rl78.c @@ -0,0 +1,39 @@ +/* BFD support for the RL78 processor. + Copyright (C) 2011 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_rl78_arch = +{ + 32, /* Bits per word. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_rl78, /* Architecture. */ + bfd_mach_rl78, /* Machine. */ + "rl78", /* Architecture name. */ + "rl78", /* Printable name. */ + 4, /* Section align power. */ + TRUE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + NULL /* Next in list. */ +}; diff --git a/bfd/elf32-rl78.c b/bfd/elf32-rl78.c new file mode 100644 index 00000000000..c969c71e7c5 --- /dev/null +++ b/bfd/elf32-rl78.c @@ -0,0 +1,1553 @@ +/* Renesas RL78 specific support for 32-bit ELF. + Copyright (C) 2011 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "bfd_stdint.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/rl78.h" +#include "libiberty.h" + +#define valid_16bit_address(v) ((v) <= 0x0ffff || (v) >= 0xf0000) + +#define RL78REL(n,sz,bit,shift,complain,pcrel) \ + HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \ + bfd_elf_generic_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE) + +/* Note that the relocations around 0x7f are internal to this file; + feel free to move them as needed to avoid conflicts with published + relocation numbers. */ + +static reloc_howto_type rl78_elf_howto_table [] = +{ + RL78REL (NONE, 0, 0, 0, dont, FALSE), + RL78REL (DIR32, 2, 32, 0, signed, FALSE), + RL78REL (DIR24S, 2, 24, 0, signed, FALSE), + RL78REL (DIR16, 1, 16, 0, dont, FALSE), + RL78REL (DIR16U, 1, 16, 0, unsigned, FALSE), + RL78REL (DIR16S, 1, 16, 0, signed, FALSE), + RL78REL (DIR8, 0, 8, 0, dont, FALSE), + RL78REL (DIR8U, 0, 8, 0, unsigned, FALSE), + RL78REL (DIR8S, 0, 8, 0, signed, FALSE), + RL78REL (DIR24S_PCREL, 2, 24, 0, signed, TRUE), + RL78REL (DIR16S_PCREL, 1, 16, 0, signed, TRUE), + RL78REL (DIR8S_PCREL, 0, 8, 0, signed, TRUE), + RL78REL (DIR16UL, 1, 16, 2, unsigned, FALSE), + RL78REL (DIR16UW, 1, 16, 1, unsigned, FALSE), + RL78REL (DIR8UL, 0, 8, 2, unsigned, FALSE), + RL78REL (DIR8UW, 0, 8, 1, unsigned, FALSE), + RL78REL (DIR32_REV, 1, 16, 0, dont, FALSE), + RL78REL (DIR16_REV, 1, 16, 0, dont, FALSE), + RL78REL (DIR3U_PCREL, 0, 3, 0, dont, TRUE), + + EMPTY_HOWTO (0x13), + EMPTY_HOWTO (0x14), + EMPTY_HOWTO (0x15), + EMPTY_HOWTO (0x16), + EMPTY_HOWTO (0x17), + EMPTY_HOWTO (0x18), + EMPTY_HOWTO (0x19), + EMPTY_HOWTO (0x1a), + EMPTY_HOWTO (0x1b), + EMPTY_HOWTO (0x1c), + EMPTY_HOWTO (0x1d), + EMPTY_HOWTO (0x1e), + EMPTY_HOWTO (0x1f), + + EMPTY_HOWTO (0x20), + EMPTY_HOWTO (0x21), + EMPTY_HOWTO (0x22), + EMPTY_HOWTO (0x23), + EMPTY_HOWTO (0x24), + EMPTY_HOWTO (0x25), + EMPTY_HOWTO (0x26), + EMPTY_HOWTO (0x27), + EMPTY_HOWTO (0x28), + EMPTY_HOWTO (0x29), + EMPTY_HOWTO (0x2a), + EMPTY_HOWTO (0x2b), + EMPTY_HOWTO (0x2c), + EMPTY_HOWTO (0x2d), + + EMPTY_HOWTO (0x2e), + EMPTY_HOWTO (0x2f), + EMPTY_HOWTO (0x30), + EMPTY_HOWTO (0x31), + EMPTY_HOWTO (0x32), + EMPTY_HOWTO (0x33), + EMPTY_HOWTO (0x34), + EMPTY_HOWTO (0x35), + EMPTY_HOWTO (0x36), + EMPTY_HOWTO (0x37), + EMPTY_HOWTO (0x38), + EMPTY_HOWTO (0x39), + EMPTY_HOWTO (0x3a), + EMPTY_HOWTO (0x3b), + EMPTY_HOWTO (0x3c), + EMPTY_HOWTO (0x3d), + EMPTY_HOWTO (0x3e), + EMPTY_HOWTO (0x3f), + EMPTY_HOWTO (0x40), + + RL78REL (ABS32, 2, 32, 0, dont, FALSE), + RL78REL (ABS24S, 2, 24, 0, signed, FALSE), + RL78REL (ABS16, 1, 16, 0, dont, FALSE), + RL78REL (ABS16U, 1, 16, 0, unsigned, FALSE), + RL78REL (ABS16S, 1, 16, 0, signed, FALSE), + RL78REL (ABS8, 0, 8, 0, dont, FALSE), + RL78REL (ABS8U, 0, 8, 0, unsigned, FALSE), + RL78REL (ABS8S, 0, 8, 0, signed, FALSE), + RL78REL (ABS24S_PCREL, 2, 24, 0, signed, TRUE), + RL78REL (ABS16S_PCREL, 1, 16, 0, signed, TRUE), + RL78REL (ABS8S_PCREL, 0, 8, 0, signed, TRUE), + RL78REL (ABS16UL, 1, 16, 0, unsigned, FALSE), + RL78REL (ABS16UW, 1, 16, 0, unsigned, FALSE), + RL78REL (ABS8UL, 0, 8, 0, unsigned, FALSE), + RL78REL (ABS8UW, 0, 8, 0, unsigned, FALSE), + RL78REL (ABS32_REV, 2, 32, 0, dont, FALSE), + RL78REL (ABS16_REV, 1, 16, 0, dont, FALSE), + +#define STACK_REL_P(x) ((x) <= R_RL78_ABS16_REV && (x) >= R_RL78_ABS32) + + EMPTY_HOWTO (0x52), + EMPTY_HOWTO (0x53), + EMPTY_HOWTO (0x54), + EMPTY_HOWTO (0x55), + EMPTY_HOWTO (0x56), + EMPTY_HOWTO (0x57), + EMPTY_HOWTO (0x58), + EMPTY_HOWTO (0x59), + EMPTY_HOWTO (0x5a), + EMPTY_HOWTO (0x5b), + EMPTY_HOWTO (0x5c), + EMPTY_HOWTO (0x5d), + EMPTY_HOWTO (0x5e), + EMPTY_HOWTO (0x5f), + EMPTY_HOWTO (0x60), + EMPTY_HOWTO (0x61), + EMPTY_HOWTO (0x62), + EMPTY_HOWTO (0x63), + EMPTY_HOWTO (0x64), + EMPTY_HOWTO (0x65), + EMPTY_HOWTO (0x66), + EMPTY_HOWTO (0x67), + EMPTY_HOWTO (0x68), + EMPTY_HOWTO (0x69), + EMPTY_HOWTO (0x6a), + EMPTY_HOWTO (0x6b), + EMPTY_HOWTO (0x6c), + EMPTY_HOWTO (0x6d), + EMPTY_HOWTO (0x6e), + EMPTY_HOWTO (0x6f), + EMPTY_HOWTO (0x70), + EMPTY_HOWTO (0x71), + EMPTY_HOWTO (0x72), + EMPTY_HOWTO (0x73), + EMPTY_HOWTO (0x74), + EMPTY_HOWTO (0x75), + EMPTY_HOWTO (0x76), + EMPTY_HOWTO (0x77), + + EMPTY_HOWTO (0x78), + EMPTY_HOWTO (0x79), + EMPTY_HOWTO (0x7a), + EMPTY_HOWTO (0x7b), + EMPTY_HOWTO (0x7c), + EMPTY_HOWTO (0x7d), + EMPTY_HOWTO (0x7e), + EMPTY_HOWTO (0x7f), + + RL78REL (SYM, 2, 32, 0, dont, FALSE), + RL78REL (OPneg, 2, 32, 0, dont, FALSE), + RL78REL (OPadd, 2, 32, 0, dont, FALSE), + RL78REL (OPsub, 2, 32, 0, dont, FALSE), + RL78REL (OPmul, 2, 32, 0, dont, FALSE), + RL78REL (OPdiv, 2, 32, 0, dont, FALSE), + RL78REL (OPshla, 2, 32, 0, dont, FALSE), + RL78REL (OPshra, 2, 32, 0, dont, FALSE), + RL78REL (OPsctsize, 2, 32, 0, dont, FALSE), + EMPTY_HOWTO (0x89), + EMPTY_HOWTO (0x8a), + EMPTY_HOWTO (0x8b), + EMPTY_HOWTO (0x8c), + RL78REL (OPscttop, 2, 32, 0, dont, FALSE), + EMPTY_HOWTO (0x8e), + EMPTY_HOWTO (0x8f), + RL78REL (OPand, 2, 32, 0, dont, FALSE), + RL78REL (OPor, 2, 32, 0, dont, FALSE), + RL78REL (OPxor, 2, 32, 0, dont, FALSE), + RL78REL (OPnot, 2, 32, 0, dont, FALSE), + RL78REL (OPmod, 2, 32, 0, dont, FALSE), + RL78REL (OPromtop, 2, 32, 0, dont, FALSE), + RL78REL (OPramtop, 2, 32, 0, dont, FALSE) +}; + +/* Map BFD reloc types to RL78 ELF reloc types. */ + +struct rl78_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int rl78_reloc_val; +}; + +static const struct rl78_reloc_map rl78_reloc_map [] = +{ + { BFD_RELOC_NONE, R_RL78_NONE }, + { BFD_RELOC_8, R_RL78_DIR8S }, + { BFD_RELOC_16, R_RL78_DIR16S }, + { BFD_RELOC_24, R_RL78_DIR24S }, + { BFD_RELOC_32, R_RL78_DIR32 }, + { BFD_RELOC_RL78_16_OP, R_RL78_DIR16 }, + { BFD_RELOC_RL78_DIR3U_PCREL, R_RL78_DIR3U_PCREL }, + { BFD_RELOC_8_PCREL, R_RL78_DIR8S_PCREL }, + { BFD_RELOC_16_PCREL, R_RL78_DIR16S_PCREL }, + { BFD_RELOC_24_PCREL, R_RL78_DIR24S_PCREL }, + { BFD_RELOC_RL78_8U, R_RL78_DIR8U }, + { BFD_RELOC_RL78_16U, R_RL78_DIR16U }, + { BFD_RELOC_RL78_SYM, R_RL78_SYM }, + { BFD_RELOC_RL78_OP_SUBTRACT, R_RL78_OPsub }, + { BFD_RELOC_RL78_OP_NEG, R_RL78_OPneg }, + { BFD_RELOC_RL78_OP_AND, R_RL78_OPand }, + { BFD_RELOC_RL78_OP_SHRA, R_RL78_OPshra }, + { BFD_RELOC_RL78_ABS8, R_RL78_ABS8 }, + { BFD_RELOC_RL78_ABS16, R_RL78_ABS16 }, + { BFD_RELOC_RL78_ABS16_REV, R_RL78_ABS16_REV }, + { BFD_RELOC_RL78_ABS32, R_RL78_ABS32 }, + { BFD_RELOC_RL78_ABS32_REV, R_RL78_ABS32_REV }, + { BFD_RELOC_RL78_ABS16UL, R_RL78_ABS16UL }, + { BFD_RELOC_RL78_ABS16UW, R_RL78_ABS16UW }, + { BFD_RELOC_RL78_ABS16U, R_RL78_ABS16U } +}; + +static reloc_howto_type * +rl78_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + if (code == BFD_RELOC_RL78_32_OP) + return rl78_elf_howto_table + R_RL78_DIR32; + + for (i = ARRAY_SIZE (rl78_reloc_map); --i;) + if (rl78_reloc_map [i].bfd_reloc_val == code) + return rl78_elf_howto_table + rl78_reloc_map[i].rl78_reloc_val; + + return NULL; +} + +static reloc_howto_type * +rl78_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (rl78_elf_howto_table); i++) + if (rl78_elf_howto_table[i].name != NULL + && strcasecmp (rl78_elf_howto_table[i].name, r_name) == 0) + return rl78_elf_howto_table + i; + + return NULL; +} + +/* Set the howto pointer for an RL78 ELF reloc. */ + +static void +rl78_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_RL78_max); + cache_ptr->howto = rl78_elf_howto_table + r_type; +} + +static bfd_vma +get_symbol_value (const char * name, + bfd_reloc_status_type * status, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + int offset) +{ + bfd_vma value = 0; + struct bfd_link_hash_entry * h; + + h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE); + + if (h == NULL + || (h->type != bfd_link_hash_defined + && h->type != bfd_link_hash_defweak)) + * status = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, offset, TRUE); + else + value = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + return value; +} + +static bfd_vma +get_romstart (bfd_reloc_status_type * status, + struct bfd_link_info * info, + bfd * abfd, + asection * sec, + int offset) +{ + static bfd_boolean cached = FALSE; + static bfd_vma cached_value = 0; + + if (!cached) + { + cached_value = get_symbol_value ("_start", status, info, abfd, sec, offset); + cached = TRUE; + } + return cached_value; +} + +static bfd_vma +get_ramstart (bfd_reloc_status_type * status, + struct bfd_link_info * info, + bfd * abfd, + asection * sec, + int offset) +{ + static bfd_boolean cached = FALSE; + static bfd_vma cached_value = 0; + + if (!cached) + { + cached_value = get_symbol_value ("__datastart", status, info, abfd, sec, offset); + cached = TRUE; + } + return cached_value; +} + +#define NUM_STACK_ENTRIES 16 +static int32_t rl78_stack [ NUM_STACK_ENTRIES ]; +static unsigned int rl78_stack_top; + +#define RL78_STACK_PUSH(val) \ + do \ + { \ + if (rl78_stack_top < NUM_STACK_ENTRIES) \ + rl78_stack [rl78_stack_top ++] = (val); \ + else \ + r = bfd_reloc_dangerous; \ + } \ + while (0) + +#define RL78_STACK_POP(dest) \ + do \ + { \ + if (rl78_stack_top > 0) \ + (dest) = rl78_stack [-- rl78_stack_top]; \ + else \ + (dest) = 0, r = bfd_reloc_dangerous; \ + } \ + while (0) + +/* Relocate an RL78 ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocatable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +rl78_elf_relocate_section + (bfd * output_bfd, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + bfd *dynobj; + asection *splt; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + dynobj = elf_hash_table (info)->dynobj; + splt = NULL; + if (dynobj != NULL) + splt = bfd_get_section_by_name (dynobj, ".plt"); + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + bfd_boolean unresolved_reloc = TRUE; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + r_symndx = ELF32_R_SYM (rel->r_info); + + howto = rl78_elf_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + relocation = 0; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + bfd_boolean warned; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, h, + sec, relocation, unresolved_reloc, + warned); + + name = h->root.root.string; + } + + if (sec != NULL && elf_discarded_section (sec)) + RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, + rel, relend, howto, contents); + + if (info->relocatable) + { + /* This is a relocatable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION) + rel->r_addend += sec->output_offset; + continue; + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_RL78_DIR16S: + { + bfd_vma *plt_offset; + + if (h != NULL) + plt_offset = &h->plt.offset; + else + plt_offset = elf_local_got_offsets (input_bfd) + r_symndx; + + /* printf("%s: rel %x plt %d\n", h ? h->root.root.string : "(none)", + relocation, *plt_offset);*/ + if (valid_16bit_address (relocation)) + { + /* If the symbol is in range for a 16-bit address, we should + have deallocated the plt entry in relax_section. */ + BFD_ASSERT (*plt_offset == (bfd_vma) -1); + } + else + { + /* If the symbol is out of range for a 16-bit address, + we must have allocated a plt entry. */ + BFD_ASSERT (*plt_offset != (bfd_vma) -1); + + /* If this is the first time we've processed this symbol, + fill in the plt entry with the correct symbol address. */ + if ((*plt_offset & 1) == 0) + { + unsigned int x; + + x = 0x000000ec; /* br !!abs24 */ + x |= (relocation << 8) & 0xffffff00; + bfd_put_32 (input_bfd, x, splt->contents + *plt_offset); + *plt_offset |= 1; + } + + relocation = (splt->output_section->vma + + splt->output_offset + + (*plt_offset & -2)); + if (name) + { + char *newname = bfd_malloc (strlen(name)+5); + strcpy (newname, name); + strcat(newname, ".plt"); + _bfd_generic_link_add_one_symbol (info, + input_bfd, + newname, + BSF_FUNCTION | BSF_WEAK, + splt, + (*plt_offset & -2), + 0, + 1, + 0, + 0); + } + } + } + break; + } + + if (h != NULL && h->root.type == bfd_link_hash_undefweak) + /* If the symbol is undefined and weak + then the relocation resolves to zero. */ + relocation = 0; + else + { + if (howto->pc_relative) + { + relocation -= (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + relocation -= bfd_get_reloc_size (howto); + } + + relocation += rel->r_addend; + } + + r = bfd_reloc_ok; + +#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow +#define ALIGN(m) if (relocation & m) r = bfd_reloc_other; +#define OP(i) (contents[rel->r_offset + (i)]) + + /* Opcode relocs are always big endian. Data relocs are bi-endian. */ + switch (r_type) + { + case R_RL78_NONE: + break; + + case R_RL78_DIR8S_PCREL: + RANGE (-128, 127); + OP (0) = relocation; + break; + + case R_RL78_DIR8S: + RANGE (-128, 255); + OP (0) = relocation; + break; + + case R_RL78_DIR8U: + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RL78_DIR16S_PCREL: + RANGE (-32768, 32767); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_DIR16S: + if ((relocation & 0xf0000) == 0xf0000) + relocation &= 0xffff; + RANGE (-32768, 65535); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_DIR16U: + RANGE (0, 65536); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_DIR16: + RANGE (-32768, 65536); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_DIR16_REV: + RANGE (-32768, 65536); + OP (1) = relocation; + OP (0) = relocation >> 8; + break; + + case R_RL78_DIR3U_PCREL: + RANGE (3, 10); + OP (0) &= 0xf8; + OP (0) |= relocation & 0x07; + break; + + case R_RL78_DIR24S_PCREL: + RANGE (-0x800000, 0x7fffff); + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + break; + + case R_RL78_DIR24S: + RANGE (-0x800000, 0x7fffff); + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + break; + + case R_RL78_DIR32: + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; + break; + + case R_RL78_DIR32_REV: + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; + break; + + /* Complex reloc handling: */ + + case R_RL78_ABS32: + RL78_STACK_POP (relocation); + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; + break; + + case R_RL78_ABS32_REV: + RL78_STACK_POP (relocation); + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; + break; + + case R_RL78_ABS24S_PCREL: + case R_RL78_ABS24S: + RL78_STACK_POP (relocation); + RANGE (-0x800000, 0x7fffff); + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + break; + + case R_RL78_ABS16: + RL78_STACK_POP (relocation); + RANGE (-32768, 65535); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_ABS16_REV: + RL78_STACK_POP (relocation); + RANGE (-32768, 65535); + OP (1) = relocation; + OP (0) = relocation >> 8; + break; + + case R_RL78_ABS16S_PCREL: + case R_RL78_ABS16S: + RL78_STACK_POP (relocation); + RANGE (-32768, 32767); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_ABS16U: + RL78_STACK_POP (relocation); + RANGE (0, 65536); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_ABS16UL: + RL78_STACK_POP (relocation); + relocation >>= 2; + RANGE (0, 65536); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_ABS16UW: + RL78_STACK_POP (relocation); + relocation >>= 1; + RANGE (0, 65536); + OP (0) = relocation; + OP (1) = relocation >> 8; + break; + + case R_RL78_ABS8: + RL78_STACK_POP (relocation); + RANGE (-128, 255); + OP (0) = relocation; + break; + + case R_RL78_ABS8U: + RL78_STACK_POP (relocation); + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RL78_ABS8UL: + RL78_STACK_POP (relocation); + relocation >>= 2; + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RL78_ABS8UW: + RL78_STACK_POP (relocation); + relocation >>= 1; + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RL78_ABS8S_PCREL: + case R_RL78_ABS8S: + RL78_STACK_POP (relocation); + RANGE (-128, 127); + OP (0) = relocation; + break; + + case R_RL78_SYM: + if (r_symndx < symtab_hdr->sh_info) + RL78_STACK_PUSH (sec->output_section->vma + + sec->output_offset + + sym->st_value + + rel->r_addend); + else + { + if (h != NULL + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) + RL78_STACK_PUSH (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset + + rel->r_addend); + else + _bfd_error_handler (_("Warning: RL78_SYM reloc with an unknown symbol")); + } + break; + + case R_RL78_OPneg: + { + int32_t tmp; + + RL78_STACK_POP (tmp); + tmp = - tmp; + RL78_STACK_PUSH (tmp); + } + break; + + case R_RL78_OPadd: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 += tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPsub: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp2 -= tmp1; + RL78_STACK_PUSH (tmp2); + } + break; + + case R_RL78_OPmul: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 *= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPdiv: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 /= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPshla: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 <<= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPshra: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 >>= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPsctsize: + RL78_STACK_PUSH (input_section->size); + break; + + case R_RL78_OPscttop: + RL78_STACK_PUSH (input_section->output_section->vma); + break; + + case R_RL78_OPand: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 &= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPor: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 |= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPxor: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 ^= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPnot: + { + int32_t tmp; + + RL78_STACK_POP (tmp); + tmp = ~ tmp; + RL78_STACK_PUSH (tmp); + } + break; + + case R_RL78_OPmod: + { + int32_t tmp1, tmp2; + + RL78_STACK_POP (tmp2); + RL78_STACK_POP (tmp1); + tmp1 %= tmp2; + RL78_STACK_PUSH (tmp1); + } + break; + + case R_RL78_OPromtop: + RL78_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + case R_RL78_OPramtop: + RL78_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + default: + r = bfd_reloc_notsupported; + break; + } + + if (r != bfd_reloc_ok) + { + const char * msg = NULL; + + switch (r) + { + case bfd_reloc_overflow: + /* Catch the case of a missing function declaration + and emit a more helpful error message. */ + if (r_type == R_RL78_DIR24S_PCREL) + msg = _("%B(%A): error: call to undefined function '%s'"); + else + r = info->callbacks->reloc_overflow + (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, + TRUE); + break; + + case bfd_reloc_other: + msg = _("%B(%A): warning: unaligned access to symbol '%s' in the small data area"); + break; + + case bfd_reloc_outofrange: + msg = _("%B(%A): internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("%B(%A): internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("%B(%A): internal error: dangerous relocation"); + break; + + default: + msg = _("%B(%A): internal error: unknown error"); + break; + } + + if (msg) + _bfd_error_handler (msg, input_bfd, input_section, name); + + if (! r) + return FALSE; + } + } + + return TRUE; +} + +/* Function to set the ELF flag bits. */ + +static bfd_boolean +rl78_elf_set_private_flags (bfd * abfd, flagword flags) +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +static bfd_boolean no_warn_mismatch = FALSE; + +void bfd_elf32_rl78_set_target_flags (bfd_boolean); + +void +bfd_elf32_rl78_set_target_flags (bfd_boolean user_no_warn_mismatch) +{ + no_warn_mismatch = user_no_warn_mismatch; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +rl78_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) +{ + flagword old_flags; + flagword new_flags; + bfd_boolean error = FALSE; + + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + + if (!elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + + return !error; +} + +static bfd_boolean +rl78_elf_print_private_bfd_data (bfd * abfd, void * ptr) +{ + FILE * file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long) flags); + + fputc ('\n', file); + return TRUE; +} + +/* Return the MACH for an e_flags value. */ + +static int +elf32_rl78_machine (bfd * abfd) +{ + if ((elf_elfheader (abfd)->e_flags & EF_RL78_CPU_MASK) == EF_RL78_CPU_RL78) + return bfd_mach_rl78; + + return 0; +} + +static bfd_boolean +rl78_elf_object_p (bfd * abfd) +{ + bfd_default_set_arch_mach (abfd, bfd_arch_rl78, + elf32_rl78_machine (abfd)); + return TRUE; +} + +#ifdef DEBUG +void +rl78_dump_symtab (bfd * abfd, void * internal_syms, void * external_syms) +{ + size_t locsymcount; + Elf_Internal_Sym * isymbuf; + Elf_Internal_Sym * isymend; + Elf_Internal_Sym * isym; + Elf_Internal_Shdr * symtab_hdr; + bfd_boolean free_internal = FALSE, free_external = FALSE; + char * st_info_str; + char * st_info_stb_str; + char * st_other_str; + char * st_shndx_str; + + if (! internal_syms) + { + internal_syms = bfd_malloc (1000); + free_internal = 1; + } + if (! external_syms) + { + external_syms = bfd_malloc (1000); + free_external = 1; + } + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym; + if (free_internal) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + internal_syms, external_syms, NULL); + else + isymbuf = internal_syms; + isymend = isymbuf + locsymcount; + + for (isym = isymbuf ; isym < isymend ; isym++) + { + switch (ELF_ST_TYPE (isym->st_info)) + { + case STT_FUNC: st_info_str = "STT_FUNC"; + case STT_SECTION: st_info_str = "STT_SECTION"; + case STT_FILE: st_info_str = "STT_FILE"; + case STT_OBJECT: st_info_str = "STT_OBJECT"; + case STT_TLS: st_info_str = "STT_TLS"; + default: st_info_str = ""; + } + switch (ELF_ST_BIND (isym->st_info)) + { + case STB_LOCAL: st_info_stb_str = "STB_LOCAL"; + case STB_GLOBAL: st_info_stb_str = "STB_GLOBAL"; + default: st_info_stb_str = ""; + } + switch (ELF_ST_VISIBILITY (isym->st_other)) + { + case STV_DEFAULT: st_other_str = "STV_DEFAULT"; + case STV_INTERNAL: st_other_str = "STV_INTERNAL"; + case STV_PROTECTED: st_other_str = "STV_PROTECTED"; + default: st_other_str = ""; + } + switch (isym->st_shndx) + { + case SHN_ABS: st_shndx_str = "SHN_ABS"; + case SHN_COMMON: st_shndx_str = "SHN_COMMON"; + case SHN_UNDEF: st_shndx_str = "SHN_UNDEF"; + default: st_shndx_str = ""; + } + + printf ("isym = %p st_value = %lx st_size = %lx st_name = (%lu) %s " + "st_info = (%d) %s %s st_other = (%d) %s st_shndx = (%d) %s\n", + isym, + (unsigned long) isym->st_value, + (unsigned long) isym->st_size, + isym->st_name, + bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link, + isym->st_name), + isym->st_info, st_info_str, st_info_stb_str, + isym->st_other, st_other_str, + isym->st_shndx, st_shndx_str); + } + if (free_internal) + free (internal_syms); + if (free_external) + free (external_syms); +} + +char * +rl78_get_reloc (long reloc) +{ + if (0 <= reloc && reloc < R_RL78_max) + return rl78_elf_howto_table[reloc].name; + return ""; +} +#endif /* DEBUG */ + + +/* support PLT for 16-bit references to 24-bit functions. */ + +/* We support 16-bit pointers to code above 64k by generating a thunk + below 64k containing a JMP instruction to the final address. */ + +static bfd_boolean +rl78_elf_check_relocs + (bfd * abfd, + struct bfd_link_info * info, + asection * sec, + const Elf_Internal_Rela * relocs) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + const Elf_Internal_Rela * rel; + const Elf_Internal_Rela * rel_end; + bfd_vma *local_plt_offsets; + asection *splt; + bfd *dynobj; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + local_plt_offsets = elf_local_got_offsets (abfd); + splt = NULL; + dynobj = elf_hash_table(info)->dynobj; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + bfd_vma *offset; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes a 16-bit pointer to a function. + We may need to allocate a thunk in low memory; reserve memory + for it now. */ + case R_RL78_DIR16S: + if (dynobj == NULL) + elf_hash_table (info)->dynobj = dynobj = abfd; + if (splt == NULL) + { + splt = bfd_get_section_by_name (dynobj, ".plt"); + if (splt == NULL) + { + flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS + | SEC_IN_MEMORY | SEC_LINKER_CREATED + | SEC_READONLY | SEC_CODE); + splt = bfd_make_section_with_flags (dynobj, ".plt", flags); + if (splt == NULL + || ! bfd_set_section_alignment (dynobj, splt, 1)) + return FALSE; + } + } + + if (h != NULL) + offset = &h->plt.offset; + else + { + if (local_plt_offsets == NULL) + { + size_t size; + unsigned int i; + + size = symtab_hdr->sh_info * sizeof (bfd_vma); + local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size); + if (local_plt_offsets == NULL) + return FALSE; + elf_local_got_offsets (abfd) = local_plt_offsets; + + for (i = 0; i < symtab_hdr->sh_info; i++) + local_plt_offsets[i] = (bfd_vma) -1; + } + offset = &local_plt_offsets[r_symndx]; + } + + if (*offset == (bfd_vma) -1) + { + *offset = splt->size; + splt->size += 4; + } + break; + } + } + + return TRUE; +} + +/* This must exist if dynobj is ever set. */ + +static bfd_boolean +rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *splt; + + /* As an extra sanity check, verify that all plt entries have + been filled in. */ + + if ((dynobj = elf_hash_table (info)->dynobj) != NULL + && (splt = bfd_get_section_by_name (dynobj, ".plt")) != NULL) + { + bfd_byte *contents = splt->contents; + unsigned int i, size = splt->size; + for (i = 0; i < size; i += 4) + { + unsigned int x = bfd_get_32 (dynobj, contents + i); + BFD_ASSERT (x != 0); + } + } + + return TRUE; +} + +static bfd_boolean +rl78_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *splt; + + if (info->relocatable) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + if (dynobj == NULL) + return TRUE; + + splt = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (splt != NULL); + + splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size); + if (splt->contents == NULL) + return FALSE; + + return TRUE; +} + + + +/* Handle relaxing. */ + +/* A subroutine of rl78_elf_relax_section. If the global symbol H + is within the low 64k, remove any entry for it in the plt. */ + +struct relax_plt_data +{ + asection *splt; + bfd_boolean *again; +}; + +static bfd_boolean +rl78_relax_plt_check (struct elf_link_hash_entry *h, + PTR xdata) +{ + struct relax_plt_data *data = (struct relax_plt_data *) xdata; + + if (h->plt.offset != (bfd_vma) -1) + { + bfd_vma address; + + if (h->root.type == bfd_link_hash_undefined + || h->root.type == bfd_link_hash_undefweak) + address = 0; + else + address = (h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset + + h->root.u.def.value); + + if (valid_16bit_address (address)) + { + h->plt.offset = -1; + data->splt->size -= 4; + *data->again = TRUE; + } + } + + return TRUE; +} + +/* A subroutine of rl78_elf_relax_section. If the global symbol H + previously had a plt entry, give it a new entry offset. */ + +static bfd_boolean +rl78_relax_plt_realloc (struct elf_link_hash_entry *h, + PTR xdata) +{ + bfd_vma *entry = (bfd_vma *) xdata; + + if (h->plt.offset != (bfd_vma) -1) + { + h->plt.offset = *entry; + *entry += 4; + } + + return TRUE; +} + +static bfd_boolean +rl78_elf_relax_plt_section (bfd *dynobj, + asection *splt, + struct bfd_link_info *info, + bfd_boolean *again) +{ + struct relax_plt_data relax_plt_data; + bfd *ibfd; + + /* Assume nothing changes. */ + *again = FALSE; + + if (info->relocatable) + return TRUE; + + /* We only relax the .plt section at the moment. */ + if (dynobj != elf_hash_table (info)->dynobj + || strcmp (splt->name, ".plt") != 0) + return TRUE; + + /* Quick check for an empty plt. */ + if (splt->size == 0) + return TRUE; + + /* Map across all global symbols; see which ones happen to + fall in the low 64k. */ + relax_plt_data.splt = splt; + relax_plt_data.again = again; + elf_link_hash_traverse (elf_hash_table (info), rl78_relax_plt_check, + &relax_plt_data); + + /* Likewise for local symbols, though that's somewhat less convenient + as we have to walk the list of input bfds and swap in symbol data. */ + for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next) + { + bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd); + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf = NULL; + unsigned int idx; + + if (! local_plt_offsets) + continue; + + symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; + if (symtab_hdr->sh_info != 0) + { + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + if (isymbuf == NULL) + return FALSE; + } + + for (idx = 0; idx < symtab_hdr->sh_info; ++idx) + { + Elf_Internal_Sym *isym; + asection *tsec; + bfd_vma address; + + if (local_plt_offsets[idx] == (bfd_vma) -1) + continue; + + isym = &isymbuf[idx]; + if (isym->st_shndx == SHN_UNDEF) + continue; + else if (isym->st_shndx == SHN_ABS) + tsec = bfd_abs_section_ptr; + else if (isym->st_shndx == SHN_COMMON) + tsec = bfd_com_section_ptr; + else + tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx); + + address = (tsec->output_section->vma + + tsec->output_offset + + isym->st_value); + if (valid_16bit_address (address)) + { + local_plt_offsets[idx] = -1; + splt->size -= 4; + *again = TRUE; + } + } + + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + { + if (! info->keep_memory) + free (isymbuf); + else + { + /* Cache the symbols for elf_link_input_bfd. */ + symtab_hdr->contents = (unsigned char *) isymbuf; + } + } + } + + /* If we changed anything, walk the symbols again to reallocate + .plt entry addresses. */ + if (*again && splt->size > 0) + { + bfd_vma entry = 0; + + elf_link_hash_traverse (elf_hash_table (info), + rl78_relax_plt_realloc, &entry); + + for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next) + { + bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd); + unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info; + unsigned int idx; + + if (! local_plt_offsets) + continue; + + for (idx = 0; idx < nlocals; ++idx) + if (local_plt_offsets[idx] != (bfd_vma) -1) + { + local_plt_offsets[idx] = entry; + entry += 4; + } + } + } + + return TRUE; +} + +static bfd_boolean +rl78_elf_relax_section + (bfd * abfd, + asection * sec, + struct bfd_link_info * link_info, + bfd_boolean * again) +{ + if (abfd == elf_hash_table (link_info)->dynobj + && strcmp (sec->name, ".plt") == 0) + return rl78_elf_relax_plt_section (abfd, sec, link_info, again); + + /* Assume nothing changes. */ + *again = FALSE; + return TRUE; +} + + + +#define ELF_ARCH bfd_arch_rl78 +#define ELF_MACHINE_CODE EM_RL78 +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_LITTLE_SYM bfd_elf32_rl78_vec +#define TARGET_LITTLE_NAME "elf32-rl78" + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto rl78_info_to_howto_rela +#define elf_backend_object_p rl78_elf_object_p +#define elf_backend_relocate_section rl78_elf_relocate_section +#define elf_symbol_leading_char ('_') +#define elf_backend_can_gc_sections 1 + +#define bfd_elf32_bfd_reloc_type_lookup rl78_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup rl78_reloc_name_lookup +#define bfd_elf32_bfd_set_private_flags rl78_elf_set_private_flags +#define bfd_elf32_bfd_merge_private_bfd_data rl78_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data rl78_elf_print_private_bfd_data + +#define bfd_elf32_bfd_relax_section rl78_elf_relax_section +#define elf_backend_check_relocs rl78_elf_check_relocs +#define elf_backend_always_size_sections \ + rl78_elf_always_size_sections +#define elf_backend_finish_dynamic_sections \ + rl78_elf_finish_dynamic_sections + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index ab3e6792984..d08c2ba829d 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1834,6 +1834,38 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_AVR_LDI", "BFD_RELOC_AVR_6", "BFD_RELOC_AVR_6_ADIW", + "BFD_RELOC_RL78_NEG8", + "BFD_RELOC_RL78_NEG16", + "BFD_RELOC_RL78_NEG24", + "BFD_RELOC_RL78_NEG32", + "BFD_RELOC_RL78_16_OP", + "BFD_RELOC_RL78_24_OP", + "BFD_RELOC_RL78_32_OP", + "BFD_RELOC_RL78_8U", + "BFD_RELOC_RL78_16U", + "BFD_RELOC_RL78_24U", + "BFD_RELOC_RL78_DIR3U_PCREL", + "BFD_RELOC_RL78_DIFF", + "BFD_RELOC_RL78_GPRELB", + "BFD_RELOC_RL78_GPRELW", + "BFD_RELOC_RL78_GPRELL", + "BFD_RELOC_RL78_SYM", + "BFD_RELOC_RL78_OP_SUBTRACT", + "BFD_RELOC_RL78_OP_NEG", + "BFD_RELOC_RL78_OP_AND", + "BFD_RELOC_RL78_OP_SHRA", + "BFD_RELOC_RL78_ABS8", + "BFD_RELOC_RL78_ABS16", + "BFD_RELOC_RL78_ABS16_REV", + "BFD_RELOC_RL78_ABS32", + "BFD_RELOC_RL78_ABS32_REV", + "BFD_RELOC_RL78_ABS16U", + "BFD_RELOC_RL78_ABS16UW", + "BFD_RELOC_RL78_ABS16UL", + "BFD_RELOC_RL78_RELAX", + "BFD_RELOC_RL78_HI16", + "BFD_RELOC_RL78_HI8", + "BFD_RELOC_RL78_LO16", "BFD_RELOC_RX_NEG8", "BFD_RELOC_RX_NEG16", "BFD_RELOC_RX_NEG24", diff --git a/bfd/reloc.c b/bfd/reloc.c index 43296499369..e0b5f620ea9 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -4316,6 +4316,73 @@ ENUMDOC instructions ENUM + BFD_RELOC_RL78_NEG8 +ENUMX + BFD_RELOC_RL78_NEG16 +ENUMX + BFD_RELOC_RL78_NEG24 +ENUMX + BFD_RELOC_RL78_NEG32 +ENUMX + BFD_RELOC_RL78_16_OP +ENUMX + BFD_RELOC_RL78_24_OP +ENUMX + BFD_RELOC_RL78_32_OP +ENUMX + BFD_RELOC_RL78_8U +ENUMX + BFD_RELOC_RL78_16U +ENUMX + BFD_RELOC_RL78_24U +ENUMX + BFD_RELOC_RL78_DIR3U_PCREL +ENUMX + BFD_RELOC_RL78_DIFF +ENUMX + BFD_RELOC_RL78_GPRELB +ENUMX + BFD_RELOC_RL78_GPRELW +ENUMX + BFD_RELOC_RL78_GPRELL +ENUMX + BFD_RELOC_RL78_SYM +ENUMX + BFD_RELOC_RL78_OP_SUBTRACT +ENUMX + BFD_RELOC_RL78_OP_NEG +ENUMX + BFD_RELOC_RL78_OP_AND +ENUMX + BFD_RELOC_RL78_OP_SHRA +ENUMX + BFD_RELOC_RL78_ABS8 +ENUMX + BFD_RELOC_RL78_ABS16 +ENUMX + BFD_RELOC_RL78_ABS16_REV +ENUMX + BFD_RELOC_RL78_ABS32 +ENUMX + BFD_RELOC_RL78_ABS32_REV +ENUMX + BFD_RELOC_RL78_ABS16U +ENUMX + BFD_RELOC_RL78_ABS16UW +ENUMX + BFD_RELOC_RL78_ABS16UL +ENUMX + BFD_RELOC_RL78_RELAX +ENUMX + BFD_RELOC_RL78_HI16 +ENUMX + BFD_RELOC_RL78_HI8 +ENUMX + BFD_RELOC_RL78_LO16 +ENUMDOC + Renesas RL78 Relocations. + +ENUM BFD_RELOC_RX_NEG8 ENUMX BFD_RELOC_RX_NEG16 diff --git a/bfd/targets.c b/bfd/targets.c index b6d8116f876..5f4ce9afdab 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -669,6 +669,7 @@ extern const bfd_target bfd_elf32_pjl_vec; extern const bfd_target bfd_elf32_powerpc_vec; extern const bfd_target bfd_elf32_powerpcle_vec; extern const bfd_target bfd_elf32_powerpc_vxworks_vec; +extern const bfd_target bfd_elf32_rl78_vec; extern const bfd_target bfd_elf32_rx_le_vec; extern const bfd_target bfd_elf32_rx_be_vec; extern const bfd_target bfd_elf32_rx_be_ns_vec; @@ -1035,6 +1036,7 @@ static const bfd_target * const _bfd_target_vector[] = &bfd_elf32_powerpc_vec, &bfd_elf32_powerpc_vxworks_vec, &bfd_elf32_powerpcle_vec, + &bfd_elf32_rl78_vec, &bfd_elf32_rx_be_vec, &bfd_elf32_rx_be_ns_vec, &bfd_elf32_rx_le_vec, diff --git a/configure b/configure index eb69f28d59e..c2a51275443 100755 --- a/configure +++ b/configure @@ -3065,6 +3065,10 @@ case "${target}" in powerpc-*-aix* | rs6000-*-aix*) noconfigdirs="$noconfigdirs target-libssp" ;; + rl78-*-*) + # Dereferencing -1 is a compile-time error + noconfigdirs="$noconfigdirs target-libssp" + ;; esac # Disable libstdc++-v3 for some systems. diff --git a/configure.ac b/configure.ac index 337e11d202a..2745bd7d812 100644 --- a/configure.ac +++ b/configure.ac @@ -501,6 +501,10 @@ case "${target}" in powerpc-*-aix* | rs6000-*-aix*) noconfigdirs="$noconfigdirs target-libssp" ;; + rl78-*-*) + # Dereferencing -1 is a compile-time error + noconfigdirs="$noconfigdirs target-libssp" + ;; esac # Disable libstdc++-v3 for some systems. diff --git a/include/ChangeLog b/include/ChangeLog index cec4c43c914..c8af7fb131c 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2011-11-01 DJ Delorie <dj@redhat.com> + + * dis-asm.h (print_insn_rl78): Declare. + 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> * dis-asm.h (print_insn_epiphany): Declare. diff --git a/include/dis-asm.h b/include/dis-asm.h index ff4732568e3..d2334c63c46 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -299,6 +299,7 @@ extern int print_insn_z80 (bfd_vma, disassemble_info *); extern int print_insn_z8001 (bfd_vma, disassemble_info *); extern int print_insn_z8002 (bfd_vma, disassemble_info *); extern int print_insn_rx (bfd_vma, disassemble_info *); +extern int print_insn_rl78 (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index b269004f2f1..c0d38b38e12 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,8 @@ +2011-11-01 DJ Delorie <dj@redhat.com> + + * common.h (EM_RL78, EM_78K0R): New. + * rl78.h: New. + 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> * epiphany.h: New file. diff --git a/include/elf/common.h b/include/elf/common.h index a62db77aa4f..4f20569ec02 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -296,6 +296,8 @@ #define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ #define EM_CUDA 190 /* NVIDIA CUDA architecture */ #define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture family */ +#define EM_RL78 197 /* Renesas RL78 family. */ +#define EM_78K0R 199 /* Renesas 78K0R. */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision diff --git a/include/elf/rl78.h b/include/elf/rl78.h new file mode 100644 index 00000000000..4f29850eea0 --- /dev/null +++ b/include/elf/rl78.h @@ -0,0 +1,118 @@ +/* RL78 ELF support for BFD. + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_RL78_H +#define _ELF_RL78_H + +#include "elf/reloc-macros.h" + +/* Note that there are a few internal relocation types used by the + linker to do link-time relaxation. If you update this file, please + check elf32-rl78.c to see if any of the internal relocations need to + be, er, relocated. */ + +/* Preliminary relocations. */ +START_RELOC_NUMBERS (elf_rl78_reloc_type) + + RELOC_NUMBER (R_RL78_NONE, 0x00) + /* These are for data, and are bi-endian. */ + RELOC_NUMBER (R_RL78_DIR32, 0x01) /* Was: R_RL78_32. */ + RELOC_NUMBER (R_RL78_DIR24S, 0x02) /* Was: R_RL78_24. */ + RELOC_NUMBER (R_RL78_DIR16, 0x03) + RELOC_NUMBER (R_RL78_DIR16U, 0x04) /* Was: R_RL78_16_UNS. */ + RELOC_NUMBER (R_RL78_DIR16S, 0x05) /* Was: R_RL78_16. */ + RELOC_NUMBER (R_RL78_DIR8, 0x06) + RELOC_NUMBER (R_RL78_DIR8U, 0x07) /* Was: R_RL78_8_UNS. */ + RELOC_NUMBER (R_RL78_DIR8S, 0x08) /* Was: R_RL78_8. */ + + /* Signed pc-relative values. */ + RELOC_NUMBER (R_RL78_DIR24S_PCREL, 0x09) /* Was: R_RL78_24_PCREL. */ + RELOC_NUMBER (R_RL78_DIR16S_PCREL, 0x0a) /* Was: R_RL78_16_PCREL. */ + RELOC_NUMBER (R_RL78_DIR8S_PCREL, 0x0b) /* Was: R_RL78_8_PCREL. */ + + /* These are for fields in the instructions. */ + RELOC_NUMBER (R_RL78_DIR16UL, 0x0c) + RELOC_NUMBER (R_RL78_DIR16UW, 0x0d) + RELOC_NUMBER (R_RL78_DIR8UL, 0x0e) + RELOC_NUMBER (R_RL78_DIR8UW, 0x0f) + RELOC_NUMBER (R_RL78_DIR32_REV, 0x10) + RELOC_NUMBER (R_RL78_DIR16_REV, 0x11) + RELOC_NUMBER (R_RL78_DIR3U_PCREL, 0x12) + + /* These are for complex relocs. */ + RELOC_NUMBER (R_RL78_ABS32, 0x41) + RELOC_NUMBER (R_RL78_ABS24S, 0x42) + RELOC_NUMBER (R_RL78_ABS16, 0x43) + RELOC_NUMBER (R_RL78_ABS16U, 0x44) + RELOC_NUMBER (R_RL78_ABS16S, 0x45) + RELOC_NUMBER (R_RL78_ABS8, 0x46) + RELOC_NUMBER (R_RL78_ABS8U, 0x47) + RELOC_NUMBER (R_RL78_ABS8S, 0x48) + RELOC_NUMBER (R_RL78_ABS24S_PCREL, 0x49) + RELOC_NUMBER (R_RL78_ABS16S_PCREL, 0x4a) + RELOC_NUMBER (R_RL78_ABS8S_PCREL, 0x4b) + RELOC_NUMBER (R_RL78_ABS16UL, 0x4c) + RELOC_NUMBER (R_RL78_ABS16UW, 0x4d) + RELOC_NUMBER (R_RL78_ABS8UL, 0x4e) + RELOC_NUMBER (R_RL78_ABS8UW, 0x4f) + RELOC_NUMBER (R_RL78_ABS32_REV, 0x50) + RELOC_NUMBER (R_RL78_ABS16_REV, 0x51) + + RELOC_NUMBER (R_RL78_SYM, 0x80) + RELOC_NUMBER (R_RL78_OPneg, 0x81) + RELOC_NUMBER (R_RL78_OPadd, 0x82) + RELOC_NUMBER (R_RL78_OPsub, 0x83) + RELOC_NUMBER (R_RL78_OPmul, 0x84) + RELOC_NUMBER (R_RL78_OPdiv, 0x85) + RELOC_NUMBER (R_RL78_OPshla, 0x86) + RELOC_NUMBER (R_RL78_OPshra, 0x87) + RELOC_NUMBER (R_RL78_OPsctsize, 0x88) + RELOC_NUMBER (R_RL78_OPscttop, 0x8d) + RELOC_NUMBER (R_RL78_OPand, 0x90) + RELOC_NUMBER (R_RL78_OPor, 0x91) + RELOC_NUMBER (R_RL78_OPxor, 0x92) + RELOC_NUMBER (R_RL78_OPnot, 0x93) + RELOC_NUMBER (R_RL78_OPmod, 0x94) + RELOC_NUMBER (R_RL78_OPromtop, 0x95) + RELOC_NUMBER (R_RL78_OPramtop, 0x96) + +END_RELOC_NUMBERS (R_RL78_max) + +#define EF_RL78_CPU_RL78 0x00000079 /* FIXME: correct value? */ +#define EF_RL78_CPU_MASK 0x0000007F /* specific cpu bits. */ +#define EF_RL78_ALL_FLAGS (EF_RL78_CPU_MASK) + +/* Values for the e_flags field in the ELF header. */ +#define E_FLAG_RL78_64BIT_DOUBLES (1 << 0) +#define E_FLAG_RL78_DSP (1 << 1) /* Defined in the RL78 CPU Object file specification, but not explained. */ + +/* These define the addend field of R_RL78_RH_RELAX relocations. */ +#define RL78_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */ +#define RL78_RELAXA_IMM12 0x00000020 /* Imm8/16/24/32 at bit offset 12. */ +#define RL78_RELAXA_DSP4 0x00000040 /* Dsp0/8/16 at bit offset 4. */ +#define RL78_RELAXA_DSP6 0x00000080 /* Dsp0/8/16 at bit offset 6. */ +#define RL78_RELAXA_DSP14 0x00000100 /* Dsp0/8/16 at bit offset 14. */ +#define RL78_RELAXA_BRA 0x00000200 /* Any type of branch (must be decoded). */ +#define RL78_RELAXA_RNUM 0x0000000f /* Number of associated relocations. */ +/* These mark the place where alignment is requested, and the place where the filler bytes end. */ +#define RL78_RELAXA_ALIGN 0x10000000 /* Start alignment; the remaining bits are the alignment value. */ +#define RL78_RELAXA_ELIGN 0x20000000 /* End alignment; the remaining bits are the alignment value. */ +#define RL78_RELAXA_ANUM 0x00ffffff /* Alignment amount, in bytes (i.e. .balign). */ + +#endif /* _ELF_RL78_H */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b0125ed57b8..dd4a977a686 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2011-11-01 DJ Delorie <dj@redhat.com> + + * rl78.h: New file. + 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com> * mips.h: Fix a typo in description. diff --git a/include/opcode/rl78.h b/include/opcode/rl78.h new file mode 100644 index 00000000000..0f3c64d6272 --- /dev/null +++ b/include/opcode/rl78.h @@ -0,0 +1,168 @@ +/* Opcode decoder for the Renesas RL78 + Copyright 2011 + Free Software Foundation, Inc. + Written by DJ Delorie <dj@redhat.com> + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* The RL78 decoder in libopcodes is used by the simulator, gdb's + analyzer, and the disassembler. Given an opcode data source, it + decodes the next opcode into the following structures. */ + +#ifndef RL78_OPCODES_H_INCLUDED +#define RL78_OPCODES_H_INCLUDED + +/* For the purposes of these structures, the RL78 registers are as + follows, despite most of these being memory-mapped and + bank-switched: */ +typedef enum { + RL78_Reg_None, + /* The order of these matches the encodings. */ + RL78_Reg_X, + RL78_Reg_A, + RL78_Reg_C, + RL78_Reg_B, + RL78_Reg_E, + RL78_Reg_D, + RL78_Reg_L, + RL78_Reg_H, + /* The order of these matches the encodings. */ + RL78_Reg_AX, + RL78_Reg_BC, + RL78_Reg_DE, + RL78_Reg_HL, + /* Unordered. */ + RL78_Reg_SP, + RL78_Reg_PSW, + RL78_Reg_CS, + RL78_Reg_ES, + RL78_Reg_PMC, + RL78_Reg_MEM +} RL78_Register; + +typedef enum +{ + RL78_Byte = 0, + RL78_Word +} RL78_Size; + +typedef enum { + RL78_Condition_T, + RL78_Condition_F, + RL78_Condition_C, + RL78_Condition_NC, + RL78_Condition_H, + RL78_Condition_NH, + RL78_Condition_Z, + RL78_Condition_NZ +} RL78_Condition; + +typedef enum { + RL78_Operand_None = 0, + RL78_Operand_Immediate, /* #addend */ + RL78_Operand_Register, /* reg */ + RL78_Operand_Indirect, /* [reg + reg2 + addend] */ + RL78_Operand_Bit, /* reg.bit */ + RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */ + RL78_Operand_PreDec, /* [--reg] = push */ + RL78_Operand_PostInc /* [reg++] = pop */ +} RL78_Operand_Type; + +typedef enum +{ + RLO_unknown, + RLO_add, /* d += s */ + RLO_addc, /* d += s + CY */ + RLO_and, /* d &= s (byte, word, bit) */ + RLO_branch, /* pc = d */ + RLO_branch_cond, /* pc = d if cond(src) */ + RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */ + RLO_break, /* BRK */ + RLO_call, /* call */ + RLO_cmp, /* cmp d, s */ + RLO_divhu, /* DIVHU */ + RLO_divwu, /* DIVWU */ + RLO_halt, /* HALT */ + RLO_mov, /* d = s */ + RLO_mach, /* MACH */ + RLO_machu, /* MACHU */ + RLO_mulu, /* MULU */ + RLO_mulh, /* MULH */ + RLO_mulhu, /* MULHU */ + RLO_nop, /* NOP */ + RLO_or, /* d |= s */ + RLO_ret, /* RET */ + RLO_reti, /* RETI */ + RLO_rol, /* d <<= s, MSB to LSB and CY */ + RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */ + RLO_ror, /* d >>= s, LSB to MSB and CY */ + RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */ + RLO_sar, /* d >>= s, signed */ + RLO_sel, /* rb = s */ + RLO_shr, /* d >>= s, unsigned */ + RLO_shl, /* d <<= s */ + RLO_skip, /* skip next insn is cond(s) */ + RLO_stop, /* STOP */ + RLO_sub, /* d -= s */ + RLO_subc, /* d -= s - CY */ + RLO_xch, /* swap d, s */ + RLO_xor, /* d ^= s */ +} RL78_Opcode_ID; + +typedef struct { + RL78_Operand_Type type; + int addend; + RL78_Register reg : 8; + RL78_Register reg2 : 8; + unsigned char bit_number : 4; + unsigned char condition : 3; + unsigned char use_es : 1; +} RL78_Opcode_Operand; + +/* PSW flag bits */ +#define RL78_PSW_IE 0x80 +#define RL78_PSW_Z 0x40 +#define RL78_PSW_RBS1 0x20 +#define RL78_PSW_AC 0x10 +#define RL78_PSW_RBS0 0x08 +#define RL78_PSW_ISP1 0x04 +#define RL78_PSW_ISP0 0x02 +#define RL78_PSW_CY 0x01 + +#define RL78_SFR_SP 0xffff8 +#define RL78_SFR_PSW 0xffffa +#define RL78_SFR_CS 0xffffc +#define RL78_SFR_ES 0xffffd +#define RL78_SFR_PMC 0xffffe +#define RL78_SFR_MEM 0xfffff + +typedef struct +{ + int lineno; + RL78_Opcode_ID id:24; + unsigned flags:8; /* PSW mask, for side effects only */ + int n_bytes; + char * syntax; + RL78_Size size; + /* By convention, these are destination, source. */ + RL78_Opcode_Operand op[2]; +} RL78_Opcode_Decoded; + +int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *); + +#endif diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1d057a4f080..965047a2504 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,18 @@ +2011-11-01 DJ Delorie <dj@redhat.com> + + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and + rl78-dis.c. + (MAINTAINERCLEANFILES): Add rl78-decode.c. + (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c. + * Makefile.in: Regenerate. + * configure.in: Add bfd_rl78_arch case. + * configure: Regenerate. + * disassemble.c: Define ARCH_rl78. + (disassembler): Add ARCH_rl78 case. + * rl78-decode.c: New file. + * rl78-decode.opc: New file. + * rl78-dis.c: New file. + 2011-10-27 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq, diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index cae73c2ab60..b377c4d17c9 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -193,6 +193,8 @@ TARGET_LIBOPCODES_CFILES = \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + rl78-decode.c \ + rl78-dis.c \ rx-decode.c \ rx-dis.c \ s390-dis.c \ @@ -482,6 +484,7 @@ MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \ MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \ $(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \ + $(srcdir)/rl78-decode.c \ $(srcdir)/rx-decode.c i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS) @@ -520,6 +523,9 @@ $(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps) ia64-opc.lo: $(srcdir)/ia64-asmtab.c +$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD) + ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c + $(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD) ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 6c2815d8f89..8ae4b841c9e 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -463,6 +463,8 @@ TARGET_LIBOPCODES_CFILES = \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + rl78-decode.c \ + rl78-dis.c \ rx-decode.c \ rx-dis.c \ s390-dis.c \ @@ -605,6 +607,7 @@ MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \ MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \ $(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \ + $(srcdir)/rl78-decode.c \ $(srcdir)/rx-decode.c @@ -846,6 +849,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pj-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rl78-decode.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rl78-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rx-decode.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rx-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/s390-dis.Plo@am__quote@ @@ -1365,6 +1370,9 @@ $(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps) ia64-opc.lo: $(srcdir)/ia64-asmtab.c +$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD) + ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c + $(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD) ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c diff --git a/opcodes/configure b/opcodes/configure index d89ed6a58d4..e9ed6c2571f 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12457,6 +12457,7 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index fc87735f0fa..29854ad55d8 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -271,6 +271,7 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 11f2ea6bca3..0b6313537ca 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -71,6 +71,7 @@ #define ARCH_pj #define ARCH_powerpc #define ARCH_rs6000 +#define ARCH_rl78 #define ARCH_rx #define ARCH_s390 #define ARCH_score @@ -355,6 +356,11 @@ disassembler (abfd) disassemble = print_insn_rs6000; break; #endif +#ifdef ARCH_rl78 + case bfd_arch_rl78: + disassemble = print_insn_rl78; + break; +#endif #ifdef ARCH_rx case bfd_arch_rx: disassemble = print_insn_rx; diff --git a/opcodes/rl78-decode.c b/opcodes/rl78-decode.c new file mode 100644 index 00000000000..d6e2339da20 --- /dev/null +++ b/opcodes/rl78-decode.c @@ -0,0 +1,5731 @@ +#line 1 "rl78-decode.opc" +/* -*- c -*- */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rl78.h" + +static int trace = 0; + +typedef struct +{ + RL78_Opcode_Decoded * rl78; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +#define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__ +#define OP(n,t,r,a) (rl78->op[n].type = t, \ + rl78->op[n].reg = r, \ + rl78->op[n].addend = a ) +#define OPX(n,t,r1,r2,a) \ + (rl78->op[n].type = t, \ + rl78->op[n].reg = r1, \ + rl78->op[n].reg2 = r2, \ + rl78->op[n].addend = a ) + +#define W() rl78->size = RL78_Word + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr)) +#define B ((unsigned long) GETBYTE()) + +#define SYNTAX(x) rl78->syntax = x + +#define UNSUPPORTED() \ + rl78->syntax = "*unknown*" + +#define RB(x) ((x)+RL78_Reg_X) +#define RW(x) ((x)+RL78_Reg_AX) + +#define Fz rl78->flags = RL78_PSW_Z +#define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC +#define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY +#define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY +#define Fa rl78->flags = RL78_PSW_AC +#define Fc rl78->flags = RL78_PSW_CY +#define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY + +#define IMMU(bytes) immediate (bytes, 0, ld) +#define IMMS(bytes) immediate (bytes, 1, ld) + +static int +immediate (int bytes, int sign_extend, LocalData * ld) +{ + unsigned long i = 0; + + switch (bytes) + { + case 1: + i |= B; + if (sign_extend && (i & 0x80)) + i -= 0x100; + break; + case 2: + i |= B; + i |= B << 8; + if (sign_extend && (i & 0x8000)) + i -= 0x10000; + break; + case 3: + i |= B; + i |= B << 8; + i |= B << 16; + if (sign_extend && (i & 0x800000)) + i -= 0x1000000; + break; + default: + fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes); + abort(); + } + return i; +} + +#define DC(c) OP (0, RL78_Operand_Immediate, 0, c) +#define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) +#define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0) +#define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0) +#define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a) +#define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) +#define DE() rl78->op[0].use_es = 1 +#define DB(b) set_bit (rl78->op, b) +#define DCY() DR(PSW); DB(0) +#define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0); + +#define SC(c) OP (1, RL78_Operand_Immediate, 0, c) +#define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0) +#define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0) +#define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0) +#define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a) +#define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) +#define SE() rl78->op[1].use_es = 1 +#define SB(b) set_bit (rl78->op+1, b) +#define SCY() SR(PSW); SB(0) +#define COND(c) rl78->op[1].condition = RL78_Condition_##c +#define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0); + +static void +set_bit (RL78_Opcode_Operand *op, int bit) +{ + op->bit_number = bit; + switch (op->type) { + case RL78_Operand_Register: + op->type = RL78_Operand_Bit; + break; + case RL78_Operand_Indirect: + op->type = RL78_Operand_BitIndirect; + break; + default: + break; + } +} + +static int +saddr (int x) +{ + if (x < 0x20) + return 0xfff00 + x; + return 0xffe00 + x; +} + +static int +sfr (int x) +{ + return 0xfff00 + x; +} + +#define SADDR saddr (IMMU (1)) +#define SFR sfr (IMMU (1)) + +int +rl78_decode_opcode (unsigned long pc AU, + RL78_Opcode_Decoded * rl78, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op_buf[20] = {0}; + unsigned char *op = op_buf; + int op0, op1; + + lds.rl78 = rl78; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rl78, 0, sizeof (*rl78)); + + start_again: + +/* Byte registers, not including A. */ +/* Word registers, not including AX. */ + +/*----------------------------------------------------------------------*/ +/* ES: prefix */ + + GETBYTE (); + switch (op[0] & 0xff) + { + case 0x00: + { + /** 0000 0000 nop */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0000 nop */", + op[0]); + } + SYNTAX("nop"); +#line 887 "rl78-decode.opc" + ID(nop); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x01: + case 0x03: + case 0x05: + case 0x07: + { + /** 0000 0rw1 addw %0, %1 */ +#line 253 "rl78-decode.opc" + int rw AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0rw1 addw %0, %1 */", + op[0]); + printf (" rw = 0x%x\n", rw); + } + SYNTAX("addw %0, %1"); +#line 253 "rl78-decode.opc" + ID(add); W(); DR(AX); SRW(rw); Fzac; + + } + break; + case 0x02: + { + /** 0000 0010 addw %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0010 addw %0, %e1%!1 */", + op[0]); + } + SYNTAX("addw %0, %e1%!1"); +#line 244 "rl78-decode.opc" + ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x04: + { + /** 0000 0100 addw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0100 addw %0, #%1 */", + op[0]); + } + SYNTAX("addw %0, #%1"); +#line 250 "rl78-decode.opc" + ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; + + } + break; + case 0x06: + { + /** 0000 0110 addw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0110 addw %0, %1 */", + op[0]); + } + SYNTAX("addw %0, %1"); +#line 256 "rl78-decode.opc" + ID(add); W(); DR(AX); SM(None, SADDR); Fzac; + + } + break; + case 0x08: + { + /** 0000 1000 xch a, x */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1000 xch a, x */", + op[0]); + } + SYNTAX("xch a, x"); +#line 1205 "rl78-decode.opc" + ID(xch); DR(A); SR(X); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x09: + { + /** 0000 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1001 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 657 "rl78-decode.opc" + ID(mov); DR(A); SM(B, IMMU(2)); + + } + break; + case 0x0a: + { + /** 0000 1010 add %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1010 add %0, #%1 */", + op[0]); + } + SYNTAX("add %0, #%1"); +#line 207 "rl78-decode.opc" + ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x0b: + { + /** 0000 1011 add %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1011 add %0, %1 */", + op[0]); + } + SYNTAX("add %0, %1"); +#line 201 "rl78-decode.opc" + ID(add); DR(A); SM(None, SADDR); Fzac; + + } + break; + case 0x0c: + { + /** 0000 1100 add %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1100 add %0, #%1 */", + op[0]); + } + SYNTAX("add %0, #%1"); +#line 195 "rl78-decode.opc" + ID(add); DR(A); SC(IMMU(1)); Fzac; + + } + break; + case 0x0d: + { + /** 0000 1101 add %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1101 add %0, %e1%1 */", + op[0]); + } + SYNTAX("add %0, %e1%1"); +#line 183 "rl78-decode.opc" + ID(add); DR(A); SM(HL, 0); Fzac; + + } + break; + case 0x0e: + { + /** 0000 1110 add %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1110 add %0, %e1%1 */", + op[0]); + } + SYNTAX("add %0, %e1%1"); +#line 189 "rl78-decode.opc" + ID(add); DR(A); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x0f: + { + /** 0000 1111 add %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1111 add %0, %e1%!1 */", + op[0]); + } + SYNTAX("add %0, %e1%!1"); +#line 180 "rl78-decode.opc" + ID(add); DR(A); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x10: + { + /** 0001 0000 addw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 0000 addw %0, #%1 */", + op[0]); + } + SYNTAX("addw %0, #%1"); +#line 259 "rl78-decode.opc" + ID(add); W(); DR(SP); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x11: + { + /** 0001 0001 es: */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 0001 es: */", + op[0]); + } + SYNTAX("es:"); +#line 172 "rl78-decode.opc" + DE(); SE(); + op ++; + pc ++; + goto start_again; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x12: + case 0x14: + case 0x16: + { + /** 0001 0ra0 movw %0, %1 */ +#line 835 "rl78-decode.opc" + int ra AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 0ra0 movw %0, %1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("movw %0, %1"); +#line 835 "rl78-decode.opc" + ID(mov); W(); DRW(ra); SR(AX); + + } + break; + case 0x13: + case 0x15: + case 0x17: + { + /** 0001 0ra1 movw %0, %1 */ +#line 832 "rl78-decode.opc" + int ra AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 0ra1 movw %0, %1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("movw %0, %1"); +#line 832 "rl78-decode.opc" + ID(mov); W(); DR(AX); SRW(ra); + + } + break; + case 0x18: + { + /** 0001 1000 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1000 mov %e0%0, %1 */", + op[0]); + } + SYNTAX("mov %e0%0, %1"); +#line 708 "rl78-decode.opc" + ID(mov); DM(B, IMMU(2)); SR(A); + + } + break; + case 0x19: + { + /** 0001 1001 mov %e0%0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1001 mov %e0%0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%0, #%1"); +#line 705 "rl78-decode.opc" + ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); + + } + break; + case 0x1a: + { + /** 0001 1010 addc %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1010 addc %0, #%1 */", + op[0]); + } + SYNTAX("addc %0, #%1"); +#line 239 "rl78-decode.opc" + ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x1b: + { + /** 0001 1011 addc %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1011 addc %0, %1 */", + op[0]); + } + SYNTAX("addc %0, %1"); +#line 236 "rl78-decode.opc" + ID(addc); DR(A); SM(None, SADDR); Fzac; + + } + break; + case 0x1c: + { + /** 0001 1100 addc %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1100 addc %0, #%1 */", + op[0]); + } + SYNTAX("addc %0, #%1"); +#line 227 "rl78-decode.opc" + ID(addc); DR(A); SC(IMMU(1)); Fzac; + + } + break; + case 0x1d: + { + /** 0001 1101 addc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1101 addc %0, %e1%1 */", + op[0]); + } + SYNTAX("addc %0, %e1%1"); +#line 215 "rl78-decode.opc" + ID(addc); DR(A); SM(HL, 0); Fzac; + + } + break; + case 0x1e: + { + /** 0001 1110 addc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1110 addc %0, %e1%1 */", + op[0]); + } + SYNTAX("addc %0, %e1%1"); +#line 224 "rl78-decode.opc" + ID(addc); DR(A); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x1f: + { + /** 0001 1111 addc %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 1111 addc %0, %e1%!1 */", + op[0]); + } + SYNTAX("addc %0, %e1%!1"); +#line 212 "rl78-decode.opc" + ID(addc); DR(A); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x20: + { + /** 0010 0000 subw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 0000 subw %0, #%1 */", + op[0]); + } + SYNTAX("subw %0, #%1"); +#line 1169 "rl78-decode.opc" + ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x21: + case 0x23: + case 0x25: + case 0x27: + { + /** 0010 0rw1 subw %0, %1 */ +#line 1163 "rl78-decode.opc" + int rw AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 0rw1 subw %0, %1 */", + op[0]); + printf (" rw = 0x%x\n", rw); + } + SYNTAX("subw %0, %1"); +#line 1163 "rl78-decode.opc" + ID(sub); W(); DR(AX); SRW(rw); Fzac; + + } + break; + case 0x22: + { + /** 0010 0010 subw %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 0010 subw %0, %e1%!1 */", + op[0]); + } + SYNTAX("subw %0, %e1%!1"); +#line 1154 "rl78-decode.opc" + ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x24: + { + /** 0010 0100 subw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 0100 subw %0, #%1 */", + op[0]); + } + SYNTAX("subw %0, #%1"); +#line 1160 "rl78-decode.opc" + ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac; + + } + break; + case 0x26: + { + /** 0010 0110 subw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 0110 subw %0, %1 */", + op[0]); + } + SYNTAX("subw %0, %1"); +#line 1166 "rl78-decode.opc" + ID(sub); W(); DR(AX); SM(None, SADDR); Fzac; + + } + break; + case 0x28: + { + /** 0010 1000 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1000 mov %e0%0, %1 */", + op[0]); + } + SYNTAX("mov %e0%0, %1"); +#line 720 "rl78-decode.opc" + ID(mov); DM(C, IMMU(2)); SR(A); + + } + break; + case 0x29: + { + /** 0010 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1001 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 663 "rl78-decode.opc" + ID(mov); DR(A); SM(C, IMMU(2)); + + } + break; + case 0x2a: + { + /** 0010 1010 sub %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1010 sub %0, #%1 */", + op[0]); + } + SYNTAX("sub %0, #%1"); +#line 1117 "rl78-decode.opc" + ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x2b: + { + /** 0010 1011 sub %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1011 sub %0, %1 */", + op[0]); + } + SYNTAX("sub %0, %1"); +#line 1111 "rl78-decode.opc" + ID(sub); DR(A); SM(None, SADDR); Fzac; + + } + break; + case 0x2c: + { + /** 0010 1100 sub %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1100 sub %0, #%1 */", + op[0]); + } + SYNTAX("sub %0, #%1"); +#line 1105 "rl78-decode.opc" + ID(sub); DR(A); SC(IMMU(1)); Fzac; + + } + break; + case 0x2d: + { + /** 0010 1101 sub %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1101 sub %0, %e1%1 */", + op[0]); + } + SYNTAX("sub %0, %e1%1"); +#line 1093 "rl78-decode.opc" + ID(sub); DR(A); SM(HL, 0); Fzac; + + } + break; + case 0x2e: + { + /** 0010 1110 sub %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1110 sub %0, %e1%1 */", + op[0]); + } + SYNTAX("sub %0, %e1%1"); +#line 1099 "rl78-decode.opc" + ID(sub); DR(A); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x2f: + { + /** 0010 1111 sub %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1111 sub %0, %e1%!1 */", + op[0]); + } + SYNTAX("sub %0, %e1%!1"); +#line 1090 "rl78-decode.opc" + ID(sub); DR(A); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x30: + case 0x32: + case 0x34: + case 0x36: + { + /** 0011 0rg0 movw %0, #%1 */ +#line 829 "rl78-decode.opc" + int rg AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 0rg0 movw %0, #%1 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("movw %0, #%1"); +#line 829 "rl78-decode.opc" + ID(mov); W(); DRW(rg); SC(IMMU(2)); + + } + break; + case 0x31: + GETBYTE (); + switch (op[1] & 0x8f) + { + case 0x00: + { + /** 0011 0001 0bit 0000 btclr %s1, $%a0 */ +#line 395 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0000 btclr %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btclr %s1, $%a0"); +#line 395 "rl78-decode.opc" + ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x01: + { + /** 0011 0001 0bit 0001 btclr %1, $%a0 */ +#line 389 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0001 btclr %1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btclr %1, $%a0"); +#line 389 "rl78-decode.opc" + ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); + + } + break; + case 0x02: + { + /** 0011 0001 0bit 0010 bt %s1, $%a0 */ +#line 381 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0010 bt %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bt %s1, $%a0"); +#line 381 "rl78-decode.opc" + ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x03: + { + /** 0011 0001 0bit 0011 bt %1, $%a0 */ +#line 375 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0011 bt %1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bt %1, $%a0"); +#line 375 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); + + } + break; + case 0x04: + { + /** 0011 0001 0bit 0100 bf %s1, $%a0 */ +#line 342 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0100 bf %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bf %s1, $%a0"); +#line 342 "rl78-decode.opc" + ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x05: + { + /** 0011 0001 0bit 0101 bf %1, $%a0 */ +#line 336 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0bit 0101 bf %1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bf %1, $%a0"); +#line 336 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); + + } + break; + case 0x07: + { + /** 0011 0001 0cnt 0111 shl %0, %1 */ +#line 1046 "rl78-decode.opc" + int cnt AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0cnt 0111 shl %0, %1 */", + op[0], op[1]); + printf (" cnt = 0x%x\n", cnt); + } + SYNTAX("shl %0, %1"); +#line 1046 "rl78-decode.opc" + ID(shl); DR(C); SC(cnt); + + } + break; + case 0x08: + { + /** 0011 0001 0cnt 1000 shl %0, %1 */ +#line 1043 "rl78-decode.opc" + int cnt AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0cnt 1000 shl %0, %1 */", + op[0], op[1]); + printf (" cnt = 0x%x\n", cnt); + } + SYNTAX("shl %0, %1"); +#line 1043 "rl78-decode.opc" + ID(shl); DR(B); SC(cnt); + + } + break; + case 0x09: + { + /** 0011 0001 0cnt 1001 shl %0, %1 */ +#line 1040 "rl78-decode.opc" + int cnt AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0cnt 1001 shl %0, %1 */", + op[0], op[1]); + printf (" cnt = 0x%x\n", cnt); + } + SYNTAX("shl %0, %1"); +#line 1040 "rl78-decode.opc" + ID(shl); DR(A); SC(cnt); + + } + break; + case 0x0a: + { + /** 0011 0001 0cnt 1010 shr %0, %1 */ +#line 1057 "rl78-decode.opc" + int cnt AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0cnt 1010 shr %0, %1 */", + op[0], op[1]); + printf (" cnt = 0x%x\n", cnt); + } + SYNTAX("shr %0, %1"); +#line 1057 "rl78-decode.opc" + ID(shr); DR(A); SC(cnt); + + } + break; + case 0x0b: + { + /** 0011 0001 0cnt 1011 sar %0, %1 */ +#line 1004 "rl78-decode.opc" + int cnt AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 0cnt 1011 sar %0, %1 */", + op[0], op[1]); + printf (" cnt = 0x%x\n", cnt); + } + SYNTAX("sar %0, %1"); +#line 1004 "rl78-decode.opc" + ID(sar); DR(A); SC(cnt); + + } + break; + case 0x0c: + case 0x8c: + { + /** 0011 0001 wcnt 1100 shlw %0, %1 */ +#line 1052 "rl78-decode.opc" + int wcnt AU = (op[1] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 wcnt 1100 shlw %0, %1 */", + op[0], op[1]); + printf (" wcnt = 0x%x\n", wcnt); + } + SYNTAX("shlw %0, %1"); +#line 1052 "rl78-decode.opc" + ID(shl); W(); DR(BC); SC(wcnt); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x0d: + case 0x8d: + { + /** 0011 0001 wcnt 1101 shlw %0, %1 */ +#line 1049 "rl78-decode.opc" + int wcnt AU = (op[1] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 wcnt 1101 shlw %0, %1 */", + op[0], op[1]); + printf (" wcnt = 0x%x\n", wcnt); + } + SYNTAX("shlw %0, %1"); +#line 1049 "rl78-decode.opc" + ID(shl); W(); DR(AX); SC(wcnt); + + } + break; + case 0x0e: + case 0x8e: + { + /** 0011 0001 wcnt 1110 shrw %0, %1 */ +#line 1060 "rl78-decode.opc" + int wcnt AU = (op[1] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 wcnt 1110 shrw %0, %1 */", + op[0], op[1]); + printf (" wcnt = 0x%x\n", wcnt); + } + SYNTAX("shrw %0, %1"); +#line 1060 "rl78-decode.opc" + ID(shr); W(); DR(AX); SC(wcnt); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x0f: + case 0x8f: + { + /** 0011 0001 wcnt 1111 sarw %0, %1 */ +#line 1007 "rl78-decode.opc" + int wcnt AU = (op[1] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 wcnt 1111 sarw %0, %1 */", + op[0], op[1]); + printf (" wcnt = 0x%x\n", wcnt); + } + SYNTAX("sarw %0, %1"); +#line 1007 "rl78-decode.opc" + ID(sar); W(); DR(AX); SC(wcnt); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x80: + { + /** 0011 0001 1bit 0000 btclr %s1, $%a0 */ +#line 392 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0000 btclr %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btclr %s1, $%a0"); +#line 392 "rl78-decode.opc" + ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + + } + break; + case 0x81: + { + /** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */ +#line 386 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btclr %e1%1, $%a0"); +#line 386 "rl78-decode.opc" + ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); + + } + break; + case 0x82: + { + /** 0011 0001 1bit 0010 bt %s1, $%a0 */ +#line 378 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0010 bt %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bt %s1, $%a0"); +#line 378 "rl78-decode.opc" + ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + + } + break; + case 0x83: + { + /** 0011 0001 1bit 0011 bt %e1%1, $%a0 */ +#line 372 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bt %e1%1, $%a0"); +#line 372 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); + + } + break; + case 0x84: + { + /** 0011 0001 1bit 0100 bf %s1, $%a0 */ +#line 339 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0100 bf %s1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bf %s1, $%a0"); +#line 339 "rl78-decode.opc" + ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F); + + } + break; + case 0x85: + { + /** 0011 0001 1bit 0101 bf %e1%1, $%a0 */ +#line 333 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bf %e1%1, $%a0"); +#line 333 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x33: + case 0x35: + case 0x37: + { + /** 0011 0ra1 xchw %0, %1 */ +#line 1210 "rl78-decode.opc" + int ra AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 0ra1 xchw %0, %1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("xchw %0, %1"); +#line 1210 "rl78-decode.opc" + ID(xch); W(); DR(AX); SRW(ra); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x38: + { + /** 0011 1000 mov %e0%0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1000 mov %e0%0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%0, #%1"); +#line 717 "rl78-decode.opc" + ID(mov); DM(C, IMMU(2)); SC(IMMU(1)); + + } + break; + case 0x39: + { + /** 0011 1001 mov %e0%0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1001 mov %e0%0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%0, #%1"); +#line 711 "rl78-decode.opc" + ID(mov); DM(BC, IMMU(2)); SC(IMMU(1)); + + } + break; + case 0x3a: + { + /** 0011 1010 subc %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1010 subc %0, #%1 */", + op[0]); + } + SYNTAX("subc %0, #%1"); +#line 1149 "rl78-decode.opc" + ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x3b: + { + /** 0011 1011 subc %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1011 subc %0, %1 */", + op[0]); + } + SYNTAX("subc %0, %1"); +#line 1146 "rl78-decode.opc" + ID(subc); DR(A); SM(None, SADDR); Fzac; + + } + break; + case 0x3c: + { + /** 0011 1100 subc %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1100 subc %0, #%1 */", + op[0]); + } + SYNTAX("subc %0, #%1"); +#line 1137 "rl78-decode.opc" + ID(subc); DR(A); SC(IMMU(1)); Fzac; + + } + break; + case 0x3d: + { + /** 0011 1101 subc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1101 subc %0, %e1%1 */", + op[0]); + } + SYNTAX("subc %0, %e1%1"); +#line 1125 "rl78-decode.opc" + ID(subc); DR(A); SM(HL, 0); Fzac; + + } + break; + case 0x3e: + { + /** 0011 1110 subc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1110 subc %0, %e1%1 */", + op[0]); + } + SYNTAX("subc %0, %e1%1"); +#line 1134 "rl78-decode.opc" + ID(subc); DR(A); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x3f: + { + /** 0011 1111 subc %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1111 subc %0, %e1%!1 */", + op[0]); + } + SYNTAX("subc %0, %e1%!1"); +#line 1122 "rl78-decode.opc" + ID(subc); DR(A); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x40: + { + /** 0100 0000 cmp %e0%!0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0000 cmp %e0%!0, #%1 */", + op[0]); + } + SYNTAX("cmp %e0%!0, #%1"); +#line 459 "rl78-decode.opc" + ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac; + + } + break; + case 0x41: + { + /** 0100 0001 mov %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0001 mov %0, #%1 */", + op[0]); + } + SYNTAX("mov %0, #%1"); +#line 696 "rl78-decode.opc" + ID(mov); DR(ES); SC(IMMU(1)); + + } + break; + case 0x42: + { + /** 0100 0010 cmpw %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0010 cmpw %0, %e1%!1 */", + op[0]); + } + SYNTAX("cmpw %0, %e1%!1"); +#line 510 "rl78-decode.opc" + ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x43: + case 0x45: + case 0x47: + { + /** 0100 0ra1 cmpw %0, %1 */ +#line 519 "rl78-decode.opc" + int ra AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0ra1 cmpw %0, %1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("cmpw %0, %1"); +#line 519 "rl78-decode.opc" + ID(cmp); W(); DR(AX); SRW(ra); Fzac; + + } + break; + case 0x44: + { + /** 0100 0100 cmpw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0100 cmpw %0, #%1 */", + op[0]); + } + SYNTAX("cmpw %0, #%1"); +#line 516 "rl78-decode.opc" + ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac; + + } + break; + case 0x46: + { + /** 0100 0110 cmpw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 0110 cmpw %0, %1 */", + op[0]); + } + SYNTAX("cmpw %0, %1"); +#line 522 "rl78-decode.opc" + ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x48: + { + /** 0100 1000 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1000 mov %e0%0, %1 */", + op[0]); + } + SYNTAX("mov %e0%0, %1"); +#line 714 "rl78-decode.opc" + ID(mov); DM(BC, IMMU(2)); SR(A); + + } + break; + case 0x49: + { + /** 0100 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1001 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 660 "rl78-decode.opc" + ID(mov); DR(A); SM(BC, IMMU(2)); + + } + break; + case 0x4a: + { + /** 0100 1010 cmp %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1010 cmp %0, #%1 */", + op[0]); + } + SYNTAX("cmp %0, #%1"); +#line 462 "rl78-decode.opc" + ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac; + + } + break; + case 0x4b: + { + /** 0100 1011 cmp %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1011 cmp %0, %1 */", + op[0]); + } + SYNTAX("cmp %0, %1"); +#line 489 "rl78-decode.opc" + ID(cmp); DR(A); SM(None, SADDR); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x4c: + { + /** 0100 1100 cmp %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1100 cmp %0, #%1 */", + op[0]); + } + SYNTAX("cmp %0, #%1"); +#line 480 "rl78-decode.opc" + ID(cmp); DR(A); SC(IMMU(1)); Fzac; + + } + break; + case 0x4d: + { + /** 0100 1101 cmp %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1101 cmp %0, %e1%1 */", + op[0]); + } + SYNTAX("cmp %0, %e1%1"); +#line 468 "rl78-decode.opc" + ID(cmp); DR(A); SM(HL, 0); Fzac; + + } + break; + case 0x4e: + { + /** 0100 1110 cmp %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1110 cmp %0, %e1%1 */", + op[0]); + } + SYNTAX("cmp %0, %e1%1"); +#line 477 "rl78-decode.opc" + ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x4f: + { + /** 0100 1111 cmp %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0100 1111 cmp %0, %e1%!1 */", + op[0]); + } + SYNTAX("cmp %0, %e1%!1"); +#line 465 "rl78-decode.opc" + ID(cmp); DR(A); SM(None, IMMU(2)); Fzac; + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + { + /** 0101 0reg mov %0, #%1 */ +#line 648 "rl78-decode.opc" + int reg AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 0reg mov %0, #%1 */", + op[0]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("mov %0, #%1"); +#line 648 "rl78-decode.opc" + ID(mov); DRB(reg); SC(IMMU(1)); + + } + break; + case 0x58: + { + /** 0101 1000 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1000 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 847 "rl78-decode.opc" + ID(mov); W(); DM(B, IMMU(2)); SR(AX); + + } + break; + case 0x59: + { + /** 0101 1001 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1001 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 838 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(B, IMMU(2)); + + } + break; + case 0x5a: + { + /** 0101 1010 and %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1010 and %0, #%1 */", + op[0]); + } + SYNTAX("and %0, #%1"); +#line 291 "rl78-decode.opc" + ID(and); DM(None, SADDR); SC(IMMU(1)); Fz; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x5b: + { + /** 0101 1011 and %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1011 and %0, %1 */", + op[0]); + } + SYNTAX("and %0, %1"); +#line 288 "rl78-decode.opc" + ID(and); DR(A); SM(None, SADDR); Fz; + + } + break; + case 0x5c: + { + /** 0101 1100 and %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1100 and %0, #%1 */", + op[0]); + } + SYNTAX("and %0, #%1"); +#line 279 "rl78-decode.opc" + ID(and); DR(A); SC(IMMU(1)); Fz; + + } + break; + case 0x5d: + { + /** 0101 1101 and %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1101 and %0, %e1%1 */", + op[0]); + } + SYNTAX("and %0, %e1%1"); +#line 267 "rl78-decode.opc" + ID(and); DR(A); SM(HL, 0); Fz; + + } + break; + case 0x5e: + { + /** 0101 1110 and %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1110 and %0, %e1%1 */", + op[0]); + } + SYNTAX("and %0, %e1%1"); +#line 273 "rl78-decode.opc" + ID(and); DR(A); SM(HL, IMMU(1)); Fz; + + } + break; + case 0x5f: + { + /** 0101 1111 and %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0101 1111 and %0, %e1%!1 */", + op[0]); + } + SYNTAX("and %0, %e1%!1"); +#line 264 "rl78-decode.opc" + ID(and); DR(A); SM(None, IMMU(2)); Fz; + + } + break; + case 0x60: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + case 0x66: + case 0x67: + { + /** 0110 0rba mov %0, %1 */ +#line 651 "rl78-decode.opc" + int rba AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 0rba mov %0, %1 */", + op[0]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("mov %0, %1"); +#line 651 "rl78-decode.opc" + ID(mov); DR(A); SRB(rba); + + } + break; + case 0x61: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + { + /** 0110 0001 0000 0reg add %0, %1 */ +#line 204 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0000 0reg add %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("add %0, %1"); +#line 204 "rl78-decode.opc" + ID(add); DRB(reg); SR(A); Fzac; + + } + break; + case 0x08: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + { + /** 0110 0001 0000 1rba add %0, %1 */ +#line 198 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0000 1rba add %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("add %0, %1"); +#line 198 "rl78-decode.opc" + ID(add); DR(A); SRB(rba); Fzac; + + } + break; + case 0x09: + { + /** 0110 0001 0000 1001 addw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0000 1001 addw %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("addw %0, %e1%1"); +#line 247 "rl78-decode.opc" + ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + { + /** 0110 0001 0001 0reg addc %0, %1 */ +#line 233 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0001 0reg addc %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("addc %0, %1"); +#line 233 "rl78-decode.opc" + ID(addc); DRB(reg); SR(A); Fzac; + + } + break; + case 0x18: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + /** 0110 0001 0001 1rba addc %0, %1 */ +#line 230 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0001 1rba addc %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("addc %0, %1"); +#line 230 "rl78-decode.opc" + ID(addc); DR(A); SRB(rba); Fzac; + + } + break; + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + { + /** 0110 0001 0010 0reg sub %0, %1 */ +#line 1114 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0010 0reg sub %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("sub %0, %1"); +#line 1114 "rl78-decode.opc" + ID(sub); DRB(reg); SR(A); Fzac; + + } + break; + case 0x28: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + { + /** 0110 0001 0010 1rba sub %0, %1 */ +#line 1108 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0010 1rba sub %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("sub %0, %1"); +#line 1108 "rl78-decode.opc" + ID(sub); DR(A); SRB(rba); Fzac; + + } + break; + case 0x29: + { + /** 0110 0001 0010 1001 subw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0010 1001 subw %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("subw %0, %e1%1"); +#line 1157 "rl78-decode.opc" + ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + { + /** 0110 0001 0011 0reg subc %0, %1 */ +#line 1143 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0011 0reg subc %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("subc %0, %1"); +#line 1143 "rl78-decode.opc" + ID(subc); DRB(reg); SR(A); Fzac; + + } + break; + case 0x38: + case 0x3a: + case 0x3b: + case 0x3c: + case 0x3d: + case 0x3e: + case 0x3f: + { + /** 0110 0001 0011 1rba subc %0, %1 */ +#line 1140 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0011 1rba subc %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("subc %0, %1"); +#line 1140 "rl78-decode.opc" + ID(subc); DR(A); SRB(rba); Fzac; + + } + break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + { + /** 0110 0001 0100 0reg cmp %0, %1 */ +#line 486 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0100 0reg cmp %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("cmp %0, %1"); +#line 486 "rl78-decode.opc" + ID(cmp); DRB(reg); SR(A); Fzac; + + } + break; + case 0x48: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + { + /** 0110 0001 0100 1rba cmp %0, %1 */ +#line 483 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0100 1rba cmp %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("cmp %0, %1"); +#line 483 "rl78-decode.opc" + ID(cmp); DR(A); SRB(rba); Fzac; + + } + break; + case 0x49: + { + /** 0110 0001 0100 1001 cmpw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0100 1001 cmpw %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("cmpw %0, %e1%1"); +#line 513 "rl78-decode.opc" + ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + { + /** 0110 0001 0101 0reg and %0, %1 */ +#line 285 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0101 0reg and %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("and %0, %1"); +#line 285 "rl78-decode.opc" + ID(and); DRB(reg); SR(A); Fz; + + } + break; + case 0x58: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + { + /** 0110 0001 0101 1rba and %0, %1 */ +#line 282 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0101 1rba and %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("and %0, %1"); +#line 282 "rl78-decode.opc" + ID(and); DR(A); SRB(rba); Fz; + + } + break; + case 0x59: + { + /** 0110 0001 0101 1001 inc %e0%0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0101 1001 inc %e0%0 */", + op[0], op[1]); + } + SYNTAX("inc %e0%0"); +#line 563 "rl78-decode.opc" + ID(add); DM(HL, IMMU(1)); SC(1); Fza; + + } + break; + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + case 0x66: + case 0x67: + { + /** 0110 0001 0110 0reg or %0, %1 */ +#line 932 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0110 0reg or %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("or %0, %1"); +#line 932 "rl78-decode.opc" + ID(or); DRB(reg); SR(A); Fz; + + } + break; + case 0x68: + case 0x6a: + case 0x6b: + case 0x6c: + case 0x6d: + case 0x6e: + case 0x6f: + { + /** 0110 0001 0110 1rba or %0, %1 */ +#line 929 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0110 1rba or %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("or %0, %1"); +#line 929 "rl78-decode.opc" + ID(or); DR(A); SRB(rba); Fz; + + } + break; + case 0x69: + { + /** 0110 0001 0110 1001 dec %e0%0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0110 1001 dec %e0%0 */", + op[0], op[1]); + } + SYNTAX("dec %e0%0"); +#line 530 "rl78-decode.opc" + ID(sub); DM(HL, IMMU(1)); SC(1); Fza; + + } + break; + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x76: + case 0x77: + { + /** 0110 0001 0111 0reg xor %0, %1 */ +#line 1236 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0111 0reg xor %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("xor %0, %1"); +#line 1236 "rl78-decode.opc" + ID(xor); DRB(reg); SR(A); Fz; + + } + break; + case 0x78: + case 0x7a: + case 0x7b: + case 0x7c: + case 0x7d: + case 0x7e: + case 0x7f: + { + /** 0110 0001 0111 1rba xor %0, %1 */ +#line 1233 "rl78-decode.opc" + int rba AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0111 1rba xor %0, %1 */", + op[0], op[1]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("xor %0, %1"); +#line 1233 "rl78-decode.opc" + ID(xor); DR(A); SRB(rba); Fz; + + } + break; + case 0x79: + { + /** 0110 0001 0111 1001 incw %e0%0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 0111 1001 incw %e0%0 */", + op[0], op[1]); + } + SYNTAX("incw %e0%0"); +#line 577 "rl78-decode.opc" + ID(add); W(); DM(HL, IMMU(1)); SC(1); + + } + break; + case 0x80: + case 0x81: + { + /** 0110 0001 1000 000 add %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1000 000 add %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("add %0, %e1%1"); +#line 186 "rl78-decode.opc" + ID(add); DR(A); SM2(HL, B, 0); Fzac; + + } + break; + case 0x82: + { + /** 0110 0001 1000 0010 add %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1000 0010 add %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("add %0, %e1%1"); +#line 192 "rl78-decode.opc" + ID(add); DR(A); SM2(HL, C, 0); Fzac; + + } + break; + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x94: + case 0x95: + case 0x96: + case 0x97: + case 0xa4: + case 0xa5: + case 0xa6: + case 0xa7: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + case 0xc4: + case 0xc5: + case 0xc6: + case 0xc7: + case 0xd4: + case 0xd5: + case 0xd6: + case 0xd7: + case 0xe4: + case 0xe5: + case 0xe6: + case 0xe7: + case 0xf4: + case 0xf5: + case 0xf6: + case 0xf7: + { + /** 0110 0001 1nnn 01mm callt [%x0] */ +#line 412 "rl78-decode.opc" + int nnn AU = (op[1] >> 4) & 0x07; +#line 412 "rl78-decode.opc" + int mm AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1nnn 01mm callt [%x0] */", + op[0], op[1]); + printf (" nnn = 0x%x,", nnn); + printf (" mm = 0x%x\n", mm); + } + SYNTAX("callt [%x0]"); +#line 412 "rl78-decode.opc" + ID(call); DM(None, 0x80 + mm*16 + nnn*2); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x88: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0x8f: + { + /** 0110 0001 1000 1reg xch %0, %1 */ +#line 1195 "rl78-decode.opc" + int reg AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1000 1reg xch %0, %1 */", + op[0], op[1]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("xch %0, %1"); +#line 1195 "rl78-decode.opc" + /* Note: DECW uses reg == X, so this must follow DECW */ + ID(xch); DR(A); SRB(reg); + + } + break; + case 0x89: + { + /** 0110 0001 1000 1001 decw %e0%0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1000 1001 decw %e0%0 */", + op[0], op[1]); + } + SYNTAX("decw %e0%0"); +#line 544 "rl78-decode.opc" + ID(sub); W(); DM(HL, IMMU(1)); SC(1); + + } + break; + case 0x90: + { + /** 0110 0001 1001 0000 addc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1001 0000 addc %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("addc %0, %e1%1"); +#line 218 "rl78-decode.opc" + ID(addc); DR(A); SM2(HL, B, 0); Fzac; + + } + break; + case 0x92: + { + /** 0110 0001 1001 0010 addc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1001 0010 addc %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("addc %0, %e1%1"); +#line 221 "rl78-decode.opc" + ID(addc); DR(A); SM2(HL, C, 0); Fzac; + + } + break; + case 0xa0: + case 0xa1: + { + /** 0110 0001 1010 000 sub %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 000 sub %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("sub %0, %e1%1"); +#line 1096 "rl78-decode.opc" + ID(sub); DR(A); SM2(HL, B, 0); Fzac; + + } + break; + case 0xa2: + { + /** 0110 0001 1010 0010 sub %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 0010 sub %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("sub %0, %e1%1"); +#line 1102 "rl78-decode.opc" + ID(sub); DR(A); SM2(HL, C, 0); Fzac; + + } + break; + case 0xa8: + { + /** 0110 0001 1010 1000 xch %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1000 xch %0, %1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %1"); +#line 1199 "rl78-decode.opc" + ID(xch); DR(A); SM(None, SADDR); + + } + break; + case 0xa9: + { + /** 0110 0001 1010 1001 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1001 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1192 "rl78-decode.opc" + ID(xch); DR(A); SM2(HL, C, 0); + + } + break; + case 0xaa: + { + /** 0110 0001 1010 1010 xch %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1010 xch %0, %e1%!1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%!1"); +#line 1174 "rl78-decode.opc" + ID(xch); DR(A); SM(None, IMMU(2)); + + } + break; + case 0xab: + { + /** 0110 0001 1010 1011 xch %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1011 xch %0, %1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %1"); +#line 1202 "rl78-decode.opc" + ID(xch); DR(A); SM(None, SFR); + + } + break; + case 0xac: + { + /** 0110 0001 1010 1100 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1100 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1183 "rl78-decode.opc" + ID(xch); DR(A); SM(HL, 0); + + } + break; + case 0xad: + { + /** 0110 0001 1010 1101 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1101 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1189 "rl78-decode.opc" + ID(xch); DR(A); SM(HL, IMMU(1)); + + } + break; + case 0xae: + { + /** 0110 0001 1010 1110 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1110 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1177 "rl78-decode.opc" + ID(xch); DR(A); SM(DE, 0); + + } + break; + case 0xaf: + { + /** 0110 0001 1010 1111 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1010 1111 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1180 "rl78-decode.opc" + ID(xch); DR(A); SM(DE, IMMU(1)); + + } + break; + case 0xb0: + { + /** 0110 0001 1011 0000 subc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1011 0000 subc %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("subc %0, %e1%1"); +#line 1128 "rl78-decode.opc" + ID(subc); DR(A); SM2(HL, B, 0); Fzac; + + } + break; + case 0xb2: + { + /** 0110 0001 1011 0010 subc %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1011 0010 subc %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("subc %0, %e1%1"); +#line 1131 "rl78-decode.opc" + ID(subc); DR(A); SM2(HL, C, 0); Fzac; + + } + break; + case 0xb8: + { + /** 0110 0001 1011 1000 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1011 1000 mov %0, %1 */", + op[0], op[1]); + } + SYNTAX("mov %0, %1"); +#line 702 "rl78-decode.opc" + ID(mov); DR(ES); SM(None, SADDR); + + } + break; + case 0xb9: + { + /** 0110 0001 1011 1001 xch %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1011 1001 xch %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xch %0, %e1%1"); +#line 1186 "rl78-decode.opc" + ID(xch); DR(A); SM2(HL, B, 0); + + } + break; + case 0xc0: + { + /** 0110 0001 1100 0000 cmp %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 0000 cmp %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("cmp %0, %e1%1"); +#line 471 "rl78-decode.opc" + ID(cmp); DR(A); SM2(HL, B, 0); Fzac; + + } + break; + case 0xc2: + { + /** 0110 0001 1100 0010 cmp %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 0010 cmp %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("cmp %0, %e1%1"); +#line 474 "rl78-decode.opc" + ID(cmp); DR(A); SM2(HL, C, 0); Fzac; + + } + break; + case 0xc3: + { + /** 0110 0001 1100 0011 bh $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 0011 bh $%a0 */", + op[0], op[1]); + } + SYNTAX("bh $%a0"); +#line 319 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H); + + } + break; + case 0xc8: + { + /** 0110 0001 1100 1000 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1000 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1065 "rl78-decode.opc" + ID(skip); COND(C); + + } + break; + case 0xc9: + { + /** 0110 0001 1100 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1001 mov %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("mov %0, %e1%1"); +#line 639 "rl78-decode.opc" + ID(mov); DR(A); SM2(HL, B, 0); + + } + break; + case 0xca: + case 0xda: + case 0xea: + case 0xfa: + { + /** 0110 0001 11rg 1010 call %0 */ +#line 409 "rl78-decode.opc" + int rg AU = (op[1] >> 4) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 11rg 1010 call %0 */", + op[0], op[1]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("call %0"); +#line 409 "rl78-decode.opc" + ID(call); DRW(rg); + + } + break; + case 0xcb: + { + /** 0110 0001 1100 1011 br ax */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1011 br ax */", + op[0], op[1]); + } + SYNTAX("br ax"); +#line 359 "rl78-decode.opc" + ID(branch); DR(AX); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xcc: + { + /** 0110 0001 1100 1100 brk */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1100 brk */", + op[0], op[1]); + } + SYNTAX("brk"); +#line 367 "rl78-decode.opc" + ID(break); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xcd: + { + /** 0110 0001 1100 1101 pop %s0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1101 pop %s0 */", + op[0], op[1]); + } + SYNTAX("pop %s0"); +#line 960 "rl78-decode.opc" + ID(mov); W(); DR(PSW); SPOP(); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xce: + { + /** 0110 0001 1100 1110 movs %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1100 1110 movs %e0%0, %1 */", + op[0], op[1]); + } + SYNTAX("movs %e0%0, %1"); +#line 787 "rl78-decode.opc" + ID(mov); DM(HL, IMMU(1)); SR(X); Fzc; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xcf: + case 0xdf: + case 0xef: + case 0xff: + { + /** 0110 0001 11rb 1111 sel rb%1 */ +#line 1012 "rl78-decode.opc" + int rb AU = (op[1] >> 4) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 11rb 1111 sel rb%1 */", + op[0], op[1]); + printf (" rb = 0x%x\n", rb); + } + SYNTAX("sel rb%1"); +#line 1012 "rl78-decode.opc" + ID(sel); SC(rb); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xd0: + { + /** 0110 0001 1101 0000 and %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 0000 and %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("and %0, %e1%1"); +#line 270 "rl78-decode.opc" + ID(and); DR(A); SM2(HL, B, 0); Fz; + + } + break; + case 0xd2: + { + /** 0110 0001 1101 0010 and %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 0010 and %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("and %0, %e1%1"); +#line 276 "rl78-decode.opc" + ID(and); DR(A); SM2(HL, C, 0); Fz; + + } + break; + case 0xd3: + { + /** 0110 0001 1101 0011 bnh $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 0011 bnh $%a0 */", + op[0], op[1]); + } + SYNTAX("bnh $%a0"); +#line 322 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH); + + } + break; + case 0xd8: + { + /** 0110 0001 1101 1000 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1000 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1071 "rl78-decode.opc" + ID(skip); COND(NC); + + } + break; + case 0xd9: + { + /** 0110 0001 1101 1001 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1001 mov %e0%0, %1 */", + op[0], op[1]); + } + SYNTAX("mov %e0%0, %1"); +#line 606 "rl78-decode.opc" + ID(mov); DM2(HL, B, 0); SR(A); + + } + break; + case 0xdb: + { + /** 0110 0001 1101 1011 ror %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1011 ror %0, %1 */", + op[0], op[1]); + } + SYNTAX("ror %0, %1"); +#line 993 "rl78-decode.opc" + ID(ror); DR(A); SC(1); + + } + break; + case 0xdc: + { + /** 0110 0001 1101 1100 rolc %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1100 rolc %0, %1 */", + op[0], op[1]); + } + SYNTAX("rolc %0, %1"); +#line 987 "rl78-decode.opc" + ID(rolc); DR(A); SC(1); + + } + break; + case 0xdd: + { + /** 0110 0001 1101 1101 push %s1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1101 push %s1 */", + op[0], op[1]); + } + SYNTAX("push %s1"); +#line 968 "rl78-decode.opc" + ID(mov); W(); DPUSH(); SR(PSW); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xde: + { + /** 0110 0001 1101 1110 cmps %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1101 1110 cmps %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("cmps %0, %e1%1"); +#line 505 "rl78-decode.opc" + ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xe0: + { + /** 0110 0001 1110 0000 or %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 0000 or %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("or %0, %e1%1"); +#line 917 "rl78-decode.opc" + ID(or); DR(A); SM2(HL, B, 0); Fz; + + } + break; + case 0xe2: + { + /** 0110 0001 1110 0010 or %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 0010 or %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("or %0, %e1%1"); +#line 923 "rl78-decode.opc" + ID(or); DR(A); SM2(HL, C, 0); Fz; + + } + break; + case 0xe3: + { + /** 0110 0001 1110 0011 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 0011 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1068 "rl78-decode.opc" + ID(skip); COND(H); + + } + break; + case 0xe8: + { + /** 0110 0001 1110 1000 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 1000 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1080 "rl78-decode.opc" + ID(skip); COND(Z); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xe9: + { + /** 0110 0001 1110 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 1001 mov %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("mov %0, %e1%1"); +#line 642 "rl78-decode.opc" + ID(mov); DR(A); SM2(HL, C, 0); + + } + break; + case 0xeb: + { + /** 0110 0001 1110 1011 rol %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 1011 rol %0, %1 */", + op[0], op[1]); + } + SYNTAX("rol %0, %1"); +#line 984 "rl78-decode.opc" + ID(rol); DR(A); SC(1); + + } + break; + case 0xec: + { + /** 0110 0001 1110 1100 retb */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 1100 retb */", + op[0], op[1]); + } + SYNTAX("retb"); +#line 979 "rl78-decode.opc" + ID(reti); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xed: + { + /** 0110 0001 1110 1101 halt */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1110 1101 halt */", + op[0], op[1]); + } + SYNTAX("halt"); +#line 555 "rl78-decode.opc" + ID(halt); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xee: + case 0xfe: + { + /** 0110 0001 111r 1110 rolwc %0, %1 */ +#line 990 "rl78-decode.opc" + int r AU = (op[1] >> 4) & 0x01; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 111r 1110 rolwc %0, %1 */", + op[0], op[1]); + printf (" r = 0x%x\n", r); + } + SYNTAX("rolwc %0, %1"); +#line 990 "rl78-decode.opc" + ID(rolc); W(); DRW(r); SC(1); + + } + break; + case 0xf0: + { + /** 0110 0001 1111 0000 xor %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 0000 xor %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xor %0, %e1%1"); +#line 1221 "rl78-decode.opc" + ID(xor); DR(A); SM2(HL, B, 0); Fz; + + } + break; + case 0xf2: + { + /** 0110 0001 1111 0010 xor %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 0010 xor %0, %e1%1 */", + op[0], op[1]); + } + SYNTAX("xor %0, %e1%1"); +#line 1227 "rl78-decode.opc" + ID(xor); DR(A); SM2(HL, C, 0); Fz; + + } + break; + case 0xf3: + { + /** 0110 0001 1111 0011 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 0011 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1074 "rl78-decode.opc" + ID(skip); COND(NH); + + } + break; + case 0xf8: + { + /** 0110 0001 1111 1000 sk%c1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 1000 sk%c1 */", + op[0], op[1]); + } + SYNTAX("sk%c1"); +#line 1077 "rl78-decode.opc" + ID(skip); COND(NZ); + + } + break; + case 0xf9: + { + /** 0110 0001 1111 1001 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 1001 mov %e0%0, %1 */", + op[0], op[1]); + } + SYNTAX("mov %e0%0, %1"); +#line 615 "rl78-decode.opc" + ID(mov); DM2(HL, C, 0); SR(A); + + } + break; + case 0xfb: + { + /** 0110 0001 1111 1011 rorc %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 1011 rorc %0, %1 */", + op[0], op[1]); + } + SYNTAX("rorc %0, %1"); +#line 996 "rl78-decode.opc" + ID(rorc); DR(A); SC(1); + + /*----------------------------------------------------------------------*/ + + /* Note that the branch insns need to be listed before the shift + ones, as "shift count of zero" means "branch insn" */ + + } + break; + case 0xfc: + { + /** 0110 0001 1111 1100 reti */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 1100 reti */", + op[0], op[1]); + } + SYNTAX("reti"); +#line 976 "rl78-decode.opc" + ID(reti); + + } + break; + case 0xfd: + { + /** 0110 0001 1111 1101 stop */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 1111 1101 stop */", + op[0], op[1]); + } + SYNTAX("stop"); +#line 1085 "rl78-decode.opc" + ID(stop); + + /*----------------------------------------------------------------------*/ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x68: + { + /** 0110 1000 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1000 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 850 "rl78-decode.opc" + ID(mov); W(); DM(C, IMMU(2)); SR(AX); + + } + break; + case 0x69: + { + /** 0110 1001 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1001 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 841 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(C, IMMU(2)); + + } + break; + case 0x6a: + { + /** 0110 1010 or %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1010 or %0, #%1 */", + op[0]); + } + SYNTAX("or %0, #%1"); +#line 938 "rl78-decode.opc" + ID(or); DM(None, SADDR); SC(IMMU(1)); Fz; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x6b: + { + /** 0110 1011 or %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1011 or %0, %1 */", + op[0]); + } + SYNTAX("or %0, %1"); +#line 935 "rl78-decode.opc" + ID(or); DR(A); SM(None, SADDR); Fz; + + } + break; + case 0x6c: + { + /** 0110 1100 or %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1100 or %0, #%1 */", + op[0]); + } + SYNTAX("or %0, #%1"); +#line 926 "rl78-decode.opc" + ID(or); DR(A); SC(IMMU(1)); Fz; + + } + break; + case 0x6d: + { + /** 0110 1101 or %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1101 or %0, %e1%1 */", + op[0]); + } + SYNTAX("or %0, %e1%1"); +#line 914 "rl78-decode.opc" + ID(or); DR(A); SM(HL, 0); Fz; + + } + break; + case 0x6e: + { + /** 0110 1110 or %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1110 or %0, %e1%1 */", + op[0]); + } + SYNTAX("or %0, %e1%1"); +#line 920 "rl78-decode.opc" + ID(or); DR(A); SM(HL, IMMU(1)); Fz; + + } + break; + case 0x6f: + { + /** 0110 1111 or %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 1111 or %0, %e1%!1 */", + op[0]); + } + SYNTAX("or %0, %e1%!1"); +#line 911 "rl78-decode.opc" + ID(or); DR(A); SM(None, IMMU(2)); Fz; + + } + break; + case 0x70: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x76: + case 0x77: + { + /** 0111 0rba mov %0, %1 */ +#line 675 "rl78-decode.opc" + int rba AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 0rba mov %0, %1 */", + op[0]); + printf (" rba = 0x%x\n", rba); + } + SYNTAX("mov %0, %1"); +#line 675 "rl78-decode.opc" + ID(mov); DRB(rba); SR(A); + + } + break; + case 0x71: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + { + /** 0111 0001 0bit 0000 set1 %e0%!0 */ +#line 1017 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0000 set1 %e0%!0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("set1 %e0%!0"); +#line 1017 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); DB(bit); SC(1); + + } + break; + case 0x01: + case 0x11: + case 0x21: + case 0x31: + case 0x41: + case 0x51: + case 0x61: + case 0x71: + { + /** 0111 0001 0bit 0001 mov1 %0, cy */ +#line 779 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0001 mov1 %0, cy */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 %0, cy"); +#line 779 "rl78-decode.opc" + ID(mov); DM(None, SADDR); DB(bit); SCY(); + + } + break; + case 0x02: + case 0x12: + case 0x22: + case 0x32: + case 0x42: + case 0x52: + case 0x62: + case 0x72: + { + /** 0111 0001 0bit 0010 set1 %0 */ +#line 1035 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0010 set1 %0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("set1 %0"); +#line 1035 "rl78-decode.opc" + ID(mov); DM(None, SADDR); DB(bit); SC(1); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x03: + case 0x13: + case 0x23: + case 0x33: + case 0x43: + case 0x53: + case 0x63: + case 0x73: + { + /** 0111 0001 0bit 0011 clr1 %0 */ +#line 435 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0011 clr1 %0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("clr1 %0"); +#line 435 "rl78-decode.opc" + ID(mov); DM(None, SADDR); DB(bit); SC(0); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x04: + case 0x14: + case 0x24: + case 0x34: + case 0x44: + case 0x54: + case 0x64: + case 0x74: + { + /** 0111 0001 0bit 0100 mov1 cy, %1 */ +#line 773 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0100 mov1 cy, %1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 cy, %1"); +#line 773 "rl78-decode.opc" + ID(mov); DCY(); SM(None, SADDR); SB(bit); + + } + break; + case 0x05: + case 0x15: + case 0x25: + case 0x35: + case 0x45: + case 0x55: + case 0x65: + case 0x75: + { + /** 0111 0001 0bit 0101 and1 cy, %s1 */ +#line 305 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0101 and1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("and1 cy, %s1"); +#line 305 "rl78-decode.opc" + ID(and); DCY(); SM(None, SADDR); SB(bit); + + /*----------------------------------------------------------------------*/ + + /* Note that the branch insns need to be listed before the shift + ones, as "shift count of zero" means "branch insn" */ + + } + break; + case 0x06: + case 0x16: + case 0x26: + case 0x36: + case 0x46: + case 0x56: + case 0x66: + case 0x76: + { + /** 0111 0001 0bit 0110 or1 cy, %s1 */ +#line 952 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0110 or1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("or1 cy, %s1"); +#line 952 "rl78-decode.opc" + ID(or); DCY(); SM(None, SADDR); SB(bit); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x07: + case 0x17: + case 0x27: + case 0x37: + case 0x47: + case 0x57: + case 0x67: + case 0x77: + { + /** 0111 0001 0bit 0111 xor1 cy, %s1 */ +#line 1256 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 0111 xor1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("xor1 cy, %s1"); +#line 1256 "rl78-decode.opc" + ID(xor); DCY(); SM(None, SADDR); SB(bit); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x08: + case 0x18: + case 0x28: + case 0x38: + case 0x48: + case 0x58: + case 0x68: + case 0x78: + { + /** 0111 0001 0bit 1000 clr1 %e0%!0 */ +#line 417 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1000 clr1 %e0%!0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("clr1 %e0%!0"); +#line 417 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); DB(bit); SC(0); + + } + break; + case 0x09: + case 0x19: + case 0x29: + case 0x39: + case 0x49: + case 0x59: + case 0x69: + case 0x79: + { + /** 0111 0001 0bit 1001 mov1 %s0, cy */ +#line 782 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1001 mov1 %s0, cy */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 %s0, cy"); +#line 782 "rl78-decode.opc" + ID(mov); DM(None, SFR); DB(bit); SCY(); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x0a: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x4a: + case 0x5a: + case 0x6a: + case 0x7a: + { + /** 0111 0001 0bit 1010 set1 %s0 */ +#line 1029 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1010 set1 %s0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("set1 %s0"); +#line 1029 "rl78-decode.opc" + op0 = SFR; + ID(mov); DM(None, op0); DB(bit); SC(1); + if (op0 == RL78_SFR_PSW && bit == 7) + rl78->syntax = "ei"; + + } + break; + case 0x0b: + case 0x1b: + case 0x2b: + case 0x3b: + case 0x4b: + case 0x5b: + case 0x6b: + case 0x7b: + { + /** 0111 0001 0bit 1011 clr1 %s0 */ +#line 429 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1011 clr1 %s0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("clr1 %s0"); +#line 429 "rl78-decode.opc" + op0 = SFR; + ID(mov); DM(None, op0); DB(bit); SC(0); + if (op0 == RL78_SFR_PSW && bit == 7) + rl78->syntax = "di"; + + } + break; + case 0x0c: + case 0x1c: + case 0x2c: + case 0x3c: + case 0x4c: + case 0x5c: + case 0x6c: + case 0x7c: + { + /** 0111 0001 0bit 1100 mov1 cy, %s1 */ +#line 776 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1100 mov1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 cy, %s1"); +#line 776 "rl78-decode.opc" + ID(mov); DCY(); SM(None, SFR); SB(bit); + + } + break; + case 0x0d: + case 0x1d: + case 0x2d: + case 0x3d: + case 0x4d: + case 0x5d: + case 0x6d: + case 0x7d: + { + /** 0111 0001 0bit 1101 and1 cy, %s1 */ +#line 302 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1101 and1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("and1 cy, %s1"); +#line 302 "rl78-decode.opc" + ID(and); DCY(); SM(None, SFR); SB(bit); + + } + break; + case 0x0e: + case 0x1e: + case 0x2e: + case 0x3e: + case 0x4e: + case 0x5e: + case 0x6e: + case 0x7e: + { + /** 0111 0001 0bit 1110 or1 cy, %s1 */ +#line 949 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1110 or1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("or1 cy, %s1"); +#line 949 "rl78-decode.opc" + ID(or); DCY(); SM(None, SFR); SB(bit); + + } + break; + case 0x0f: + case 0x1f: + case 0x2f: + case 0x3f: + case 0x4f: + case 0x5f: + case 0x6f: + case 0x7f: + { + /** 0111 0001 0bit 1111 xor1 cy, %s1 */ +#line 1253 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 0bit 1111 xor1 cy, %s1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("xor1 cy, %s1"); +#line 1253 "rl78-decode.opc" + ID(xor); DCY(); SM(None, SFR); SB(bit); + + } + break; + case 0x80: + { + /** 0111 0001 1000 0000 set1 cy */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1000 0000 set1 cy */", + op[0], op[1]); + } + SYNTAX("set1 cy"); +#line 1026 "rl78-decode.opc" + ID(mov); DCY(); SC(1); + + } + break; + case 0x81: + case 0x91: + case 0xa1: + case 0xb1: + case 0xc1: + case 0xd1: + case 0xe1: + case 0xf1: + { + /** 0111 0001 1bit 0001 mov1 %e0%0, cy */ +#line 761 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0001 mov1 %e0%0, cy */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 %e0%0, cy"); +#line 761 "rl78-decode.opc" + ID(mov); DM(HL, 0); DB(bit); SCY(); + + } + break; + case 0x82: + case 0x92: + case 0xa2: + case 0xb2: + case 0xc2: + case 0xd2: + case 0xe2: + case 0xf2: + { + /** 0111 0001 1bit 0010 set1 %e0%0 */ +#line 1020 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0010 set1 %e0%0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("set1 %e0%0"); +#line 1020 "rl78-decode.opc" + ID(mov); DM(HL, 0); DB(bit); SC(1); + + } + break; + case 0x83: + case 0x93: + case 0xa3: + case 0xb3: + case 0xc3: + case 0xd3: + case 0xe3: + case 0xf3: + { + /** 0111 0001 1bit 0011 clr1 %e0%0 */ +#line 420 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0011 clr1 %e0%0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("clr1 %e0%0"); +#line 420 "rl78-decode.opc" + ID(mov); DM(HL, 0); DB(bit); SC(0); + + } + break; + case 0x84: + case 0x94: + case 0xa4: + case 0xb4: + case 0xc4: + case 0xd4: + case 0xe4: + case 0xf4: + { + /** 0111 0001 1bit 0100 mov1 cy, %e1%1 */ +#line 767 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 cy, %e1%1"); +#line 767 "rl78-decode.opc" + ID(mov); DCY(); SM(HL, 0); SB(bit); + + } + break; + case 0x85: + case 0x95: + case 0xa5: + case 0xb5: + case 0xc5: + case 0xd5: + case 0xe5: + case 0xf5: + { + /** 0111 0001 1bit 0101 and1 cy, %e1%1 */ +#line 296 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0101 and1 cy, %e1%1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("and1 cy, %e1%1"); +#line 296 "rl78-decode.opc" + ID(and); DCY(); SM(HL, 0); SB(bit); + + } + break; + case 0x86: + case 0x96: + case 0xa6: + case 0xb6: + case 0xc6: + case 0xd6: + case 0xe6: + case 0xf6: + { + /** 0111 0001 1bit 0110 or1 cy, %e1%1 */ +#line 943 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0110 or1 cy, %e1%1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("or1 cy, %e1%1"); +#line 943 "rl78-decode.opc" + ID(or); DCY(); SM(HL, 0); SB(bit); + + } + break; + case 0x87: + case 0x97: + case 0xa7: + case 0xb7: + case 0xc7: + case 0xd7: + case 0xe7: + case 0xf7: + { + /** 0111 0001 1bit 0111 xor1 cy, %e1%1 */ +#line 1247 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("xor1 cy, %e1%1"); +#line 1247 "rl78-decode.opc" + ID(xor); DCY(); SM(HL, 0); SB(bit); + + } + break; + case 0x88: + { + /** 0111 0001 1000 1000 clr1 cy */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1000 1000 clr1 cy */", + op[0], op[1]); + } + SYNTAX("clr1 cy"); +#line 426 "rl78-decode.opc" + ID(mov); DCY(); SC(0); + + } + break; + case 0x89: + case 0x99: + case 0xa9: + case 0xb9: + case 0xc9: + case 0xd9: + case 0xe9: + case 0xf9: + { + /** 0111 0001 1bit 1001 mov1 %e0%0, cy */ +#line 764 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1001 mov1 %e0%0, cy */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 %e0%0, cy"); +#line 764 "rl78-decode.opc" + ID(mov); DR(A); DB(bit); SCY(); + + } + break; + case 0x8a: + case 0x9a: + case 0xaa: + case 0xba: + case 0xca: + case 0xda: + case 0xea: + case 0xfa: + { + /** 0111 0001 1bit 1010 set1 %0 */ +#line 1023 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1010 set1 %0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("set1 %0"); +#line 1023 "rl78-decode.opc" + ID(mov); DR(A); DB(bit); SC(1); + + } + break; + case 0x8b: + case 0x9b: + case 0xab: + case 0xbb: + case 0xcb: + case 0xdb: + case 0xeb: + case 0xfb: + { + /** 0111 0001 1bit 1011 clr1 %0 */ +#line 423 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1011 clr1 %0 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("clr1 %0"); +#line 423 "rl78-decode.opc" + ID(mov); DR(A); DB(bit); SC(0); + + } + break; + case 0x8c: + case 0x9c: + case 0xac: + case 0xbc: + case 0xcc: + case 0xdc: + case 0xec: + case 0xfc: + { + /** 0111 0001 1bit 1100 mov1 cy, %e1%1 */ +#line 770 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("mov1 cy, %e1%1"); +#line 770 "rl78-decode.opc" + ID(mov); DCY(); SR(A); SB(bit); + + } + break; + case 0x8d: + case 0x9d: + case 0xad: + case 0xbd: + case 0xcd: + case 0xdd: + case 0xed: + case 0xfd: + { + /** 0111 0001 1bit 1101 and1 cy, %1 */ +#line 299 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1101 and1 cy, %1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("and1 cy, %1"); +#line 299 "rl78-decode.opc" + ID(and); DCY(); SR(A); SB(bit); + + } + break; + case 0x8e: + case 0x9e: + case 0xae: + case 0xbe: + case 0xce: + case 0xde: + case 0xee: + case 0xfe: + { + /** 0111 0001 1bit 1110 or1 cy, %1 */ +#line 946 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1110 or1 cy, %1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("or1 cy, %1"); +#line 946 "rl78-decode.opc" + ID(or); DCY(); SR(A); SB(bit); + + } + break; + case 0x8f: + case 0x9f: + case 0xaf: + case 0xbf: + case 0xcf: + case 0xdf: + case 0xef: + case 0xff: + { + /** 0111 0001 1bit 1111 xor1 cy, %1 */ +#line 1250 "rl78-decode.opc" + int bit AU = (op[1] >> 4) & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0001 1bit 1111 xor1 cy, %1 */", + op[0], op[1]); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("xor1 cy, %1"); +#line 1250 "rl78-decode.opc" + ID(xor); DCY(); SR(A); SB(bit); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x78: + { + /** 0111 1000 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1000 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 853 "rl78-decode.opc" + ID(mov); W(); DM(BC, IMMU(2)); SR(AX); + + } + break; + case 0x79: + { + /** 0111 1001 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1001 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 844 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(BC, IMMU(2)); + + } + break; + case 0x7a: + { + /** 0111 1010 xor %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1010 xor %0, #%1 */", + op[0]); + } + SYNTAX("xor %0, #%1"); +#line 1242 "rl78-decode.opc" + ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x7b: + { + /** 0111 1011 xor %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1011 xor %0, %1 */", + op[0]); + } + SYNTAX("xor %0, %1"); +#line 1239 "rl78-decode.opc" + ID(xor); DR(A); SM(None, SADDR); Fz; + + } + break; + case 0x7c: + { + /** 0111 1100 xor %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1100 xor %0, #%1 */", + op[0]); + } + SYNTAX("xor %0, #%1"); +#line 1230 "rl78-decode.opc" + ID(xor); DR(A); SC(IMMU(1)); Fz; + + } + break; + case 0x7d: + { + /** 0111 1101 xor %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1101 xor %0, %e1%1 */", + op[0]); + } + SYNTAX("xor %0, %e1%1"); +#line 1218 "rl78-decode.opc" + ID(xor); DR(A); SM(HL, 0); Fz; + + } + break; + case 0x7e: + { + /** 0111 1110 xor %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1110 xor %0, %e1%1 */", + op[0]); + } + SYNTAX("xor %0, %e1%1"); +#line 1224 "rl78-decode.opc" + ID(xor); DR(A); SM(HL, IMMU(1)); Fz; + + } + break; + case 0x7f: + { + /** 0111 1111 xor %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0111 1111 xor %0, %e1%!1 */", + op[0]); + } + SYNTAX("xor %0, %e1%!1"); +#line 1215 "rl78-decode.opc" + ID(xor); DR(A); SM(None, IMMU(2)); Fz; + + } + break; + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + { + /** 1000 0reg inc %0 */ +#line 566 "rl78-decode.opc" + int reg AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 0reg inc %0 */", + op[0]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("inc %0"); +#line 566 "rl78-decode.opc" + ID(add); DRB(reg); SC(1); Fza; + + } + break; + case 0x88: + { + /** 1000 1000 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1000 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 645 "rl78-decode.opc" + ID(mov); DR(A); SM(SP, IMMU(1)); + + } + break; + case 0x89: + { + /** 1000 1001 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1001 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 627 "rl78-decode.opc" + ID(mov); DR(A); SM(DE, 0); + + } + break; + case 0x8a: + { + /** 1000 1010 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1010 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 630 "rl78-decode.opc" + ID(mov); DR(A); SM(DE, IMMU(1)); + + } + break; + case 0x8b: + { + /** 1000 1011 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1011 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 633 "rl78-decode.opc" + ID(mov); DR(A); SM(HL, 0); + + } + break; + case 0x8c: + { + /** 1000 1100 mov %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1100 mov %0, %e1%1 */", + op[0]); + } + SYNTAX("mov %0, %e1%1"); +#line 636 "rl78-decode.opc" + ID(mov); DR(A); SM(HL, IMMU(1)); + + } + break; + case 0x8d: + { + /** 1000 1101 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1101 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 669 "rl78-decode.opc" + ID(mov); DR(A); SM(None, SADDR); + + } + break; + case 0x8e: + { + /** 1000 1110 mov %0, %s1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1110 mov %0, %s1 */", + op[0]); + } + SYNTAX("mov %0, %s1"); +#line 666 "rl78-decode.opc" + ID(mov); DR(A); SM(None, SFR); + + } + break; + case 0x8f: + { + /** 1000 1111 mov %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1000 1111 mov %0, %e1%!1 */", + op[0]); + } + SYNTAX("mov %0, %e1%!1"); +#line 624 "rl78-decode.opc" + ID(mov); DR(A); SM(None, IMMU(2)); + + } + break; + case 0x90: + case 0x91: + case 0x92: + case 0x93: + case 0x94: + case 0x95: + case 0x96: + case 0x97: + { + /** 1001 0reg dec %0 */ +#line 533 "rl78-decode.opc" + int reg AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 0reg dec %0 */", + op[0]); + printf (" reg = 0x%x\n", reg); + } + SYNTAX("dec %0"); +#line 533 "rl78-decode.opc" + ID(sub); DRB(reg); SC(1); Fza; + + } + break; + case 0x98: + { + /** 1001 1000 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1000 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 621 "rl78-decode.opc" + ID(mov); DM(SP, IMMU(1)); SR(A); + + } + break; + case 0x99: + { + /** 1001 1001 mov %e0%0,%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1001 mov %e0%0,%1 */", + op[0]); + } + SYNTAX("mov %e0%0,%1"); +#line 594 "rl78-decode.opc" + ID(mov); DM(DE, 0); SR(A); + + } + break; + case 0x9a: + { + /** 1001 1010 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1010 mov %e0%0, %1 */", + op[0]); + } + SYNTAX("mov %e0%0, %1"); +#line 600 "rl78-decode.opc" + ID(mov); DM(DE, IMMU(1)); SR(A); + + } + break; + case 0x9b: + { + /** 1001 1011 mov %e0%0,%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1011 mov %e0%0,%1 */", + op[0]); + } + SYNTAX("mov %e0%0,%1"); +#line 603 "rl78-decode.opc" + ID(mov); DM(HL, 0); SR(A); + + } + break; + case 0x9c: + { + /** 1001 1100 mov %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1100 mov %e0%0, %1 */", + op[0]); + } + SYNTAX("mov %e0%0, %1"); +#line 612 "rl78-decode.opc" + ID(mov); DM(HL, IMMU(1)); SR(A); + + } + break; + case 0x9d: + { + /** 1001 1101 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1101 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 726 "rl78-decode.opc" + ID(mov); DM(None, SADDR); SR(A); + + } + break; + case 0x9e: + { + /** 1001 1110 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1110 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 756 "rl78-decode.opc" + ID(mov); DM(None, SFR); SR(A); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0x9f: + { + /** 1001 1111 mov %e0%!0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1001 1111 mov %e0%!0, %1 */", + op[0]); + } + SYNTAX("mov %e0%!0, %1"); +#line 591 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); SR(A); + + } + break; + case 0xa0: + { + /** 1010 0000 inc %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 0000 inc %e0%!0 */", + op[0]); + } + SYNTAX("inc %e0%!0"); +#line 560 "rl78-decode.opc" + ID(add); DM(None, IMMU(2)); SC(1); Fza; + + } + break; + case 0xa1: + case 0xa3: + case 0xa5: + case 0xa7: + { + /** 1010 0rg1 incw %0 */ +#line 580 "rl78-decode.opc" + int rg AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 0rg1 incw %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("incw %0"); +#line 580 "rl78-decode.opc" + ID(add); W(); DRW(rg); SC(1); + + } + break; + case 0xa2: + { + /** 1010 0010 incw %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 0010 incw %e0%!0 */", + op[0]); + } + SYNTAX("incw %e0%!0"); +#line 574 "rl78-decode.opc" + ID(add); W(); DM(None, IMMU(2)); SC(1); + + } + break; + case 0xa4: + { + /** 1010 0100 inc %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 0100 inc %0 */", + op[0]); + } + SYNTAX("inc %0"); +#line 569 "rl78-decode.opc" + ID(add); DM(None, SADDR); SC(1); Fza; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xa6: + { + /** 1010 0110 incw %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 0110 incw %0 */", + op[0]); + } + SYNTAX("incw %0"); +#line 583 "rl78-decode.opc" + ID(add); W(); DM(None, SADDR); SC(1); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xa8: + { + /** 1010 1000 movw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1000 movw %0, %1 */", + op[0]); + } + SYNTAX("movw %0, %1"); +#line 826 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(SP, IMMU(1)); + + } + break; + case 0xa9: + { + /** 1010 1001 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1001 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 814 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(DE, 0); + + } + break; + case 0xaa: + { + /** 1010 1010 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1010 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 817 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(DE, IMMU(1)); + + } + break; + case 0xab: + { + /** 1010 1011 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1011 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 820 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(HL, 0); + + } + break; + case 0xac: + { + /** 1010 1100 movw %0, %e1%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1100 movw %0, %e1%1 */", + op[0]); + } + SYNTAX("movw %0, %e1%1"); +#line 823 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(HL, IMMU(1)); + + } + break; + case 0xad: + { + /** 1010 1101 movw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1101 movw %0, %1 */", + op[0]); + } + SYNTAX("movw %0, %1"); +#line 856 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(None, SADDR); + + } + break; + case 0xae: + { + /** 1010 1110 movw %0, %s1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1110 movw %0, %s1 */", + op[0]); + } + SYNTAX("movw %0, %s1"); +#line 859 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(None, SFR); + + } + break; + case 0xaf: + { + /** 1010 1111 movw %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1010 1111 movw %0, %e1%!1 */", + op[0]); + } + SYNTAX("movw %0, %e1%!1"); +#line 810 "rl78-decode.opc" + ID(mov); W(); DR(AX); SM(None, IMMU(2)); + + + } + break; + case 0xb0: + { + /** 1011 0000 dec %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 0000 dec %e0%!0 */", + op[0]); + } + SYNTAX("dec %e0%!0"); +#line 527 "rl78-decode.opc" + ID(sub); DM(None, IMMU(2)); SC(1); Fza; + + } + break; + case 0xb1: + case 0xb3: + case 0xb5: + case 0xb7: + { + /** 1011 0rg1 decw %0 */ +#line 547 "rl78-decode.opc" + int rg AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 0rg1 decw %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("decw %0"); +#line 547 "rl78-decode.opc" + ID(sub); W(); DRW(rg); SC(1); + + } + break; + case 0xb2: + { + /** 1011 0010 decw %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 0010 decw %e0%!0 */", + op[0]); + } + SYNTAX("decw %e0%!0"); +#line 541 "rl78-decode.opc" + ID(sub); W(); DM(None, IMMU(2)); SC(1); + + } + break; + case 0xb4: + { + /** 1011 0100 dec %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 0100 dec %0 */", + op[0]); + } + SYNTAX("dec %0"); +#line 536 "rl78-decode.opc" + ID(sub); DM(None, SADDR); SC(1); Fza; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xb6: + { + /** 1011 0110 decw %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 0110 decw %0 */", + op[0]); + } + SYNTAX("decw %0"); +#line 550 "rl78-decode.opc" + ID(sub); W(); DM(None, SADDR); SC(1); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xb8: + { + /** 1011 1000 movw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1000 movw %0, %1 */", + op[0]); + } + SYNTAX("movw %0, %1"); +#line 807 "rl78-decode.opc" + ID(mov); W(); DM(SP, IMMU(1)); SR(AX); + + } + break; + case 0xb9: + { + /** 1011 1001 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1001 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 795 "rl78-decode.opc" + ID(mov); W(); DM(DE, 0); SR(AX); + + } + break; + case 0xba: + { + /** 1011 1010 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1010 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 798 "rl78-decode.opc" + ID(mov); W(); DM(DE, IMMU(1)); SR(AX); + + } + break; + case 0xbb: + { + /** 1011 1011 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1011 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 801 "rl78-decode.opc" + ID(mov); W(); DM(HL, 0); SR(AX); + + } + break; + case 0xbc: + { + /** 1011 1100 movw %e0%0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1100 movw %e0%0, %1 */", + op[0]); + } + SYNTAX("movw %e0%0, %1"); +#line 804 "rl78-decode.opc" + ID(mov); W(); DM(HL, IMMU(1)); SR(AX); + + } + break; + case 0xbd: + { + /** 1011 1101 movw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1101 movw %0, %1 */", + op[0]); + } + SYNTAX("movw %0, %1"); +#line 871 "rl78-decode.opc" + ID(mov); W(); DM(None, SADDR); SR(AX); + + } + break; + case 0xbe: + { + /** 1011 1110 movw %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1110 movw %0, %1 */", + op[0]); + } + SYNTAX("movw %0, %1"); +#line 877 "rl78-decode.opc" + ID(mov); W(); DM(None, SFR); SR(AX); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xbf: + { + /** 1011 1111 movw %e0%!0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1011 1111 movw %e0%!0, %1 */", + op[0]); + } + SYNTAX("movw %e0%!0, %1"); +#line 792 "rl78-decode.opc" + ID(mov); W(); DM(None, IMMU(2)); SR(AX); + + } + break; + case 0xc0: + case 0xc2: + case 0xc4: + case 0xc6: + { + /** 1100 0rg0 pop %0 */ +#line 957 "rl78-decode.opc" + int rg AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 0rg0 pop %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("pop %0"); +#line 957 "rl78-decode.opc" + ID(mov); W(); DRW(rg); SPOP(); + + } + break; + case 0xc1: + case 0xc3: + case 0xc5: + case 0xc7: + { + /** 1100 0rg1 push %1 */ +#line 965 "rl78-decode.opc" + int rg AU = (op[0] >> 1) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 0rg1 push %1 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("push %1"); +#line 965 "rl78-decode.opc" + ID(mov); W(); DPUSH(); SRW(rg); + + } + break; + case 0xc8: + { + /** 1100 1000 mov %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1000 mov %0, #%1 */", + op[0]); + } + SYNTAX("mov %0, #%1"); +#line 618 "rl78-decode.opc" + ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); + + } + break; + case 0xc9: + { + /** 1100 1001 movw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1001 movw %0, #%1 */", + op[0]); + } + SYNTAX("movw %0, #%1"); +#line 868 "rl78-decode.opc" + ID(mov); W(); DM(None, SADDR); SC(IMMU(2)); + + } + break; + case 0xca: + { + /** 1100 1010 mov %e0%0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1010 mov %e0%0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%0, #%1"); +#line 597 "rl78-decode.opc" + ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); + + } + break; + case 0xcb: + { + /** 1100 1011 movw %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1011 movw %0, #%1 */", + op[0]); + } + SYNTAX("movw %0, #%1"); +#line 874 "rl78-decode.opc" + ID(mov); W(); DM(None, SFR); SC(IMMU(2)); + + } + break; + case 0xcc: + { + /** 1100 1100 mov %e0%0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1100 mov %e0%0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%0, #%1"); +#line 609 "rl78-decode.opc" + ID(mov); DM(HL, IMMU(1)); SC(IMMU(1)); + + } + break; + case 0xcd: + { + /** 1100 1101 mov %0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1101 mov %0, #%1 */", + op[0]); + } + SYNTAX("mov %0, #%1"); +#line 723 "rl78-decode.opc" + ID(mov); DM(None, SADDR); SC(IMMU(1)); + + } + break; + case 0xce: + { + /** 1100 1110 mov %s0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1110 mov %s0, #%1 */", + op[0]); + } + SYNTAX("mov %s0, #%1"); +#line 729 "rl78-decode.opc" + op0 = SFR; + op1 = IMMU(1); + ID(mov); DM(None, op0); SC(op1); + if (op0 == 0xffffb) + switch (op1) + { + case 0x01: + rl78->syntax = "mulhu"; ID(mulhu); + break; + case 0x02: + rl78->syntax = "mulh"; ID(mulh); + break; + case 0x03: + rl78->syntax = "divhu"; ID(divhu); + break; + case 0x04: + rl78->syntax = "divwu"; ID(divwu); + break; + case 0x05: + rl78->syntax = "machu"; ID(machu); + break; + case 0x06: + rl78->syntax = "mach"; ID(mach); + break; + } + + } + break; + case 0xcf: + { + /** 1100 1111 mov %e0%!0, #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1100 1111 mov %e0%!0, #%1 */", + op[0]); + } + SYNTAX("mov %e0%!0, #%1"); +#line 588 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); SC(IMMU(1)); + + } + break; + case 0xd0: + case 0xd1: + case 0xd2: + case 0xd3: + { + /** 1101 00rg cmp0 %0 */ +#line 497 "rl78-decode.opc" + int rg AU = op[0] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 00rg cmp0 %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("cmp0 %0"); +#line 497 "rl78-decode.opc" + ID(cmp); DRB(rg); SC(0); Fzac; + + } + break; + case 0xd4: + { + /** 1101 0100 cmp0 %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 0100 cmp0 %0 */", + op[0]); + } + SYNTAX("cmp0 %0"); +#line 500 "rl78-decode.opc" + ID(cmp); DM(None, SADDR); SC(0); Fzac; + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xd5: + { + /** 1101 0101 cmp0 %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 0101 cmp0 %e0%!0 */", + op[0]); + } + SYNTAX("cmp0 %e0%!0"); +#line 494 "rl78-decode.opc" + ID(cmp); DM(None, IMMU(2)); SC(0); Fzac; + + } + break; + case 0xd6: + { + /** 1101 0110 mulu x */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 0110 mulu x */", + op[0]); + } + SYNTAX("mulu x"); +#line 882 "rl78-decode.opc" + ID(mulu); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xd7: + { + /** 1101 0111 ret */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 0111 ret */", + op[0]); + } + SYNTAX("ret"); +#line 973 "rl78-decode.opc" + ID(ret); + + } + break; + case 0xd8: + { + /** 1101 1000 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1000 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 690 "rl78-decode.opc" + ID(mov); DR(X); SM(None, SADDR); + + } + break; + case 0xd9: + { + /** 1101 1001 mov %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1001 mov %0, %e1%!1 */", + op[0]); + } + SYNTAX("mov %0, %e1%!1"); +#line 687 "rl78-decode.opc" + ID(mov); DR(X); SM(None, IMMU(2)); + + } + break; + case 0xda: + case 0xea: + case 0xfa: + { + /** 11ra 1010 movw %0, %1 */ +#line 865 "rl78-decode.opc" + int ra AU = (op[0] >> 4) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 11ra 1010 movw %0, %1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("movw %0, %1"); +#line 865 "rl78-decode.opc" + ID(mov); W(); DRW(ra); SM(None, SADDR); + + } + break; + case 0xdb: + case 0xeb: + case 0xfb: + { + /** 11ra 1011 movw %0, %e1%!1 */ +#line 862 "rl78-decode.opc" + int ra AU = (op[0] >> 4) & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 11ra 1011 movw %0, %e1%!1 */", + op[0]); + printf (" ra = 0x%x\n", ra); + } + SYNTAX("movw %0, %e1%!1"); +#line 862 "rl78-decode.opc" + ID(mov); W(); DRW(ra); SM(None, IMMU(2)); + + } + break; + case 0xdc: + { + /** 1101 1100 bc $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1100 bc $%a0 */", + op[0]); + } + SYNTAX("bc $%a0"); +#line 313 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C); + + } + break; + case 0xdd: + { + /** 1101 1101 bz $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1101 bz $%a0 */", + op[0]); + } + SYNTAX("bz $%a0"); +#line 325 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z); + + } + break; + case 0xde: + { + /** 1101 1110 bnc $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1110 bnc $%a0 */", + op[0]); + } + SYNTAX("bnc $%a0"); +#line 316 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC); + + } + break; + case 0xdf: + { + /** 1101 1111 bnz $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1101 1111 bnz $%a0 */", + op[0]); + } + SYNTAX("bnz $%a0"); +#line 328 "rl78-decode.opc" + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xe0: + case 0xe1: + case 0xe2: + case 0xe3: + { + /** 1110 00rg oneb %0 */ +#line 895 "rl78-decode.opc" + int rg AU = op[0] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 00rg oneb %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("oneb %0"); +#line 895 "rl78-decode.opc" + ID(mov); DRB(rg); SC(1); + + } + break; + case 0xe4: + { + /** 1110 0100 oneb %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 0100 oneb %0 */", + op[0]); + } + SYNTAX("oneb %0"); +#line 898 "rl78-decode.opc" + ID(mov); DM(None, SADDR); SC(1); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xe5: + { + /** 1110 0101 oneb %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 0101 oneb %e0%!0 */", + op[0]); + } + SYNTAX("oneb %e0%!0"); +#line 892 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); SC(1); + + } + break; + case 0xe6: + { + /** 1110 0110 onew %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 0110 onew %0 */", + op[0]); + } + SYNTAX("onew %0"); +#line 903 "rl78-decode.opc" + ID(mov); DR(AX); SC(1); + + } + break; + case 0xe7: + { + /** 1110 0111 onew %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 0111 onew %0 */", + op[0]); + } + SYNTAX("onew %0"); +#line 906 "rl78-decode.opc" + ID(mov); DR(BC); SC(1); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xe8: + { + /** 1110 1000 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1000 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 678 "rl78-decode.opc" + ID(mov); DR(B); SM(None, SADDR); + + } + break; + case 0xe9: + { + /** 1110 1001 mov %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1001 mov %0, %e1%!1 */", + op[0]); + } + SYNTAX("mov %0, %e1%!1"); +#line 672 "rl78-decode.opc" + ID(mov); DR(B); SM(None, IMMU(2)); + + } + break; + case 0xec: + { + /** 1110 1100 br !%!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1100 br !%!a0 */", + op[0]); + } + SYNTAX("br !%!a0"); +#line 347 "rl78-decode.opc" + ID(branch); DC(IMMU(3)); + + } + break; + case 0xed: + { + /** 1110 1101 br %!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1101 br %!a0 */", + op[0]); + } + SYNTAX("br %!a0"); +#line 350 "rl78-decode.opc" + ID(branch); DC(IMMU(2)); + + } + break; + case 0xee: + { + /** 1110 1110 br $%!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1110 br $%!a0 */", + op[0]); + } + SYNTAX("br $%!a0"); +#line 353 "rl78-decode.opc" + ID(branch); DC(pc+IMMS(2)+3); + + } + break; + case 0xef: + { + /** 1110 1111 br $%a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1110 1111 br $%a0 */", + op[0]); + } + SYNTAX("br $%a0"); +#line 356 "rl78-decode.opc" + ID(branch); DC(pc+IMMS(1)+2); + + } + break; + case 0xf0: + case 0xf1: + case 0xf2: + case 0xf3: + { + /** 1111 00rg clrb %0 */ +#line 443 "rl78-decode.opc" + int rg AU = op[0] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 00rg clrb %0 */", + op[0]); + printf (" rg = 0x%x\n", rg); + } + SYNTAX("clrb %0"); +#line 443 "rl78-decode.opc" + ID(mov); DRB(rg); SC(0); + + } + break; + case 0xf4: + { + /** 1111 0100 clrb %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 0100 clrb %0 */", + op[0]); + } + SYNTAX("clrb %0"); +#line 446 "rl78-decode.opc" + ID(mov); DM(None, SADDR); SC(0); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xf5: + { + /** 1111 0101 clrb %e0%!0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 0101 clrb %e0%!0 */", + op[0]); + } + SYNTAX("clrb %e0%!0"); +#line 440 "rl78-decode.opc" + ID(mov); DM(None, IMMU(2)); SC(0); + + } + break; + case 0xf6: + { + /** 1111 0110 clrw %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 0110 clrw %0 */", + op[0]); + } + SYNTAX("clrw %0"); +#line 451 "rl78-decode.opc" + ID(mov); DR(AX); SC(0); + + } + break; + case 0xf7: + { + /** 1111 0111 clrw %0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 0111 clrw %0 */", + op[0]); + } + SYNTAX("clrw %0"); +#line 454 "rl78-decode.opc" + ID(mov); DR(BC); SC(0); + + /*----------------------------------------------------------------------*/ + + } + break; + case 0xf8: + { + /** 1111 1000 mov %0, %1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1000 mov %0, %1 */", + op[0]); + } + SYNTAX("mov %0, %1"); +#line 684 "rl78-decode.opc" + ID(mov); DR(C); SM(None, SADDR); + + } + break; + case 0xf9: + { + /** 1111 1001 mov %0, %e1%!1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1001 mov %0, %e1%!1 */", + op[0]); + } + SYNTAX("mov %0, %e1%!1"); +#line 681 "rl78-decode.opc" + ID(mov); DR(C); SM(None, IMMU(2)); + + } + break; + case 0xfc: + { + /** 1111 1100 call !%!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1100 call !%!a0 */", + op[0]); + } + SYNTAX("call !%!a0"); +#line 400 "rl78-decode.opc" + ID(call); DC(IMMU(3)); + + } + break; + case 0xfd: + { + /** 1111 1101 call %!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1101 call %!a0 */", + op[0]); + } + SYNTAX("call %!a0"); +#line 403 "rl78-decode.opc" + ID(call); DC(IMMU(2)); + + } + break; + case 0xfe: + { + /** 1111 1110 call $%!a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1110 call $%!a0 */", + op[0]); + } + SYNTAX("call $%!a0"); +#line 406 "rl78-decode.opc" + ID(call); DC(pc+IMMS(2)+3); + + } + break; + case 0xff: + { + /** 1111 1111 brk1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 1111 1111 brk1 */", + op[0]); + } + SYNTAX("brk1"); +#line 364 "rl78-decode.opc" + ID(break); + + } + break; + } +#line 1261 "rl78-decode.opc" + + return rl78->n_bytes; +} diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc new file mode 100644 index 00000000000..c5cdf296b3d --- /dev/null +++ b/opcodes/rl78-decode.opc @@ -0,0 +1,1263 @@ +/* -*- c -*- */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rl78.h" + +static int trace = 0; + +typedef struct +{ + RL78_Opcode_Decoded * rl78; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +#define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__ +#define OP(n,t,r,a) (rl78->op[n].type = t, \ + rl78->op[n].reg = r, \ + rl78->op[n].addend = a ) +#define OPX(n,t,r1,r2,a) \ + (rl78->op[n].type = t, \ + rl78->op[n].reg = r1, \ + rl78->op[n].reg2 = r2, \ + rl78->op[n].addend = a ) + +#define W() rl78->size = RL78_Word + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr)) +#define B ((unsigned long) GETBYTE()) + +#define SYNTAX(x) rl78->syntax = x + +#define UNSUPPORTED() \ + rl78->syntax = "*unknown*" + +#define RB(x) ((x)+RL78_Reg_X) +#define RW(x) ((x)+RL78_Reg_AX) + +#define Fz rl78->flags = RL78_PSW_Z +#define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC +#define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY +#define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY +#define Fa rl78->flags = RL78_PSW_AC +#define Fc rl78->flags = RL78_PSW_CY +#define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY + +#define IMMU(bytes) immediate (bytes, 0, ld) +#define IMMS(bytes) immediate (bytes, 1, ld) + +static int +immediate (int bytes, int sign_extend, LocalData * ld) +{ + unsigned long i = 0; + + switch (bytes) + { + case 1: + i |= B; + if (sign_extend && (i & 0x80)) + i -= 0x100; + break; + case 2: + i |= B; + i |= B << 8; + if (sign_extend && (i & 0x8000)) + i -= 0x10000; + break; + case 3: + i |= B; + i |= B << 8; + i |= B << 16; + if (sign_extend && (i & 0x800000)) + i -= 0x1000000; + break; + default: + fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes); + abort(); + } + return i; +} + +#define DC(c) OP (0, RL78_Operand_Immediate, 0, c) +#define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) +#define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0) +#define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0) +#define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a) +#define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) +#define DE() rl78->op[0].use_es = 1 +#define DB(b) set_bit (rl78->op, b) +#define DCY() DR(PSW); DB(0) +#define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0); + +#define SC(c) OP (1, RL78_Operand_Immediate, 0, c) +#define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0) +#define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0) +#define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0) +#define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a) +#define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) +#define SE() rl78->op[1].use_es = 1 +#define SB(b) set_bit (rl78->op+1, b) +#define SCY() SR(PSW); SB(0) +#define COND(c) rl78->op[1].condition = RL78_Condition_##c +#define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0); + +static void +set_bit (RL78_Opcode_Operand *op, int bit) +{ + op->bit_number = bit; + switch (op->type) { + case RL78_Operand_Register: + op->type = RL78_Operand_Bit; + break; + case RL78_Operand_Indirect: + op->type = RL78_Operand_BitIndirect; + break; + default: + break; + } +} + +static int +saddr (int x) +{ + if (x < 0x20) + return 0xfff00 + x; + return 0xffe00 + x; +} + +static int +sfr (int x) +{ + return 0xfff00 + x; +} + +#define SADDR saddr (IMMU (1)) +#define SFR sfr (IMMU (1)) + +int +rl78_decode_opcode (unsigned long pc AU, + RL78_Opcode_Decoded * rl78, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op_buf[20] = {0}; + unsigned char *op = op_buf; + int op0, op1; + + lds.rl78 = rl78; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rl78, 0, sizeof (*rl78)); + + start_again: + +/* Byte registers, not including A. */ +/** VARY rba 000 010 011 100 101 110 111 */ +/* Word registers, not including AX. */ +/** VARY ra 01 10 11 */ + +/*----------------------------------------------------------------------*/ +/* ES: prefix */ + +/** 0001 0001 es: */ + DE(); SE(); + op ++; + pc ++; + goto start_again; + +/*----------------------------------------------------------------------*/ + +/** 0000 1111 add %0, %e1%!1 */ + ID(add); DR(A); SM(None, IMMU(2)); Fzac; + +/** 0000 1101 add %0, %e1%1 */ + ID(add); DR(A); SM(HL, 0); Fzac; + +/** 0110 0001 1000 000 add %0, %e1%1 */ + ID(add); DR(A); SM2(HL, B, 0); Fzac; + +/** 0000 1110 add %0, %e1%1 */ + ID(add); DR(A); SM(HL, IMMU(1)); Fzac; + +/** 0110 0001 1000 0010 add %0, %e1%1 */ + ID(add); DR(A); SM2(HL, C, 0); Fzac; + +/** 0000 1100 add %0, #%1 */ + ID(add); DR(A); SC(IMMU(1)); Fzac; + +/** 0110 0001 0000 1rba add %0, %1 */ + ID(add); DR(A); SRB(rba); Fzac; + +/** 0000 1011 add %0, %1 */ + ID(add); DR(A); SM(None, SADDR); Fzac; + +/** 0110 0001 0000 0reg add %0, %1 */ + ID(add); DRB(reg); SR(A); Fzac; + +/** 0000 1010 add %0, #%1 */ + ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0001 1111 addc %0, %e1%!1 */ + ID(addc); DR(A); SM(None, IMMU(2)); Fzac; + +/** 0001 1101 addc %0, %e1%1 */ + ID(addc); DR(A); SM(HL, 0); Fzac; + +/** 0110 0001 1001 0000 addc %0, %e1%1 */ + ID(addc); DR(A); SM2(HL, B, 0); Fzac; + +/** 0110 0001 1001 0010 addc %0, %e1%1 */ + ID(addc); DR(A); SM2(HL, C, 0); Fzac; + +/** 0001 1110 addc %0, %e1%1 */ + ID(addc); DR(A); SM(HL, IMMU(1)); Fzac; + +/** 0001 1100 addc %0, #%1 */ + ID(addc); DR(A); SC(IMMU(1)); Fzac; + +/** 0110 0001 0001 1rba addc %0, %1 */ + ID(addc); DR(A); SRB(rba); Fzac; + +/** 0110 0001 0001 0reg addc %0, %1 */ + ID(addc); DRB(reg); SR(A); Fzac; + +/** 0001 1011 addc %0, %1 */ + ID(addc); DR(A); SM(None, SADDR); Fzac; + +/** 0001 1010 addc %0, #%1 */ + ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0000 0010 addw %0, %e1%!1 */ + ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; + +/** 0110 0001 0000 1001 addw %0, %e1%1 */ + ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + +/** 0000 0100 addw %0, #%1 */ + ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; + +/** 0000 0rw1 addw %0, %1 */ + ID(add); W(); DR(AX); SRW(rw); Fzac; + +/** 0000 0110 addw %0, %1 */ + ID(add); W(); DR(AX); SM(None, SADDR); Fzac; + +/** 0001 0000 addw %0, #%1 */ + ID(add); W(); DR(SP); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0101 1111 and %0, %e1%!1 */ + ID(and); DR(A); SM(None, IMMU(2)); Fz; + +/** 0101 1101 and %0, %e1%1 */ + ID(and); DR(A); SM(HL, 0); Fz; + +/** 0110 0001 1101 0000 and %0, %e1%1 */ + ID(and); DR(A); SM2(HL, B, 0); Fz; + +/** 0101 1110 and %0, %e1%1 */ + ID(and); DR(A); SM(HL, IMMU(1)); Fz; + +/** 0110 0001 1101 0010 and %0, %e1%1 */ + ID(and); DR(A); SM2(HL, C, 0); Fz; + +/** 0101 1100 and %0, #%1 */ + ID(and); DR(A); SC(IMMU(1)); Fz; + +/** 0110 0001 0101 1rba and %0, %1 */ + ID(and); DR(A); SRB(rba); Fz; + +/** 0110 0001 0101 0reg and %0, %1 */ + ID(and); DRB(reg); SR(A); Fz; + +/** 0101 1011 and %0, %1 */ + ID(and); DR(A); SM(None, SADDR); Fz; + +/** 0101 1010 and %0, #%1 */ + ID(and); DM(None, SADDR); SC(IMMU(1)); Fz; + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 1bit 0101 and1 cy, %e1%1 */ + ID(and); DCY(); SM(HL, 0); SB(bit); + +/** 0111 0001 1bit 1101 and1 cy, %1 */ + ID(and); DCY(); SR(A); SB(bit); + +/** 0111 0001 0bit 1101 and1 cy, %s1 */ + ID(and); DCY(); SM(None, SFR); SB(bit); + +/** 0111 0001 0bit 0101 and1 cy, %s1 */ + ID(and); DCY(); SM(None, SADDR); SB(bit); + +/*----------------------------------------------------------------------*/ + +/* Note that the branch insns need to be listed before the shift + ones, as "shift count of zero" means "branch insn" */ + +/** 1101 1100 bc $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C); + +/** 1101 1110 bnc $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC); + +/** 0110 0001 1100 0011 bh $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H); + +/** 0110 0001 1101 0011 bnh $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH); + +/** 1101 1101 bz $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z); + +/** 1101 1111 bnz $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ); + +/*----------------------------------------------------------------------*/ + +/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F); + +/** 0011 0001 0bit 0101 bf %1, $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); + +/** 0011 0001 1bit 0100 bf %s1, $%a0 */ + ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F); + +/** 0011 0001 0bit 0100 bf %s1, $%a0 */ + ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F); + +/*----------------------------------------------------------------------*/ + +/** 1110 1100 br !%!a0 */ + ID(branch); DC(IMMU(3)); + +/** 1110 1101 br %!a0 */ + ID(branch); DC(IMMU(2)); + +/** 1110 1110 br $%!a0 */ + ID(branch); DC(pc+IMMS(2)+3); + +/** 1110 1111 br $%a0 */ + ID(branch); DC(pc+IMMS(1)+2); + +/** 0110 0001 1100 1011 br ax */ + ID(branch); DR(AX); + +/*----------------------------------------------------------------------*/ + +/** 1111 1111 brk1 */ + ID(break); + +/** 0110 0001 1100 1100 brk */ + ID(break); + +/*----------------------------------------------------------------------*/ + +/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); + +/** 0011 0001 0bit 0011 bt %1, $%a0 */ + ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); + +/** 0011 0001 1bit 0010 bt %s1, $%a0 */ + ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + +/** 0011 0001 0bit 0010 bt %s1, $%a0 */ + ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + +/*----------------------------------------------------------------------*/ + +/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */ + ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); + +/** 0011 0001 0bit 0001 btclr %1, $%a0 */ + ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); + +/** 0011 0001 1bit 0000 btclr %s1, $%a0 */ + ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + +/** 0011 0001 0bit 0000 btclr %s1, $%a0 */ + ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); + +/*----------------------------------------------------------------------*/ + +/** 1111 1100 call !%!a0 */ + ID(call); DC(IMMU(3)); + +/** 1111 1101 call %!a0 */ + ID(call); DC(IMMU(2)); + +/** 1111 1110 call $%!a0 */ + ID(call); DC(pc+IMMS(2)+3); + +/** 0110 0001 11rg 1010 call %0 */ + ID(call); DRW(rg); + +/** 0110 0001 1nnn 01mm callt [%x0] */ + ID(call); DM(None, 0x80 + mm*16 + nnn*2); + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 0bit 1000 clr1 %e0%!0 */ + ID(mov); DM(None, IMMU(2)); DB(bit); SC(0); + +/** 0111 0001 1bit 0011 clr1 %e0%0 */ + ID(mov); DM(HL, 0); DB(bit); SC(0); + +/** 0111 0001 1bit 1011 clr1 %0 */ + ID(mov); DR(A); DB(bit); SC(0); + +/** 0111 0001 1000 1000 clr1 cy */ + ID(mov); DCY(); SC(0); + +/** 0111 0001 0bit 1011 clr1 %s0 */ + op0 = SFR; + ID(mov); DM(None, op0); DB(bit); SC(0); + if (op0 == RL78_SFR_PSW && bit == 7) + rl78->syntax = "di"; + +/** 0111 0001 0bit 0011 clr1 %0 */ + ID(mov); DM(None, SADDR); DB(bit); SC(0); + +/*----------------------------------------------------------------------*/ + +/** 1111 0101 clrb %e0%!0 */ + ID(mov); DM(None, IMMU(2)); SC(0); + +/** 1111 00rg clrb %0 */ + ID(mov); DRB(rg); SC(0); + +/** 1111 0100 clrb %0 */ + ID(mov); DM(None, SADDR); SC(0); + +/*----------------------------------------------------------------------*/ + +/** 1111 0110 clrw %0 */ + ID(mov); DR(AX); SC(0); + +/** 1111 0111 clrw %0 */ + ID(mov); DR(BC); SC(0); + +/*----------------------------------------------------------------------*/ + +/** 0100 0000 cmp %e0%!0, #%1 */ + ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac; + +/** 0100 1010 cmp %0, #%1 */ + ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac; + +/** 0100 1111 cmp %0, %e1%!1 */ + ID(cmp); DR(A); SM(None, IMMU(2)); Fzac; + +/** 0100 1101 cmp %0, %e1%1 */ + ID(cmp); DR(A); SM(HL, 0); Fzac; + +/** 0110 0001 1100 0000 cmp %0, %e1%1 */ + ID(cmp); DR(A); SM2(HL, B, 0); Fzac; + +/** 0110 0001 1100 0010 cmp %0, %e1%1 */ + ID(cmp); DR(A); SM2(HL, C, 0); Fzac; + +/** 0100 1110 cmp %0, %e1%1 */ + ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac; + +/** 0100 1100 cmp %0, #%1 */ + ID(cmp); DR(A); SC(IMMU(1)); Fzac; + +/** 0110 0001 0100 1rba cmp %0, %1 */ + ID(cmp); DR(A); SRB(rba); Fzac; + +/** 0110 0001 0100 0reg cmp %0, %1 */ + ID(cmp); DRB(reg); SR(A); Fzac; + +/** 0100 1011 cmp %0, %1 */ + ID(cmp); DR(A); SM(None, SADDR); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 1101 0101 cmp0 %e0%!0 */ + ID(cmp); DM(None, IMMU(2)); SC(0); Fzac; + +/** 1101 00rg cmp0 %0 */ + ID(cmp); DRB(rg); SC(0); Fzac; + +/** 1101 0100 cmp0 %0 */ + ID(cmp); DM(None, SADDR); SC(0); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1101 1110 cmps %0, %e1%1 */ + ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0100 0010 cmpw %0, %e1%!1 */ + ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac; + +/** 0110 0001 0100 1001 cmpw %0, %e1%1 */ + ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + +/** 0100 0100 cmpw %0, #%1 */ + ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac; + +/** 0100 0ra1 cmpw %0, %1 */ + ID(cmp); W(); DR(AX); SRW(ra); Fzac; + +/** 0100 0110 cmpw %0, %1 */ + ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 1011 0000 dec %e0%!0 */ + ID(sub); DM(None, IMMU(2)); SC(1); Fza; + +/** 0110 0001 0110 1001 dec %e0%0 */ + ID(sub); DM(HL, IMMU(1)); SC(1); Fza; + +/** 1001 0reg dec %0 */ + ID(sub); DRB(reg); SC(1); Fza; + +/** 1011 0100 dec %0 */ + ID(sub); DM(None, SADDR); SC(1); Fza; + +/*----------------------------------------------------------------------*/ + +/** 1011 0010 decw %e0%!0 */ + ID(sub); W(); DM(None, IMMU(2)); SC(1); + +/** 0110 0001 1000 1001 decw %e0%0 */ + ID(sub); W(); DM(HL, IMMU(1)); SC(1); + +/** 1011 0rg1 decw %0 */ + ID(sub); W(); DRW(rg); SC(1); + +/** 1011 0110 decw %0 */ + ID(sub); W(); DM(None, SADDR); SC(1); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1110 1101 halt */ + ID(halt); + +/*----------------------------------------------------------------------*/ + +/** 1010 0000 inc %e0%!0 */ + ID(add); DM(None, IMMU(2)); SC(1); Fza; + +/** 0110 0001 0101 1001 inc %e0%0 */ + ID(add); DM(HL, IMMU(1)); SC(1); Fza; + +/** 1000 0reg inc %0 */ + ID(add); DRB(reg); SC(1); Fza; + +/** 1010 0100 inc %0 */ + ID(add); DM(None, SADDR); SC(1); Fza; + +/*----------------------------------------------------------------------*/ + +/** 1010 0010 incw %e0%!0 */ + ID(add); W(); DM(None, IMMU(2)); SC(1); + +/** 0110 0001 0111 1001 incw %e0%0 */ + ID(add); W(); DM(HL, IMMU(1)); SC(1); + +/** 1010 0rg1 incw %0 */ + ID(add); W(); DRW(rg); SC(1); + +/** 1010 0110 incw %0 */ + ID(add); W(); DM(None, SADDR); SC(1); + +/*----------------------------------------------------------------------*/ + +/** 1100 1111 mov %e0%!0, #%1 */ + ID(mov); DM(None, IMMU(2)); SC(IMMU(1)); + +/** 1001 1111 mov %e0%!0, %1 */ + ID(mov); DM(None, IMMU(2)); SR(A); + +/** 1001 1001 mov %e0%0,%1 */ + ID(mov); DM(DE, 0); SR(A); + +/** 1100 1010 mov %e0%0, #%1 */ + ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); + +/** 1001 1010 mov %e0%0, %1 */ + ID(mov); DM(DE, IMMU(1)); SR(A); + +/** 1001 1011 mov %e0%0,%1 */ + ID(mov); DM(HL, 0); SR(A); + +/** 0110 0001 1101 1001 mov %e0%0, %1 */ + ID(mov); DM2(HL, B, 0); SR(A); + +/** 1100 1100 mov %e0%0, #%1 */ + ID(mov); DM(HL, IMMU(1)); SC(IMMU(1)); + +/** 1001 1100 mov %e0%0, %1 */ + ID(mov); DM(HL, IMMU(1)); SR(A); + +/** 0110 0001 1111 1001 mov %e0%0, %1 */ + ID(mov); DM2(HL, C, 0); SR(A); + +/** 1100 1000 mov %0, #%1 */ + ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); + +/** 1001 1000 mov %0, %1 */ + ID(mov); DM(SP, IMMU(1)); SR(A); + +/** 1000 1111 mov %0, %e1%!1 */ + ID(mov); DR(A); SM(None, IMMU(2)); + +/** 1000 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM(DE, 0); + +/** 1000 1010 mov %0, %e1%1 */ + ID(mov); DR(A); SM(DE, IMMU(1)); + +/** 1000 1011 mov %0, %e1%1 */ + ID(mov); DR(A); SM(HL, 0); + +/** 1000 1100 mov %0, %e1%1 */ + ID(mov); DR(A); SM(HL, IMMU(1)); + +/** 0110 0001 1100 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM2(HL, B, 0); + +/** 0110 0001 1110 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM2(HL, C, 0); + +/** 1000 1000 mov %0, %e1%1 */ + ID(mov); DR(A); SM(SP, IMMU(1)); + +/** 0101 0reg mov %0, #%1 */ + ID(mov); DRB(reg); SC(IMMU(1)); + +/** 0110 0rba mov %0, %1 */ + ID(mov); DR(A); SRB(rba); + +/** 1000 1110 1111 1101 mov %0, %1 */ + ID(mov); DR(A); SR(ES); + +/** 0000 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM(B, IMMU(2)); + +/** 0100 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM(BC, IMMU(2)); + +/** 0010 1001 mov %0, %e1%1 */ + ID(mov); DR(A); SM(C, IMMU(2)); + +/** 1000 1110 mov %0, %s1 */ + ID(mov); DR(A); SM(None, SFR); + +/** 1000 1101 mov %0, %1 */ + ID(mov); DR(A); SM(None, SADDR); + +/** 1110 1001 mov %0, %e1%!1 */ + ID(mov); DR(B); SM(None, IMMU(2)); + +/** 0111 0rba mov %0, %1 */ + ID(mov); DRB(rba); SR(A); + +/** 1110 1000 mov %0, %1 */ + ID(mov); DR(B); SM(None, SADDR); + +/** 1111 1001 mov %0, %e1%!1 */ + ID(mov); DR(C); SM(None, IMMU(2)); + +/** 1111 1000 mov %0, %1 */ + ID(mov); DR(C); SM(None, SADDR); + +/** 1101 1001 mov %0, %e1%!1 */ + ID(mov); DR(X); SM(None, IMMU(2)); + +/** 1101 1000 mov %0, %1 */ + ID(mov); DR(X); SM(None, SADDR); + +/** 1001 1110 1111 1100 mov %0, %1 */ + ID(mov); DR(CS); SR(A); + +/** 0100 0001 mov %0, #%1 */ + ID(mov); DR(ES); SC(IMMU(1)); + +/** 1001 1110 1111 1101 mov %0, %1 */ + ID(mov); DR(ES); SR(A); + +/** 0110 0001 1011 1000 mov %0, %1 */ + ID(mov); DR(ES); SM(None, SADDR); + +/** 0001 1001 mov %e0%0, #%1 */ + ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); + +/** 0001 1000 mov %e0%0, %1 */ + ID(mov); DM(B, IMMU(2)); SR(A); + +/** 0011 1001 mov %e0%0, #%1 */ + ID(mov); DM(BC, IMMU(2)); SC(IMMU(1)); + +/** 0100 1000 mov %e0%0, %1 */ + ID(mov); DM(BC, IMMU(2)); SR(A); + +/** 0011 1000 mov %e0%0, #%1 */ + ID(mov); DM(C, IMMU(2)); SC(IMMU(1)); + +/** 0010 1000 mov %e0%0, %1 */ + ID(mov); DM(C, IMMU(2)); SR(A); + +/** 1100 1101 mov %0, #%1 */ + ID(mov); DM(None, SADDR); SC(IMMU(1)); + +/** 1001 1101 mov %0, %1 */ + ID(mov); DM(None, SADDR); SR(A); + +/** 1100 1110 mov %s0, #%1 */ + op0 = SFR; + op1 = IMMU(1); + ID(mov); DM(None, op0); SC(op1); + if (op0 == 0xffffb) + switch (op1) + { + case 0x01: + rl78->syntax = "mulhu"; ID(mulhu); + break; + case 0x02: + rl78->syntax = "mulh"; ID(mulh); + break; + case 0x03: + rl78->syntax = "divhu"; ID(divhu); + break; + case 0x04: + rl78->syntax = "divwu"; ID(divwu); + break; + case 0x05: + rl78->syntax = "machu"; ID(machu); + break; + case 0x06: + rl78->syntax = "mach"; ID(mach); + break; + } + +/** 1001 1110 mov %0, %1 */ + ID(mov); DM(None, SFR); SR(A); + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 1bit 0001 mov1 %e0%0, cy */ + ID(mov); DM(HL, 0); DB(bit); SCY(); + +/** 0111 0001 1bit 1001 mov1 %e0%0, cy */ + ID(mov); DR(A); DB(bit); SCY(); + +/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */ + ID(mov); DCY(); SM(HL, 0); SB(bit); + +/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */ + ID(mov); DCY(); SR(A); SB(bit); + +/** 0111 0001 0bit 0100 mov1 cy, %1 */ + ID(mov); DCY(); SM(None, SADDR); SB(bit); + +/** 0111 0001 0bit 1100 mov1 cy, %s1 */ + ID(mov); DCY(); SM(None, SFR); SB(bit); + +/** 0111 0001 0bit 0001 mov1 %0, cy */ + ID(mov); DM(None, SADDR); DB(bit); SCY(); + +/** 0111 0001 0bit 1001 mov1 %s0, cy */ + ID(mov); DM(None, SFR); DB(bit); SCY(); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1100 1110 movs %e0%0, %1 */ + ID(mov); DM(HL, IMMU(1)); SR(X); Fzc; + +/*----------------------------------------------------------------------*/ + +/** 1011 1111 movw %e0%!0, %1 */ + ID(mov); W(); DM(None, IMMU(2)); SR(AX); + +/** 1011 1001 movw %e0%0, %1 */ + ID(mov); W(); DM(DE, 0); SR(AX); + +/** 1011 1010 movw %e0%0, %1 */ + ID(mov); W(); DM(DE, IMMU(1)); SR(AX); + +/** 1011 1011 movw %e0%0, %1 */ + ID(mov); W(); DM(HL, 0); SR(AX); + +/** 1011 1100 movw %e0%0, %1 */ + ID(mov); W(); DM(HL, IMMU(1)); SR(AX); + +/** 1011 1000 movw %0, %1 */ + ID(mov); W(); DM(SP, IMMU(1)); SR(AX); + +/** 1010 1111 movw %0, %e1%!1 */ + ID(mov); W(); DR(AX); SM(None, IMMU(2)); + + +/** 1010 1001 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(DE, 0); + +/** 1010 1010 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(DE, IMMU(1)); + +/** 1010 1011 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(HL, 0); + +/** 1010 1100 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(HL, IMMU(1)); + +/** 1010 1000 movw %0, %1 */ + ID(mov); W(); DR(AX); SM(SP, IMMU(1)); + +/** 0011 0rg0 movw %0, #%1 */ + ID(mov); W(); DRW(rg); SC(IMMU(2)); + +/** 0001 0ra1 movw %0, %1 */ + ID(mov); W(); DR(AX); SRW(ra); + +/** 0001 0ra0 movw %0, %1 */ + ID(mov); W(); DRW(ra); SR(AX); + +/** 0101 1001 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(B, IMMU(2)); + +/** 0110 1001 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(C, IMMU(2)); + +/** 0111 1001 movw %0, %e1%1 */ + ID(mov); W(); DR(AX); SM(BC, IMMU(2)); + +/** 0101 1000 movw %e0%0, %1 */ + ID(mov); W(); DM(B, IMMU(2)); SR(AX); + +/** 0110 1000 movw %e0%0, %1 */ + ID(mov); W(); DM(C, IMMU(2)); SR(AX); + +/** 0111 1000 movw %e0%0, %1 */ + ID(mov); W(); DM(BC, IMMU(2)); SR(AX); + +/** 1010 1101 movw %0, %1 */ + ID(mov); W(); DR(AX); SM(None, SADDR); + +/** 1010 1110 movw %0, %s1 */ + ID(mov); W(); DR(AX); SM(None, SFR); + +/** 11ra 1011 movw %0, %e1%!1 */ + ID(mov); W(); DRW(ra); SM(None, IMMU(2)); + +/** 11ra 1010 movw %0, %1 */ + ID(mov); W(); DRW(ra); SM(None, SADDR); + +/** 1100 1001 movw %0, #%1 */ + ID(mov); W(); DM(None, SADDR); SC(IMMU(2)); + +/** 1011 1101 movw %0, %1 */ + ID(mov); W(); DM(None, SADDR); SR(AX); + +/** 1100 1011 movw %0, #%1 */ + ID(mov); W(); DM(None, SFR); SC(IMMU(2)); + +/** 1011 1110 movw %0, %1 */ + ID(mov); W(); DM(None, SFR); SR(AX); + +/*----------------------------------------------------------------------*/ + +/** 1101 0110 mulu x */ + ID(mulu); + +/*----------------------------------------------------------------------*/ + +/** 0000 0000 nop */ + ID(nop); + +/*----------------------------------------------------------------------*/ + +/** 1110 0101 oneb %e0%!0 */ + ID(mov); DM(None, IMMU(2)); SC(1); + +/** 1110 00rg oneb %0 */ + ID(mov); DRB(rg); SC(1); + +/** 1110 0100 oneb %0 */ + ID(mov); DM(None, SADDR); SC(1); + +/*----------------------------------------------------------------------*/ + +/** 1110 0110 onew %0 */ + ID(mov); DR(AX); SC(1); + +/** 1110 0111 onew %0 */ + ID(mov); DR(BC); SC(1); + +/*----------------------------------------------------------------------*/ + +/** 0110 1111 or %0, %e1%!1 */ + ID(or); DR(A); SM(None, IMMU(2)); Fz; + +/** 0110 1101 or %0, %e1%1 */ + ID(or); DR(A); SM(HL, 0); Fz; + +/** 0110 0001 1110 0000 or %0, %e1%1 */ + ID(or); DR(A); SM2(HL, B, 0); Fz; + +/** 0110 1110 or %0, %e1%1 */ + ID(or); DR(A); SM(HL, IMMU(1)); Fz; + +/** 0110 0001 1110 0010 or %0, %e1%1 */ + ID(or); DR(A); SM2(HL, C, 0); Fz; + +/** 0110 1100 or %0, #%1 */ + ID(or); DR(A); SC(IMMU(1)); Fz; + +/** 0110 0001 0110 1rba or %0, %1 */ + ID(or); DR(A); SRB(rba); Fz; + +/** 0110 0001 0110 0reg or %0, %1 */ + ID(or); DRB(reg); SR(A); Fz; + +/** 0110 1011 or %0, %1 */ + ID(or); DR(A); SM(None, SADDR); Fz; + +/** 0110 1010 or %0, #%1 */ + ID(or); DM(None, SADDR); SC(IMMU(1)); Fz; + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 1bit 0110 or1 cy, %e1%1 */ + ID(or); DCY(); SM(HL, 0); SB(bit); + +/** 0111 0001 1bit 1110 or1 cy, %1 */ + ID(or); DCY(); SR(A); SB(bit); + +/** 0111 0001 0bit 1110 or1 cy, %s1 */ + ID(or); DCY(); SM(None, SFR); SB(bit); + +/** 0111 0001 0bit 0110 or1 cy, %s1 */ + ID(or); DCY(); SM(None, SADDR); SB(bit); + +/*----------------------------------------------------------------------*/ + +/** 1100 0rg0 pop %0 */ + ID(mov); W(); DRW(rg); SPOP(); + +/** 0110 0001 1100 1101 pop %s0 */ + ID(mov); W(); DR(PSW); SPOP(); + +/*----------------------------------------------------------------------*/ + +/** 1100 0rg1 push %1 */ + ID(mov); W(); DPUSH(); SRW(rg); + +/** 0110 0001 1101 1101 push %s1 */ + ID(mov); W(); DPUSH(); SR(PSW); + +/*----------------------------------------------------------------------*/ + +/** 1101 0111 ret */ + ID(ret); + +/** 0110 0001 1111 1100 reti */ + ID(reti); + +/** 0110 0001 1110 1100 retb */ + ID(reti); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1110 1011 rol %0, %1 */ + ID(rol); DR(A); SC(1); + +/** 0110 0001 1101 1100 rolc %0, %1 */ + ID(rolc); DR(A); SC(1); + +/** 0110 0001 111r 1110 rolwc %0, %1 */ + ID(rolc); W(); DRW(r); SC(1); + +/** 0110 0001 1101 1011 ror %0, %1 */ + ID(ror); DR(A); SC(1); + +/** 0110 0001 1111 1011 rorc %0, %1 */ + ID(rorc); DR(A); SC(1); + +/*----------------------------------------------------------------------*/ + +/* Note that the branch insns need to be listed before the shift + ones, as "shift count of zero" means "branch insn" */ + +/** 0011 0001 0cnt 1011 sar %0, %1 */ + ID(sar); DR(A); SC(cnt); + +/** 0011 0001 wcnt 1111 sarw %0, %1 */ + ID(sar); W(); DR(AX); SC(wcnt); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 11rb 1111 sel rb%1 */ + ID(sel); SC(rb); + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 0bit 0000 set1 %e0%!0 */ + ID(mov); DM(None, IMMU(2)); DB(bit); SC(1); + +/** 0111 0001 1bit 0010 set1 %e0%0 */ + ID(mov); DM(HL, 0); DB(bit); SC(1); + +/** 0111 0001 1bit 1010 set1 %0 */ + ID(mov); DR(A); DB(bit); SC(1); + +/** 0111 0001 1000 0000 set1 cy */ + ID(mov); DCY(); SC(1); + +/** 0111 0001 0bit 1010 set1 %s0 */ + op0 = SFR; + ID(mov); DM(None, op0); DB(bit); SC(1); + if (op0 == RL78_SFR_PSW && bit == 7) + rl78->syntax = "ei"; + +/** 0111 0001 0bit 0010 set1 %0 */ + ID(mov); DM(None, SADDR); DB(bit); SC(1); + +/*----------------------------------------------------------------------*/ + +/** 0011 0001 0cnt 1001 shl %0, %1 */ + ID(shl); DR(A); SC(cnt); + +/** 0011 0001 0cnt 1000 shl %0, %1 */ + ID(shl); DR(B); SC(cnt); + +/** 0011 0001 0cnt 0111 shl %0, %1 */ + ID(shl); DR(C); SC(cnt); + +/** 0011 0001 wcnt 1101 shlw %0, %1 */ + ID(shl); W(); DR(AX); SC(wcnt); + +/** 0011 0001 wcnt 1100 shlw %0, %1 */ + ID(shl); W(); DR(BC); SC(wcnt); + +/*----------------------------------------------------------------------*/ + +/** 0011 0001 0cnt 1010 shr %0, %1 */ + ID(shr); DR(A); SC(cnt); + +/** 0011 0001 wcnt 1110 shrw %0, %1 */ + ID(shr); W(); DR(AX); SC(wcnt); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1100 1000 sk%c1 */ + ID(skip); COND(C); + +/** 0110 0001 1110 0011 sk%c1 */ + ID(skip); COND(H); + +/** 0110 0001 1101 1000 sk%c1 */ + ID(skip); COND(NC); + +/** 0110 0001 1111 0011 sk%c1 */ + ID(skip); COND(NH); + +/** 0110 0001 1111 1000 sk%c1 */ + ID(skip); COND(NZ); + +/** 0110 0001 1110 1000 sk%c1 */ + ID(skip); COND(Z); + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1111 1101 stop */ + ID(stop); + +/*----------------------------------------------------------------------*/ + +/** 0010 1111 sub %0, %e1%!1 */ + ID(sub); DR(A); SM(None, IMMU(2)); Fzac; + +/** 0010 1101 sub %0, %e1%1 */ + ID(sub); DR(A); SM(HL, 0); Fzac; + +/** 0110 0001 1010 000 sub %0, %e1%1 */ + ID(sub); DR(A); SM2(HL, B, 0); Fzac; + +/** 0010 1110 sub %0, %e1%1 */ + ID(sub); DR(A); SM(HL, IMMU(1)); Fzac; + +/** 0110 0001 1010 0010 sub %0, %e1%1 */ + ID(sub); DR(A); SM2(HL, C, 0); Fzac; + +/** 0010 1100 sub %0, #%1 */ + ID(sub); DR(A); SC(IMMU(1)); Fzac; + +/** 0110 0001 0010 1rba sub %0, %1 */ + ID(sub); DR(A); SRB(rba); Fzac; + +/** 0010 1011 sub %0, %1 */ + ID(sub); DR(A); SM(None, SADDR); Fzac; + +/** 0110 0001 0010 0reg sub %0, %1 */ + ID(sub); DRB(reg); SR(A); Fzac; + +/** 0010 1010 sub %0, #%1 */ + ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0011 1111 subc %0, %e1%!1 */ + ID(subc); DR(A); SM(None, IMMU(2)); Fzac; + +/** 0011 1101 subc %0, %e1%1 */ + ID(subc); DR(A); SM(HL, 0); Fzac; + +/** 0110 0001 1011 0000 subc %0, %e1%1 */ + ID(subc); DR(A); SM2(HL, B, 0); Fzac; + +/** 0110 0001 1011 0010 subc %0, %e1%1 */ + ID(subc); DR(A); SM2(HL, C, 0); Fzac; + +/** 0011 1110 subc %0, %e1%1 */ + ID(subc); DR(A); SM(HL, IMMU(1)); Fzac; + +/** 0011 1100 subc %0, #%1 */ + ID(subc); DR(A); SC(IMMU(1)); Fzac; + +/** 0110 0001 0011 1rba subc %0, %1 */ + ID(subc); DR(A); SRB(rba); Fzac; + +/** 0110 0001 0011 0reg subc %0, %1 */ + ID(subc); DRB(reg); SR(A); Fzac; + +/** 0011 1011 subc %0, %1 */ + ID(subc); DR(A); SM(None, SADDR); Fzac; + +/** 0011 1010 subc %0, #%1 */ + ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0010 0010 subw %0, %e1%!1 */ + ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac; + +/** 0110 0001 0010 1001 subw %0, %e1%1 */ + ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac; + +/** 0010 0100 subw %0, #%1 */ + ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac; + +/** 0010 0rw1 subw %0, %1 */ + ID(sub); W(); DR(AX); SRW(rw); Fzac; + +/** 0010 0110 subw %0, %1 */ + ID(sub); W(); DR(AX); SM(None, SADDR); Fzac; + +/** 0010 0000 subw %0, #%1 */ + ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac; + +/*----------------------------------------------------------------------*/ + +/** 0110 0001 1010 1010 xch %0, %e1%!1 */ + ID(xch); DR(A); SM(None, IMMU(2)); + +/** 0110 0001 1010 1110 xch %0, %e1%1 */ + ID(xch); DR(A); SM(DE, 0); + +/** 0110 0001 1010 1111 xch %0, %e1%1 */ + ID(xch); DR(A); SM(DE, IMMU(1)); + +/** 0110 0001 1010 1100 xch %0, %e1%1 */ + ID(xch); DR(A); SM(HL, 0); + +/** 0110 0001 1011 1001 xch %0, %e1%1 */ + ID(xch); DR(A); SM2(HL, B, 0); + +/** 0110 0001 1010 1101 xch %0, %e1%1 */ + ID(xch); DR(A); SM(HL, IMMU(1)); + +/** 0110 0001 1010 1001 xch %0, %e1%1 */ + ID(xch); DR(A); SM2(HL, C, 0); + +/** 0110 0001 1000 1reg xch %0, %1 */ + /* Note: DECW uses reg == X, so this must follow DECW */ + ID(xch); DR(A); SRB(reg); + +/** 0110 0001 1010 1000 xch %0, %1 */ + ID(xch); DR(A); SM(None, SADDR); + +/** 0110 0001 1010 1011 xch %0, %1 */ + ID(xch); DR(A); SM(None, SFR); + +/** 0000 1000 xch a, x */ + ID(xch); DR(A); SR(X); + +/*----------------------------------------------------------------------*/ + +/** 0011 0ra1 xchw %0, %1 */ + ID(xch); W(); DR(AX); SRW(ra); + +/*----------------------------------------------------------------------*/ + +/** 0111 1111 xor %0, %e1%!1 */ + ID(xor); DR(A); SM(None, IMMU(2)); Fz; + +/** 0111 1101 xor %0, %e1%1 */ + ID(xor); DR(A); SM(HL, 0); Fz; + +/** 0110 0001 1111 0000 xor %0, %e1%1 */ + ID(xor); DR(A); SM2(HL, B, 0); Fz; + +/** 0111 1110 xor %0, %e1%1 */ + ID(xor); DR(A); SM(HL, IMMU(1)); Fz; + +/** 0110 0001 1111 0010 xor %0, %e1%1 */ + ID(xor); DR(A); SM2(HL, C, 0); Fz; + +/** 0111 1100 xor %0, #%1 */ + ID(xor); DR(A); SC(IMMU(1)); Fz; + +/** 0110 0001 0111 1rba xor %0, %1 */ + ID(xor); DR(A); SRB(rba); Fz; + +/** 0110 0001 0111 0reg xor %0, %1 */ + ID(xor); DRB(reg); SR(A); Fz; + +/** 0111 1011 xor %0, %1 */ + ID(xor); DR(A); SM(None, SADDR); Fz; + +/** 0111 1010 xor %0, #%1 */ + ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz; + +/*----------------------------------------------------------------------*/ + +/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */ + ID(xor); DCY(); SM(HL, 0); SB(bit); + +/** 0111 0001 1bit 1111 xor1 cy, %1 */ + ID(xor); DCY(); SR(A); SB(bit); + +/** 0111 0001 0bit 1111 xor1 cy, %s1 */ + ID(xor); DCY(); SM(None, SFR); SB(bit); + +/** 0111 0001 0bit 0111 xor1 cy, %s1 */ + ID(xor); DCY(); SM(None, SADDR); SB(bit); + +/*----------------------------------------------------------------------*/ + +/** */ + + return rl78->n_bytes; +} diff --git a/opcodes/rl78-dis.c b/opcodes/rl78-dis.c new file mode 100644 index 00000000000..826235a7feb --- /dev/null +++ b/opcodes/rl78-dis.c @@ -0,0 +1,327 @@ +/* Disassembler code for Renesas RL78. + Copyright 2011 Free Software Foundation, Inc. + Contributed by Red Hat. + Written by DJ Delorie. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include <stdio.h> + +#include "bfd.h" +#include "dis-asm.h" +#include "opcode/rl78.h" + +#define DEBUG_SEMANTICS 0 + +typedef struct +{ + bfd_vma pc; + disassemble_info * dis; +} RL78_Data; + +static int +rl78_get_byte (void * vdata) +{ + bfd_byte buf[1]; + RL78_Data *rl78_data = (RL78_Data *) vdata; + + rl78_data->dis->read_memory_func (rl78_data->pc, + buf, + 1, + rl78_data->dis); + + rl78_data->pc ++; + return buf[0]; +} + +static char const * +register_names[] = +{ + "", + "x", "a", "c", "b", "e", "d", "l", "h", + "ax", "bc", "de", "hl", + "sp", "psw", "cs", "es", "pmc", "mem" +}; + +static char const * +condition_names[] = +{ + "t", "f", "c", "nc", "h", "nh", "z", "nz" +}; + +static int +indirect_type (int t) +{ + switch (t) + { + case RL78_Operand_Indirect: + case RL78_Operand_BitIndirect: + case RL78_Operand_PostInc: + case RL78_Operand_PreDec: + return 1; + default: + return 0; + } +} + +int +print_insn_rl78 (bfd_vma addr, disassemble_info * dis) +{ + int rv; + RL78_Data rl78_data; + RL78_Opcode_Decoded opcode; + const char * s; +#if DEBUG_SEMANTICS + static char buf[200]; +#endif + + rl78_data.pc = addr; + rl78_data.dis = dis; + + rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data); + + dis->bytes_per_line = 10; + +#define PR (dis->fprintf_func) +#define PS (dis->stream) +#define PC(c) PR (PS, "%c", c) + + s = opcode.syntax; + +#if DEBUG_SEMANTICS + + switch (opcode.id) + { + case RLO_unknown: s = "uknown"; break; + case RLO_add: s = "add: %e0%0 += %e1%1"; break; + case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break; + case RLO_and: s = "and: %e0%0 &= %e1%1"; break; + case RLO_branch: s = "branch: pc = %e0%0"; break; + case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break; + case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break; + case RLO_call: s = "call: pc = %e1%0"; break; + case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break; + case RLO_mov: s = "mov: %e0%0 = %e1%1"; break; + case RLO_or: s = "or: %e0%0 |= %e1%1"; break; + case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break; + case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break; + case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break; + case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break; + case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break; + case RLO_sel: s = "sel: rb = %1"; break; + case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break; + case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break; + case RLO_skip: s = "skip: if %c1"; break; + case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break; + case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break; + case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break; + case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break; + } + + sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax); + s = buf; + +#endif + + for (; *s; s++) + { + if (*s != '%') + { + PC (*s); + } + else + { + RL78_Opcode_Operand * oper; + int do_hex = 0; + int do_addr = 0; + int do_es = 0; + int do_sfr = 0; + int do_cond = 0; + int do_bang = 0; + + s ++; + + if (*s == 'x') + { + do_hex = 1; + s++; + } + if (*s == '!') + { + do_bang = 1; + s++; + } + if (*s == 'e') + { + do_es = 1; + s++; + } + if (*s == 'a') + { + do_addr = 1; + s++; + } + if (*s == 's') + { + do_sfr = 1; + s++; + } + if (*s == 'c') + { + do_cond = 1; + s++; + } + + switch (*s) + { + case '%': + PC ('%'); + break; + +#if DEBUG_SEMANTICS + + case 'W': + if (opcode.size == RL78_Word) + PR (PS, " \033[33mW\033[0m"); + break; + + case 'f': + if (opcode.flags) + { + char *comma = ""; + PR (PS, " \033[35m"); + + if (opcode.flags & RL78_PSW_Z) + { PR (PS, "Z"); comma = ","; } + if (opcode.flags & RL78_PSW_AC) + { PR (PS, "%sAC", comma); comma = ","; } + if (opcode.flags & RL78_PSW_CY) + { PR (PS, "%sCY", comma); comma = ","; } + PR (PS, "\033[0m"); + } + break; + +#endif + + case '0': + case '1': + oper = opcode.op + *s - '0'; + if (do_bang) + PC ('!'); + + if (do_es) + { + if (oper->use_es && indirect_type (oper->type)) + PR (PS, "es:"); + } + + else if (do_cond) + { + PR (PS, "%s", condition_names[oper->condition]); + } + + else + switch (oper->type) + { + case RL78_Operand_Immediate: + if (do_addr) + dis->print_address_func (oper->addend, dis); + else if (do_hex + || oper->addend > 999 + || oper->addend < -999) + PR (PS, "%#x", oper->addend); + else + PR (PS, "%d", oper->addend); + break; + + case RL78_Operand_Register: + PR (PS, "%s", register_names[oper->reg]); + break; + + case RL78_Operand_Bit: + PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number); + break; + + case RL78_Operand_Indirect: + case RL78_Operand_BitIndirect: + switch (oper->reg) + { + case RL78_Reg_None: + if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte) + PR (PS, "psw"); + else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word) + PR (PS, "sp"); + else if (oper->addend >= 0xffe20) + PR (PS, "%#x", oper->addend); + else + dis->print_address_func (oper->addend, dis); + break; + + case RL78_Reg_B: + case RL78_Reg_C: + case RL78_Reg_BC: + PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]); + break; + + default: + PR (PS, "[%s", register_names[oper->reg]); + if (oper->reg2 != RL78_Reg_None) + PR (PS, "+%s", register_names[oper->reg2]); + if (oper->addend) + PR (PS, "+%d", oper->addend); + PC (']'); + break; + + } + if (oper->type == RL78_Operand_BitIndirect) + PR (PS, ".%d", oper->bit_number); + break; + +#if DEBUG_SEMANTICS + /* Shouldn't happen - push and pop don't print + [SP] directly. But we *do* use them for + semantic debugging. */ + case RL78_Operand_PostInc: + PR (PS, "[%s++]", register_names[oper->reg]); + break; + case RL78_Operand_PreDec: + PR (PS, "[--%s]", register_names[oper->reg]); + break; +#endif + + default: + /* If we ever print this, that means the + programmer tried to print an operand with a + type we don't expect. Print the line and + operand number from rl78-decode.opc for + them. */ + PR (PS, "???%d.%d", opcode.lineno, *s - '0'); + break; + } + } + } + } + +#if DEBUG_SEMANTICS + + PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno); + +#endif + + return rv; +} |