1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
|
;; Predicates of machine description for CR16.
;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
;; Contributed by KPIT Cummins Infosystems Limited.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Predicates
;; Predicates for sbit/cbit instructions
;; bit operand used for the generation of bit insn generation
(define_predicate "bit_operand"
(match_code "mem")
{
return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
})
;; Unsigned 4-bits constant int or double value.
(define_predicate "u4bits_operand"
(match_code "const_int,const_double")
{
if (GET_CODE (op) == CONST_DOUBLE)
return cr16_const_double_ok (op);
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
})
;; Operand is a constant integer where
;; only one bit is set to 1.
(define_predicate "one_bit_operand"
(match_code "const_int")
{
unsigned int val;
val = INTVAL (op);
if (mode == QImode)
val &= 0xff;
else if (mode == HImode)
val &= 0xffff;
else
gcc_unreachable();
if (val != 0)
return (val & (val - 1)) == 0; /* true if only one bit is set. */
else
return 0;
})
;; Operand is a constant integer where
;; only one bit is set to 0.
(define_predicate "rev_one_bit_operand"
(match_code "const_int")
{
unsigned int val;
val = ~INTVAL (op); /* Invert and use. */
if (mode == QImode)
val &= 0xff;
else if (mode == HImode)
val &= 0xffff;
else
gcc_unreachable();
if (val != 0)
return (val & (val - 1)) == 0; /* true if only one bit is set. */
else
return 0;
})
;; Predicates for shift instructions
;; Immediate operand predicate for count in shift operations.
;; Immediate shall be 3-bits in case operand to be operated on
;; is a qi mode operand.
(define_predicate "shift_qi_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 3)) ? 1 : 0;
})
;; Immediate shall be 4-bits in case operand to be operated on
;; is a hi mode operand.
(define_predicate "shift_hi_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
})
;; Immediate shall be 3-bits in case operand to be operated on
;; is a si mode operand.
(define_predicate "shift_si_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 5)) ? 1 : 0;
})
;; Predicates for jump/call instructions
;; Jump immediate cannot be more than 24-bits
(define_predicate "jump_imm_operand"
(match_code "const_int")
{
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
})
;; Call immediate cannot be more than 24-bits
(define_predicate "call_imm_operand"
(match_operand 0 "immediate_operand")
{
if (GET_CODE (op) != CONST_INT) return 1;
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
})
;; Operand is register or 4-bit immediate operand
(define_predicate "reg_or_u4bits_operand"
(ior (match_operand 0 "u4bits_operand")
(match_operand 0 "register_operand")))
;; Operand is a register or symbol reference
(define_predicate "reg_or_sym_operand"
(ior (match_code "symbol_ref")
(match_operand 0 "register_operand")))
;; Operand is a non stack pointer register
(define_predicate "nosp_reg_operand"
(and (match_operand 0 "register_operand")
(match_test "REGNO (op) != SP_REGNUM")))
(define_predicate "hard_reg_operand"
(and (match_operand 0 "register_operand")
(match_test "REGNO (op) <= 15")))
;; Operand is a memory reference and
;; not a push operand.
(define_predicate "store_operand"
(and (match_operand 0 "memory_operand")
(not (match_operand 0 "push_operand"))))
;; Helper predicate
(define_predicate "reg_or_int_operand"
(ior (match_code "const_int")
(match_operand 0 "register_operand")))
;;
;;
;; Atithmetic/logical predicates
;; QI Helper
(define_predicate "arith_qi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 15) && ((INTVAL (op) != 9)
|| (INTVAL (op) != 11))) ? 1 : 0 ;
})
;;QI Reg, subreg(reg) or const_int.
(define_predicate "reg_qi_int_operand"
(ior (match_operand 0 "arith_qi_operand")
(match_operand 0 "register_operand")))
;; HI Helper
(define_predicate "arith_hi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), -32768, 32768) ) ? 1 : 0 ;
})
;;HI Reg, subreg(reg) or const_int.
(define_predicate "reg_hi_int_operand"
(ior (match_operand 0 "arith_hi_operand")
(match_operand 0 "register_operand")))
;;SI Reg, subreg(reg) or const_int.
(define_predicate "reg_si_int_operand"
(ior (match_operand 0 "const_int_operand")
(match_operand 0 "register_operand")))
;;
;; Shift predicates
;; QI Helper
(define_predicate "shift_qi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 7) ) ? 1 : 0;
})
;;QI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_qi_int_operand"
(ior (match_operand 0 "shift_qi_operand")
(match_operand 0 "register_operand")))
;; HI Helper
(define_predicate "shift_hi_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 15) ) ? 1 : 0 ;
})
;;HI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_hi_int_operand"
(ior (match_operand 0 "shift_hi_operand")
(match_operand 0 "register_operand")))
;; SI Helper
(define_predicate "shift_si_operand"
(match_code "const_int")
{
return (IN_RAN(INTVAL (op), 0, 31) ) ? 1 : 0;
})
;;SI Reg, subreg(reg) or const_int.
(define_predicate "shift_reg_si_int_operand"
(ior (match_operand 0 "shift_si_operand")
(match_operand 0 "register_operand")))
|
