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* [RTEMS] Add GCC Runtime Library Exceptionsh2017-07-251-12/+17
* MIPS16/GCC: Emit bounds checking as RTL in `casesi'macro2017-06-141-35/+23
* * config/mips/frame-header-opt.c: Include profile-count.h.hubicka2017-06-051-0/+1
* Fix previous commitrsandifo2017-05-042-9/+7
* Remove bogus top-level ChangeLog commit (sorry!)rsandifo2017-05-042-7/+9
* MIPS: Prevent buffer overrun in uninitialised variable fixmpf2017-04-201-1/+1
* PR target/74563law2017-04-191-1/+0
* * regcprop.c (maybe_mode_change): Avoid creating copies of thelaw2017-04-181-8/+2
* * config/mips.mips.md (zero_extendsidi2): Do not allow SP to appearlaw2017-04-141-2/+8
* Update MIPS -mvirt option descriptionmpf2017-04-101-1/+1
* * config/mips/mips.c (mips_multi_add): Zero initialize the newlylaw2017-04-041-1/+5
* Fix numerous typos in commentsredi2017-04-031-1/+1
* Fix extraction from odd-numbered MSA registersmpf2017-03-311-1/+14
* Fix ICE when expanding MSA constant vectors with replicated valuesmpf2017-03-301-2/+3
* Apply temporary fix for PR rtl-optimization/79150.tomtab2017-03-211-0/+3
* gcc/prachigodbole2017-03-061-6/+6
* gcc/prachigodbole2017-03-061-6/+6
* gcc/prachigodbole2017-03-062-2/+2
* Fix MIPS o32 calling convention for MSA and FP vector typesmpf2017-02-221-3/+7
* MIPS: Fix mode mismatch error between Loongson builtin arguments and insntomtab2017-02-071-0/+18
* gcc/clm2017-01-202-3/+13
* MIPS: Make loongson3a use fused madd.dmpf2017-01-191-2/+4
* MIPS: PR target/78176 add -mlxc1-sxc1.mpf2017-01-192-2/+10
* MIPS: Fix generation of Loongson-specific division and modulo instructions.tomtab2017-01-181-5/+11
* Update copyright years.jakub2017-01-0189-90/+90
* [MIPS][MSA] Fix builtins with literal integer arguments.rts2016-12-061-22/+61
* PR ada/67205ebotcazou2016-11-251-0/+4
* MIPS16/GCC: Emit explicit JRC from `casesi_internal_mips16_<mode>' insnmacro2016-11-161-2/+8
* MIPS16/GCC: Improve `casesi_internal_mips16_<mode>'s instruction count estimatemacro2016-11-161-1/+1
* MIPS16/GCC: Correct `casesi_internal_mips16_<mode>'s RTL patternmacro2016-11-161-1/+1
* MIPS16/GCC: Fix DImode `casesi_internal_mips16_<mode>' assembly instructionsmacro2016-11-161-6/+6
* microMIPS/GCC: Fix PIC call relaxationmacro2016-11-161-6/+3
* MIPS/GCC: Mark text contents as code or datamacro2016-11-164-5/+104
* Fix instances of gen_rtx_REG (VOIDmode, ...)rsandifo2016-11-151-1/+1
* MIPS/GCC: Mark trailing labels with `.insn'macro2016-11-152-0/+62
* split up some variables to use rtx_insn * moretbsaunde2016-11-021-28/+33
* * config/mips/mips.c (mips16_constant_cost): Add missinglaw2016-10-261-2/+4
* 2016-10-13 Catherine Moore <clm@codesourcery.com>clm2016-10-141-17/+19
* [MIPS] Disable -mbranch-likely for -Os when targetting generic archrts2016-10-113-35/+52
* MIPS/GCC/doc: Fix `d' constraint descriptionmacro2016-09-271-2/+2
* 2016-09-26 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-09-261-0/+1
* [mips] Add support for mips*r6-*-muslnsz2016-08-251-3/+6
* MIPS: Use create_tmp_var_raw in mips_atomic_assign_expand_fenvmpf2016-08-091-3/+3
* merge adjust_cost and adjust_cost_2 target hookstbsaunde2016-07-281-6/+2
* 2016-07-11 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2016-07-111-1/+1
* MIPS: Stay within 79 columns in `mips_output_jump'macro2016-06-091-2/+3
* [MIPS] P5600 scheduler fixrts2016-06-071-2/+2
* Enable LSA/DLSA for MSA.rts2016-05-161-2/+4
* Correct the latency of loads in M5100rts2016-05-161-1/+1
* Fix multi-line brackets in mips-cpus.defmpf2016-05-161-2/+2
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