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path: root/gcc/config/aarch64/predicates.md
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* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-281-0/+5
* [PATCH][AArch64] Fix missing optimization for CMP+ANDjgreenhalgh2017-07-271-0/+4
* 2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>collison2017-06-291-0/+4
* [AArch64] Use SUBS for parallel subtraction and comparison with immediatektkachov2017-06-051-0/+4
* [AArch64] Accept more addressing modes for PRFMktkachov2017-05-041-0/+3
* Update copyright years.jakub2017-01-011-1/+1
* 2016-11-22 Michael Collison <michael.collison@arm.com>collison2016-11-231-0/+4
* [AArch64] Fix gcc.dg/torture/float32-builtin.c with RTL checkingktkachov2016-11-171-3/+3
* PR c/7652mpolacek2016-08-121-0/+2
* [AArch64] Fix SIMD predicateevandro2016-04-011-1/+1
* [AArch64] PR target/69161: Don't use special predicate for CCmode comparisons...ktkachov2016-02-171-2/+11
* PR target/69305rth2016-01-281-0/+19
* [Patch 1/4] Simplify the representation of CCMP patterns by usingjiwang2016-01-191-17/+0
* PR target/69176rth2016-01-181-0/+4
* Update copyright years.jakub2016-01-041-1/+1
* [AArch64][v2] Improve comparison with complex immediates followed by branch/csetktkachov2015-11-241-0/+5
* [AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INTktkachov2015-11-091-1/+1
* [AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisationktkachov2015-10-201-0/+7
* [AArch64] Delete aarch64_symbol_context which is not usedjiwang2015-09-241-2/+2
* [AArch64] Handle literal pools for functions > 1 MiB in size.ramana2015-09-141-0/+4
* Update copyright years.jakub2015-01-051-1/+1
* 2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>zqchen2014-11-171-0/+5
* 2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>zqchen2014-11-171-0/+17
* 2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>zqchen2014-11-171-0/+8
* [AArch64] Tighten predicates on SIMD shift intrinsicsjgreenhalgh2014-09-251-0/+53
* [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instructionalalaw012014-09-051-0/+6
* [AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.ktkachov2014-09-021-0/+12
* [AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insnsjiwang2014-08-011-0/+4
* [AArch64_be] Fix vec_select hi/lo mask confusions.jgreenhalgh2014-07-311-49/+2
* [AARCH64] Support tail indirect function call.mshawcroft2014-05-231-0/+4
* [PATCH][AArch64] Vector shift by 64 fixjgreenhalgh2014-01-231-0/+4
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
* gcc/vp2013-08-271-0/+5
* [AArch64] Remove aarch64_symbolic_constant_p.mshawcroft2013-06-281-3/+2
* [AArch64] Implement support for --mcmodel=tinymshawcroft2013-05-291-1/+1
* [AArch64] Refactor aarch64_mov_operand predicate.mshawcroft2013-05-231-10/+1
* [AArch64] Improve description of <F>CM instructions in RTLjgreenhalgh2013-05-011-0/+5
* Update copyright years in gcc/rsandifo2013-01-101-1/+1
* [AARCH64] Add support for vector and scalar floating-point immediate loads.jgreenhalgh2013-01-071-1/+1
* Use CSINC instead of CSEL to return 1 (AArch64)ibolton2012-11-121-2/+3
* AArch64 [3/10]mshawcroft2012-10-231-0/+297