delta/gcc.git - gcc.gnu.org: git/gcc.git

	Commit message (Expand)	Author	Age	Files	Lines
*	Merged trunk revision 251080 into the hsa branchhsa	jamborm	2017-08-14	1	-5/+0
*	2017-07-28 Tamar Christina <tamar.christina@arm.com>	tnfchris	2017-07-28	1	-0/+5
*	[PATCH][AArch64] Fix missing optimization for CMP+AND	jgreenhalgh	2017-07-27	1	-0/+4
*	2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>	collison	2017-06-29	1	-0/+4
*	[AArch64] Use SUBS for parallel subtraction and comparison with immediate	ktkachov	2017-06-05	1	-0/+4
*	[AArch64] Accept more addressing modes for PRFM	ktkachov	2017-05-04	1	-0/+3
*	Update copyright years.	jakub	2017-01-01	1	-1/+1
*	2016-11-22 Michael Collison <michael.collison@arm.com>	collison	2016-11-23	1	-0/+4
*	[AArch64] Fix gcc.dg/torture/float32-builtin.c with RTL checking	ktkachov	2016-11-17	1	-3/+3
*	PR c/7652	mpolacek	2016-08-12	1	-0/+2
*	[AArch64] Fix SIMD predicate	evandro	2016-04-01	1	-1/+1
*	[AArch64] PR target/69161: Don't use special predicate for CCmode comparisons...	ktkachov	2016-02-17	1	-2/+11
*	PR target/69305	rth	2016-01-28	1	-0/+19
*	[Patch 1/4] Simplify the representation of CCMP patterns by using	jiwang	2016-01-19	1	-17/+0
*	PR target/69176	rth	2016-01-18	1	-0/+4
*	Update copyright years.	jakub	2016-01-04	1	-1/+1
*	[AArch64][v2] Improve comparison with complex immediates followed by branch/cset	ktkachov	2015-11-24	1	-0/+5
*	[AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT	ktkachov	2015-11-09	1	-1/+1
*	[AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisation	ktkachov	2015-10-20	1	-0/+7
*	[AArch64] Delete aarch64_symbol_context which is not used	jiwang	2015-09-24	1	-2/+2
*	[AArch64] Handle literal pools for functions > 1 MiB in size.	ramana	2015-09-14	1	-0/+4
*	Update copyright years.	jakub	2015-01-05	1	-1/+1
*	2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>	zqchen	2014-11-17	1	-0/+5
*	2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>	zqchen	2014-11-17	1	-0/+17
*	2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>	zqchen	2014-11-17	1	-0/+8
*	[AArch64] Tighten predicates on SIMD shift intrinsics	jgreenhalgh	2014-09-25	1	-0/+53
*	[PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction	alalaw01	2014-09-05	1	-0/+6
*	[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.	ktkachov	2014-09-02	1	-0/+12
*	[AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insns	jiwang	2014-08-01	1	-0/+4
*	[AArch64_be] Fix vec_select hi/lo mask confusions.	jgreenhalgh	2014-07-31	1	-49/+2
*	[AARCH64] Support tail indirect function call.	mshawcroft	2014-05-23	1	-0/+4
*	[PATCH][AArch64] Vector shift by 64 fix	jgreenhalgh	2014-01-23	1	-0/+4
*	Update copyright years in gcc/	rsandifo	2014-01-02	1	-1/+1
*	gcc/	vp	2013-08-27	1	-0/+5
*	[AArch64] Remove aarch64_symbolic_constant_p.	mshawcroft	2013-06-28	1	-3/+2
*	[AArch64] Implement support for --mcmodel=tiny	mshawcroft	2013-05-29	1	-1/+1
*	[AArch64] Refactor aarch64_mov_operand predicate.	mshawcroft	2013-05-23	1	-10/+1
*	[AArch64] Improve description of <F>CM instructions in RTL	jgreenhalgh	2013-05-01	1	-0/+5
*	Update copyright years in gcc/	rsandifo	2013-01-10	1	-1/+1
*	[AARCH64] Add support for vector and scalar floating-point immediate loads.	jgreenhalgh	2013-01-07	1	-1/+1
*	Use CSINC instead of CSEL to return 1 (AArch64)	ibolton	2012-11-12	1	-2/+3
*	AArch64 [3/10]	mshawcroft	2012-10-23	1	-0/+297