diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
19 files changed, 446 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h index a95d06aa2ed..07e56fff857 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h @@ -34,6 +34,13 @@ struct hfa_fx2_t float b; }; +struct hfa_fx3_t +{ + float a; + float b; + float c; +}; + struct hfa_dx2_t { double a; diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c new file mode 100644 index 00000000000..ae1e3ec45cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c @@ -0,0 +1,59 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named HFA/HVA argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-13.c" + +struct float_float_t +{ + float a; + float b; +} float_float; + +union float_int_t +{ + float b8; + int b5; +} float_int; + +#define HAS_DATA_INIT_FUNC +void +init_data () +{ + float_float.a = 1.2f; + float_float.b = 2.2f; + + float_int.b8 = 4983.80f; +} + +#include "abitest.h" +#else + ARG (float, 1.0f, S0, 0) + ARG (float, 2.0f, S1, 1) + ARG (float, 3.0f, S2, 2) + ARG (float, 4.0f, S3, 3) + ARG (float, 5.0f, S4, 4) + ARG (float, 6.0f, S5, 5) + ARG (float, 7.0f, S6, 6) + ARG (struct float_float_t, float_float, STACK, 7) + ARG (int, 9, W0, 8) + ARG (int, 10, W1, 9) + ARG (int, 11, W2, 10) + ARG (int, 12, W3, 11) + ARG (int, 13, W4, 12) + ARG (int, 14, W5, 13) + ARG (int, 15, W6, LAST_NAMED_ARG_ID) + DOTS + /* Note on the reason of using 'X7' instead of 'W7' here: + Using 'X7' makes sure the test works in the big-endian mode. + According to PCS rules B.4 and C.10, the size of float_int is rounded + to 8 bytes and prepared in the register X7 as if loaded via LDR from + the memory, with the content of the other 4 bytes unspecified. The + test framework will only compare the 4 relavent bytes. */ + ANON (union float_int_t, float_int, X7, 15) + LAST_ANON (long long, 12683143434LL, STACK + 8, 16) +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c new file mode 100644 index 00000000000..91080d5afa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c @@ -0,0 +1,35 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named HFA/HVA argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-14.c" +#include "type-def.h" + +struct hfa_fx2_t hfa_fx2 = {1.2f, 2.2f}; +struct hfa_fx3_t hfa_fx3 = {3.2f, 4.2f, 5.2f}; +vf4_t float32x4 = {6.2f, 7.2f, 8.2f, 9.2f}; +vf4_t float32x4_2 = {10.2f, 11.2f, 12.2f, 13.2f}; + +#include "abitest.h" +#else + ARG (float, 1.0f, S0, 0) + ARG (float, 2.0f, S1, 1) + ARG (float, 3.0f, S2, 2) + ARG (float, 4.0f, S3, 3) + ARG (float, 5.0f, S4, 4) + ARG (float, 6.0f, S5, 5) + ARG (float, 7.0f, S6, 6) + ARG (struct hfa_fx3_t, hfa_fx3, STACK, 7) + /* Previous argument size has been rounded up to the nearest multiple of + 8 bytes. */ + ARG (struct hfa_fx2_t, hfa_fx2, STACK + 16, 8) + /* NSAA is rounded up to the nearest natural alignment of float32x4. */ + ARG (vf4_t, float32x4, STACK + 32, 9) + ARG (vf4_t, float32x4_2, STACK + 48, LAST_NAMED_ARG_ID) + DOTS + LAST_ANON (double, 123456789.987, STACK + 64, 11) +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c new file mode 100644 index 00000000000..d8fdb322b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c @@ -0,0 +1,39 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named __128int argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-15.c" +#include "type-def.h" + +union int128_t qword; + +#define HAS_DATA_INIT_FUNC +void +init_data () +{ + /* Init signed quad-word integer. */ + qword.l64 = 0xfdb9753102468aceLL; + qword.h64 = 0xeca8642013579bdfLL; +} + +#include "abitest.h" +#else + ARG (int, 1, W0, 0) + ARG (int, 2, W1, 1) + ARG (int, 3, W2, 2) + ARG (int, 4, W3, 3) + ARG (int, 5, W4, 4) + ARG (int, 6, W5, 5) + ARG (int, 7, W6, 6) + ARG (__int128, qword.i, STACK, LAST_NAMED_ARG_ID) + DOTS +#ifndef __AAPCS64_BIG_ENDIAN__ + LAST_ANON (int, 8, STACK + 16, 8) +#else + LAST_ANON (int, 8, STACK + 20, 8) +#endif +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/acle/acle.exp b/gcc/testsuite/gcc.target/aarch64/acle/acle.exp new file mode 100644 index 00000000000..e820f6c8c4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/acle.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c new file mode 100644 index 00000000000..bf9a3d82a73 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c @@ -0,0 +1,15 @@ +/* Test the crc32b ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32b (uint32_t arg0, uint8_t arg1) +{ + return __crc32b (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32b\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c new file mode 100644 index 00000000000..a5a39b139dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c @@ -0,0 +1,15 @@ +/* Test the crc32cb ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32cb (uint32_t arg0, uint8_t arg1) +{ + return __crc32cb (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32cb\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c new file mode 100644 index 00000000000..b50097a20d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c @@ -0,0 +1,15 @@ +/* Test the crc32cd ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32cd (uint32_t arg0, uint64_t arg1) +{ + return __crc32cd (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32cx\tw..?, w..?, x..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c new file mode 100644 index 00000000000..523faa25be9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c @@ -0,0 +1,15 @@ +/* Test the crc32ch ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32ch (uint32_t arg0, uint16_t arg1) +{ + return __crc32ch (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32ch\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c new file mode 100644 index 00000000000..531e6043209 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c @@ -0,0 +1,15 @@ +/* Test the crc32cw ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32cw (uint32_t arg0, uint32_t arg1) +{ + return __crc32cw (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32cw\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c new file mode 100644 index 00000000000..14fa627ba91 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c @@ -0,0 +1,15 @@ +/* Test the crc32d ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32d (uint32_t arg0, uint64_t arg1) +{ + return __crc32d (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32x\tw..?, w..?, x..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c new file mode 100644 index 00000000000..90819e615cb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c @@ -0,0 +1,15 @@ +/* Test the crc32h ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32h (uint32_t arg0, uint16_t arg1) +{ + return __crc32h (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32h\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c new file mode 100644 index 00000000000..006f17635b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c @@ -0,0 +1,15 @@ +/* Test the crc32w ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */ + +#include "arm_acle.h" + +uint32_t +test_crc32w (uint32_t arg0, uint32_t arg1) +{ + return __crc32w (arg0, arg1); +} + +/* { dg-final { scan-assembler "crc32w\tw..?, w..?, w..?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/avr/torture/pr61443.c b/gcc/testsuite/gcc.target/avr/torture/pr61443.c new file mode 100644 index 00000000000..12c6bca6663 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr61443.c @@ -0,0 +1,134 @@ +/* { dg-do run } */ +/* { dg-options "-std=gnu99" } */ + +#include <stdlib.h> +#include <stdarg.h> + +#define NC __attribute__((noinline,noclone)) + +void NC vfun (char n, ...) +{ + va_list ap; + + va_start (ap, n); + + switch (n) + { + default: + abort(); + case 1: + if (11 != va_arg (ap, int)) + abort(); + break; + case 2: + if (2222 != va_arg (ap, int)) + abort(); + break; + case 3: + if (333333 != va_arg (ap, __int24)) + abort(); + break; + case 4: + if (44444444 != va_arg (ap, long)) + abort(); + break; + case 8: + if (8888888888888888 != va_arg (ap, long long)) + abort(); + break; + } + + va_end (ap); +} + + +void NC boo_qi (const __flash char *p) +{ + vfun (1, *p); +} + +void NC boox_qi (const __memx char *p) +{ + vfun (1, *p); +} + +void NC boo_hi (const __flash int *p) +{ + vfun (2, *p); +} + +void NC boox_hi (const __memx int *p) +{ + vfun (2, *p); +} + +void NC boo_psi (const __flash __int24 *p) +{ + vfun (3, *p); +} + +void NC boox_psi (const __memx __int24 *p) +{ + vfun (3, *p); +} + +void NC boo_si (const __flash long *p) +{ + vfun (4, *p); +} + +void NC boox_si (const __memx long *p) +{ + vfun (4, *p); +} + +void NC boo_di (const __flash long long *p) +{ + vfun (8, *p); +} + +void NC boox_di (const __memx long long *p) +{ + vfun (8, *p); +} + +const __flash char f_qi = 11; +const __flash int f_hi = 2222; +const __flash __int24 f_psi = 333333; +const __flash long f_si = 44444444; +const __flash long long f_di = 8888888888888888; + +const __memx char x_qi = 11; +const __memx int x_hi = 2222; +const __memx __int24 x_psi = 333333; +const __memx long x_si = 44444444; +const __memx long long x_di = 8888888888888888; + +char r_qi = 11; +int r_hi = 2222; +__int24 r_psi = 333333; +long r_si = 44444444; +long long r_di = 8888888888888888; + +int main (void) +{ + boo_qi (&f_qi); + boo_hi (&f_hi); + boo_psi (&f_psi); + boo_si (&f_si); + boo_di (&f_di); + + boox_qi (&x_qi); + boox_hi (&x_hi); + boox_psi (&x_psi); + boox_si (&x_si); + boox_di (&x_di); + + boox_qi (&r_qi); + boox_hi (&r_hi); + boox_psi (&r_psi); + boox_si (&r_si); + boox_di (&r_di); + + exit (0); +} diff --git a/gcc/testsuite/gcc.target/i386/fuse-caller-save.c b/gcc/testsuite/gcc.target/i386/fuse-caller-save.c index 8618409c78a..4ec49952b27 100644 --- a/gcc/testsuite/gcc.target/i386/fuse-caller-save.c +++ b/gcc/testsuite/gcc.target/i386/fuse-caller-save.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fuse-caller-save" } */ +/* { dg-options "-O2 -fuse-caller-save -fomit-frame-pointer" } */ /* { dg-additional-options "-mregparm=1" { target ia32 } } */ /* Testing -fuse-caller-save optimization option. */ diff --git a/gcc/testsuite/gcc.target/i386/pr61446.c b/gcc/testsuite/gcc.target/i386/pr61446.c new file mode 100644 index 00000000000..fc32f63ee69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr61446.c @@ -0,0 +1,14 @@ +/* PR rtl-optimization/61446 */ + +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -march=corei7 -mfpmath=387" } */ + +unsigned long long +foo (float a) +{ + const double dfa = a; + const unsigned int hi = dfa / 0x1p32f; + const unsigned int lo = dfa - (double) hi * 0x1p32f; + + return ((unsigned long long) hi << (4 * (8))) | lo; +} diff --git a/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c b/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c index fbf605f31ec..fc8c8806f78 100644 --- a/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c +++ b/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c @@ -33,4 +33,3 @@ int main () /* { dg-final { scan-assembler "vpmulld" } } */ /* { dg-final { scan-assembler "vphadddq" } } */ -/* { dg-final { scan-assembler "vpmacsdql" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pack02.c b/gcc/testsuite/gcc.target/powerpc/pack02.c index 584d6c29205..f85d3ff00b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pack02.c +++ b/gcc/testsuite/gcc.target/powerpc/pack02.c @@ -2,6 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_fprs } */ +/* { dg-require-effective-target longdouble128 } */ /* { dg-options "-O2 -mhard-float" } */ #include <stddef.h> diff --git a/gcc/testsuite/gcc.target/powerpc/tfmode_off.c b/gcc/testsuite/gcc.target/powerpc/tfmode_off.c index e6578ef31a8..ea703f0ee0a 100644 --- a/gcc/testsuite/gcc.target/powerpc/tfmode_off.c +++ b/gcc/testsuite/gcc.target/powerpc/tfmode_off.c @@ -1,6 +1,7 @@ /* { dg-do assemble } */ /* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ /* { dg-skip-if "no TFmode" { powerpc-*-eabi* } { "*" } { "" } } */ +/* { dg-require-effective-target longdouble128 } */ /* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */ typedef float TFmode __attribute__ ((mode (TF))); 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