11 files changed, 135 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc/testsuite/gcc.target/i386/pr37434-1.c
new file mode 100644
index 00000000000..b556bf0848e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr37434-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc/testsuite/gcc.target/i386/pr37434-2.c
new file mode 100644
index 00000000000..00ff9fd2e6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr37434-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrw" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc/testsuite/gcc.target/i386/pr37434-3.c
new file mode 100644
index 00000000000..916c99fe02f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr37434-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc/testsuite/gcc.target/i386/pr37434-4.c
new file mode 100644
index 00000000000..15f8292b029
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr37434-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrb" } } */
diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
new file mode 100644
index 00000000000..816c19e20f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
new file mode 100644
index 00000000000..b5103ac1d75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
new file mode 100644
index 00000000000..b8612962dea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
new file mode 100644
index 00000000000..21f1692cdf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
new file mode 100644
index 00000000000..1065a843a58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc/testsuite/gcc.target/m68k/xgot-1.c b/gcc/testsuite/gcc.target/m68k/xgot-1.c
index f7dd6c939ac..e7bc5fb6012 100644
--- a/gcc/testsuite/gcc.target/m68k/xgot-1.c
+++ b/gcc/testsuite/gcc.target/m68k/xgot-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-fpic -mxgot" } */
+/* { dg-options "-fpic -mxgot -mcpu=5206" } */
 /* { dg-final { scan-assembler "foo@GOT,\%\[ad\]\[0-7\]" } } */
 
 extern int foo;
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-27.c b/gcc/testsuite/gcc.target/powerpc/altivec-27.c
new file mode 100644
index 00000000000..7db0ea01f2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-27.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define f0() void x0 (vector float x) { }
+f0 ()
+
+#define f1(type) void x1##type (vector type x) { }
+f1 (float)
+
+#define f2(v, type) void x2##type (v type x) { }
+f2 (vector, float)
+
+#define f3(type) void x3##type (vector bool type x) { }
+f3 (int)
+
+#define f4(v, type) void x4##type (v bool type x) { }
+f4 (vector, int)
+
+#define f5(b, type) void x5##type (vector b type x) { }
+f5 (bool, int)
+
+#define f6(v, b, type) void x6##type (v b type x) { }
+f6 (vector, bool, int)
+
+#define f7(v, b, type) void x7##type (v type b x) { }
+f7 (vector, bool, int)
+
+int vector = 6;
+
+#define v1(v) int x8 (int v) { return v; }
+v1(vector)