diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
290 files changed, 1550 insertions, 192 deletions
diff --git a/gcc/testsuite/gcc.target/arm/interrupt-1.c b/gcc/testsuite/gcc.target/arm/interrupt-1.c new file mode 100644 index 00000000000..18379de33d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/interrupt-1.c @@ -0,0 +1,23 @@ +/* Verify that prologue and epilogue are correct for functions with + __attribute__ ((interrupt)). */ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +/* This test is not valid when -mthumb. We just cheat. */ +#ifndef __thumb__ +extern void bar (int); +extern void foo (void) __attribute__ ((interrupt("IRQ"))); + +void foo () +{ + bar (0); +} +#else +void foo () +{ + asm ("stmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, lr}"); + asm ("ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, pc}^"); +} +#endif +/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, lr}" } } */ +/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, pc}\\^" } } */ diff --git a/gcc/testsuite/gcc.target/arm/interrupt-2.c b/gcc/testsuite/gcc.target/arm/interrupt-2.c new file mode 100644 index 00000000000..b979bf17e8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/interrupt-2.c @@ -0,0 +1,26 @@ +/* Verify that prologue and epilogue are correct for functions with + __attribute__ ((interrupt)). */ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* This test is not valid when -mthum. We just cheat. */ +#ifndef __thumb__ +extern void bar (int); +extern void test (void) __attribute__((__interrupt__)); + +int foo; +void test() +{ + funcptrs(foo); + foo = 0; +} +#else +void test () +{ + asm ("stmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, lr}"); + asm ("ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, pc}^"); +} +#endif + +/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, lr}" } } */ +/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, pc}\\^" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vadds64.c b/gcc/testsuite/gcc.target/arm/neon-vadds64.c new file mode 100644 index 00000000000..284a1d8adc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vadds64.c @@ -0,0 +1,21 @@ +/* Test the `vadd_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL; + + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddu64.c b/gcc/testsuite/gcc.target/arm/neon-vaddu64.c new file mode 100644 index 00000000000..05bda8b046e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddu64.c @@ -0,0 +1,21 @@ +/* Test the `vadd_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL; + + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vands64.c b/gcc/testsuite/gcc.target/arm/neon-vands64.c new file mode 100644 index 00000000000..8b6975db6e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vands64.c @@ -0,0 +1,21 @@ +/* Test the `vand_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vandu64.c b/gcc/testsuite/gcc.target/arm/neon-vandu64.c new file mode 100644 index 00000000000..a8ec3a28b4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vandu64.c @@ -0,0 +1,21 @@ +/* Test the `vand_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vbics64.c b/gcc/testsuite/gcc.target/arm/neon-vbics64.c new file mode 100644 index 00000000000..ec3438baef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vbics64.c @@ -0,0 +1,21 @@ +/* Test the `vbic_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); + + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vbicu64.c b/gcc/testsuite/gcc.target/arm/neon-vbicu64.c new file mode 100644 index 00000000000..a0c1b85b405 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vbicu64.c @@ -0,0 +1,21 @@ +/* Test the `vbic_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); + + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c new file mode 100644 index 00000000000..da24eaca69f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_lanes64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c new file mode 100644 index 00000000000..cc19ea51252 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_laneu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c new file mode 100644 index 00000000000..79b4d4eb60d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c new file mode 100644 index 00000000000..ef6f47fd3aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c b/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c new file mode 100644 index 00000000000..589ea22930d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x1_t = vdup_n_s64 (arg0_int64_t); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c b/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c new file mode 100644 index 00000000000..8bed5a0c7d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-veors64.c b/gcc/testsuite/gcc.target/arm/neon-veors64.c new file mode 100644 index 00000000000..59d5baa3579 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-veors64.c @@ -0,0 +1,21 @@ +/* Test the `veor_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-veoru64.c b/gcc/testsuite/gcc.target/arm/neon-veoru64.c new file mode 100644 index 00000000000..b7ff77af0d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-veoru64.c @@ -0,0 +1,21 @@ +/* Test the `veor_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c b/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c new file mode 100644 index 00000000000..5891e66193a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vget_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64_t out_int64_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; + + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); + if (out_int64_t != (int64_t)arg0_int64x1_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c b/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c new file mode 100644 index 00000000000..b0ce070d3b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vget_lane_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64_t out_uint64_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; + + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); + if (out_uint64_t != (uint64_t)arg0_uint64x1_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vmla-1.c b/gcc/testsuite/gcc.target/arm/neon-vmla-1.c index 336a53bb481..9d239ed47d0 100644 --- a/gcc/testsuite/gcc.target/arm/neon-vmla-1.c +++ b/gcc/testsuite/gcc.target/arm/neon-vmla-1.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target arm_neon_hw } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ /* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vmla\\.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vmls-1.c b/gcc/testsuite/gcc.target/arm/neon-vmls-1.c index 5e5e0c757ac..2beaebe17cf 100644 --- a/gcc/testsuite/gcc.target/arm/neon-vmls-1.c +++ b/gcc/testsuite/gcc.target/arm/neon-vmls-1.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target arm_neon_hw } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ /* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vmls\\.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c new file mode 100644 index 00000000000..5a8abdce038 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c @@ -0,0 +1,22 @@ +/* Test the `vmovq_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c new file mode 100644 index 00000000000..8012fc1753d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c @@ -0,0 +1,23 @@ +/* Test the `vmovq_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c b/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c new file mode 100644 index 00000000000..c125f4a247d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x1_t = vmov_n_s64 (arg0_int64_t); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c b/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c new file mode 100644 index 00000000000..71ecaed134e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vorns64.c b/gcc/testsuite/gcc.target/arm/neon-vorns64.c new file mode 100644 index 00000000000..364dbd1904c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vorns64.c @@ -0,0 +1,21 @@ +/* Test the `vorn_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); + + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vornu64.c b/gcc/testsuite/gcc.target/arm/neon-vornu64.c new file mode 100644 index 00000000000..b352868469f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vornu64.c @@ -0,0 +1,21 @@ +/* Test the `vorn_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); + + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vorrs64.c b/gcc/testsuite/gcc.target/arm/neon-vorrs64.c new file mode 100644 index 00000000000..90ced9e9c86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vorrs64.c @@ -0,0 +1,21 @@ +/* Test the `vorr_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vorru64.c b/gcc/testsuite/gcc.target/arm/neon-vorru64.c new file mode 100644 index 00000000000..5b44afb07ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vorru64.c @@ -0,0 +1,21 @@ +/* Test the `vorr_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c b/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c new file mode 100644 index 00000000000..10113932711 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c @@ -0,0 +1,21 @@ +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = 0xf00f00f00LL; + int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; + + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c b/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c new file mode 100644 index 00000000000..cafc2607687 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c @@ -0,0 +1,21 @@ +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = 0xf00f00f00LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; + + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vsubs64.c b/gcc/testsuite/gcc.target/arm/neon-vsubs64.c new file mode 100644 index 00000000000..23947004127 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vsubs64.c @@ -0,0 +1,21 @@ +/* Test the `vsub_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL; + int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL; + + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon-vsubu64.c b/gcc/testsuite/gcc.target/arm/neon-vsubu64.c new file mode 100644 index 00000000000..0162e206ef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vsubu64.c @@ -0,0 +1,21 @@ +/* Test the `vsub_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL; + + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc/testsuite/gcc.target/arm/neon/vadds64.c index d3923775237..fb17e0ea3b6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vadds64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vadds64.c @@ -17,5 +17,4 @@ void test_vadds64 (void) out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c index 1114725b44d..18fc500b9f2 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vaddu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c @@ -17,5 +17,4 @@ void test_vaddu64 (void) out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc/testsuite/gcc.target/arm/neon/vands64.c index b34abab6651..13e18fb0cbf 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vands64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vands64.c @@ -17,5 +17,4 @@ void test_vands64 (void) out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc/testsuite/gcc.target/arm/neon/vandu64.c index 4660272cc20..d9ddf847af3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vandu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vandu64.c @@ -17,5 +17,4 @@ void test_vandu64 (void) out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc/testsuite/gcc.target/arm/neon/vbics64.c index 41db18e2744..379db45f4db 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbics64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbics64.c @@ -17,5 +17,4 @@ void test_vbics64 (void) out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c index 9f0a047fc92..c276d65ebe3 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c @@ -17,5 +17,4 @@ void test_vbicu64 (void) out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c index 987a4d3f63f..ab749a7bbad 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c @@ -16,6 +16,4 @@ void test_vdupQ_ns64 (void) out_int64x2_t = vdupq_n_s64 (arg0_int64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c index c2e5d481a3d..0ddb72decc8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c @@ -16,6 +16,4 @@ void test_vdupQ_nu64 (void) out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c index 720cc0452d2..033f1b4744c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c @@ -16,5 +16,4 @@ void test_vdup_ns64 (void) out_int64x1_t = vdup_n_s64 (arg0_int64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c index 4033e4757dc..6888125c638 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c @@ -16,5 +16,4 @@ void test_vdup_nu64 (void) out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc/testsuite/gcc.target/arm/neon/veors64.c index 0543b22e2e1..2781be1b2cc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/veors64.c +++ b/gcc/testsuite/gcc.target/arm/neon/veors64.c @@ -17,5 +17,4 @@ void test_veors64 (void) out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc/testsuite/gcc.target/arm/neon/veoru64.c index 1098285dc6f..19d081489ed 100644 --- a/gcc/testsuite/gcc.target/arm/neon/veoru64.c +++ b/gcc/testsuite/gcc.target/arm/neon/veoru64.c @@ -17,5 +17,4 @@ void test_veoru64 (void) out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c index 136242900a7..5dc99424fa5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c @@ -16,5 +16,4 @@ void test_vget_lanes64 (void) out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); } -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c index 4b44a1e8c37..496a057fc73 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c @@ -16,5 +16,4 @@ void test_vget_laneu64 (void) out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); } -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c index 89fe2c150fd..35936cbd43a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c @@ -16,6 +16,4 @@ void test_vmovQ_ns64 (void) out_int64x2_t = vmovq_n_s64 (arg0_int64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c index d7d3e365ecd..e373a121865 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c @@ -16,6 +16,4 @@ void test_vmovQ_nu64 (void) out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c index 6d2d61678b9..7b011282832 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c @@ -16,5 +16,4 @@ void test_vmov_ns64 (void) out_int64x1_t = vmov_n_s64 (arg0_int64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c index 9434377d2ff..b9613e06ff1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c @@ -16,5 +16,4 @@ void test_vmov_nu64 (void) out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc/testsuite/gcc.target/arm/neon/vorns64.c index eb3253743a2..d7b8e60d208 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorns64.c @@ -17,5 +17,4 @@ void test_vorns64 (void) out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc/testsuite/gcc.target/arm/neon/vornu64.c index a92a7d7124c..6fb3a9502a6 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornu64.c @@ -17,5 +17,4 @@ void test_vornu64 (void) out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c index eaa107cb649..a1c7e5ee222 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorrs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c @@ -17,5 +17,4 @@ void test_vorrs64 (void) out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc/testsuite/gcc.target/arm/neon/vorru64.c index 2dc4898a779..1991b02152f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorru64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorru64.c @@ -17,5 +17,4 @@ void test_vorru64 (void) out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c index 2c4bede7796..5c5454f9807 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c @@ -17,5 +17,4 @@ void test_vset_lanes64 (void) out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c index 22ba53c20a9..3bff5d232c7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c @@ -17,5 +17,4 @@ void test_vset_laneu64 (void) out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); } -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c index 656039989a0..57bcd33d42c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vsubs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c @@ -17,5 +17,4 @@ void test_vsubs64 (void) out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); } -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c index 5e4a2a871e9..3a8ae462e81 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vsubu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c @@ -17,5 +17,4 @@ void test_vsubu64 (void) out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr39839.c b/gcc/testsuite/gcc.target/arm/pr39839.c new file mode 100644 index 00000000000..31e865af2f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr39839.c @@ -0,0 +1,24 @@ +/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ + +struct S +{ + int count; + char *addr; +}; + +void func(const char*, const char*, int, const char*); + +/* This function should not need to spill to the stack. */ +void test(struct S *p) +{ + int off = p->count; + while (p->count >= 0) + { + const char *s = "xyz"; + if (*p->addr) s = "pqr"; + func("abcde", p->addr + off, off, s); + p->count--; + } +} diff --git a/gcc/testsuite/gcc.target/arm/pr40657-1.c b/gcc/testsuite/gcc.target/arm/pr40657-1.c new file mode 100644 index 00000000000..a6ac6c78a1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr40657-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -march=armv5te -mthumb" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler "pop.*r1.*pc" } } */ +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ + +extern void bar(int*); +int foo() +{ + int x; + bar(&x); + return x; +} diff --git a/gcc/testsuite/gcc.target/arm/pr40657-2.c b/gcc/testsuite/gcc.target/arm/pr40657-2.c new file mode 100644 index 00000000000..31d48376730 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr40657-2.c @@ -0,0 +1,20 @@ +/* { dg-options "-Os -march=armv4t -mthumb" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ + +/* Here, we test that if there's a pop of r[4567] in the epilogue, + add sp,sp,#12 is removed and replaced by three additional pops + of lower-numbered regs. */ + +extern void bar(int*); + +int t1, t2, t3, t4, t5; +int foo() +{ + int i,j,k,x = 0; + for (i = 0; i < t1; i++) + for (j = 0; j < t2; j++) + bar(&x); + return x; +} diff --git a/gcc/testsuite/gcc.target/arm/pr42172-1.c b/gcc/testsuite/gcc.target/arm/pr42172-1.c new file mode 100644 index 00000000000..207f6001fb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr42172-1.c @@ -0,0 +1,19 @@ +/* { dg-options "-O2" } */ + +struct A { + unsigned int f1 : 3; + unsigned int f2 : 3; + unsigned int f3 : 1; + unsigned int f4 : 1; + +}; + +void init_A (struct A *this) +{ + this->f1 = 0; + this->f2 = 1; + this->f3 = 0; + this->f4 = 0; +} + +/* { dg-final { scan-assembler-times "ldr" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr42235.c b/gcc/testsuite/gcc.target/arm/pr42235.c new file mode 100644 index 00000000000..478abcc0765 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr42235.c @@ -0,0 +1,11 @@ +/* { dg-options "-mthumb -O2 -march=armv5te" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */ + +#include <string.h> + +int foo (char *x) +{ + memset (x, 0, 6); +} diff --git a/gcc/testsuite/gcc.target/arm/pr42505.c b/gcc/testsuite/gcc.target/arm/pr42505.c new file mode 100644 index 00000000000..60902c35d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr42505.c @@ -0,0 +1,23 @@ +/* { dg-options "-mthumb -Os -march=armv5te" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ + +struct A { + int f1; + int f2; +}; + +int func(int c); + +/* This function should not need to spill anything to the stack. */ +int test(struct A* src, struct A* dst, int count) +{ + while (count--) { + if (!func(src->f2)) { + return 0; + } + *dst++ = *src++; + } + + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/pr42835.c b/gcc/testsuite/gcc.target/arm/pr42835.c new file mode 100644 index 00000000000..71c51ebe31c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr42835.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int foo(int *p, int i) +{ + return( (i < 0 && *p == 1) + || (i > 0 && *p == 2) ); +} + +/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */ +/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr43698.c b/gcc/testsuite/gcc.target/arm/pr43698.c new file mode 100644 index 00000000000..407cf7eac2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr43698.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-Os -march=armv7-a" } */ +#include <stdint.h> +#include <stdlib.h> + + +char do_reverse_endian = 0; + +# define bswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) + +#define EGET(X) \ + (__extension__ ({ \ + uint64_t __res; \ + if (!do_reverse_endian) { __res = (X); \ + } else if (sizeof(X) == 4) { __res = bswap_32((X)); \ + } \ + __res; \ + })) + +void __attribute__((noinline)) X(char **phdr, char **data, int *phoff) +{ + *phdr = *data + EGET(*phoff); +} + +int main() +{ + char *phdr; + char *data = (char *)0x40164000; + int phoff = 0x34; + X(&phdr, &data, &phoff); + if (phdr != (char *)0x40164034) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/arm/pr44788.c b/gcc/testsuite/gcc.target/arm/pr44788.c new file mode 100644 index 00000000000..eb4bc11af9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr44788.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ + +void joint_decode(float* mlt_buffer1, int t) { + int i; + float decode_buffer[1060]; + foo(decode_buffer); + for (i=0; i<10 ; i++) { + mlt_buffer1[i] = i * decode_buffer[t]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/20020523.c b/gcc/testsuite/gcc.target/i386/20020523.c index 7c3490f780b..0684d5feb42 100644 --- a/gcc/testsuite/gcc.target/i386/20020523.c +++ b/gcc/testsuite/gcc.target/i386/20020523.c @@ -4,6 +4,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse -mfpmath=sse -ffast-math" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/aes-avx-check.h b/gcc/testsuite/gcc.target/i386/aes-avx-check.h index e91e88173cf..36a038ea341 100644 --- a/gcc/testsuite/gcc.target/i386/aes-avx-check.h +++ b/gcc/testsuite/gcc.target/i386/aes-avx-check.h @@ -22,7 +22,8 @@ main () return 0; /* Run AES + AVX test only if host has AES + AVX support. */ - if ((ecx & (bit_AVX | bit_AES)) == (bit_AVX | bit_AES)) + if ((ecx & (bit_AVX | bit_OSXSAVE | bit_AES)) + == (bit_AVX | bit_OSXSAVE | bit_AES)) { do_test (); #ifdef DEBUG diff --git a/gcc/testsuite/gcc.target/i386/all_one_m128i.c b/gcc/testsuite/gcc.target/i386/all_one_m128i.c index 24d870fa37f..fa973e420ab 100644 --- a/gcc/testsuite/gcc.target/i386/all_one_m128i.c +++ b/gcc/testsuite/gcc.target/i386/all_one_m128i.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef long long __m128i __attribute__ ((__vector_size__ (16))); typedef int __v4si __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc/testsuite/gcc.target/i386/avx-check.h index 7736fc9f40b..b15584ad274 100644 --- a/gcc/testsuite/gcc.target/i386/avx-check.h +++ b/gcc/testsuite/gcc.target/i386/avx-check.h @@ -20,7 +20,7 @@ main () return 0; /* Run AVX test only if host has AVX support. */ - if (ecx & bit_AVX) + if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE)) { do_test (); #ifdef DEBUG diff --git a/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c b/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c index 65cda0b2cbf..7898606b0bc 100644 --- a/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c b/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c index b2603aad4c5..e0ee934dad5 100644 --- a/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #define CHECK_H "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c index be69d47e822..f9646a10d12 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c index 7000bb07feb..1c169f5ac5c 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c index 753f2ce64d0..888f9eb2878 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c index c1292a25555..b82abb6dcea 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c index 97ca6e6c50f..9b6d580289c 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c b/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c index 627333a860c..0dd1b09228e 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ /* { dg-options "-O2 -mavx -std=c99" } */ #include "avx-check.h" diff --git a/gcc/testsuite/gcc.target/i386/brokensqrt.c b/gcc/testsuite/gcc.target/i386/brokensqrt.c index 19a59d822e6..836d3b37d4c 100644 --- a/gcc/testsuite/gcc.target/i386/brokensqrt.c +++ b/gcc/testsuite/gcc.target/i386/brokensqrt.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" extern float sqrtf (float); diff --git a/gcc/testsuite/gcc.target/i386/f16c-check.h b/gcc/testsuite/gcc.target/i386/f16c-check.h new file mode 100644 index 00000000000..af7f32c5f4f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/f16c-check.h @@ -0,0 +1,30 @@ +#include <stdlib.h> +#include <stdio.h> +#include "cpuid.h" +#include "m256-check.h" + +static void f16c_test (void); + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run F16C test only if host has F16C support. */ + if (ecx & bit_F16C) + { + f16c_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c b/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c index bdfae5b3b7b..1a55a3d60eb 100644 --- a/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c +++ b/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-mpreferred-stack-boundary=4 -msse" } */ /* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/fpcvt-1.c b/gcc/testsuite/gcc.target/i386/fpcvt-1.c index 5f09aedc53e..1c3b9b83453 100644 --- a/gcc/testsuite/gcc.target/i386/fpcvt-1.c +++ b/gcc/testsuite/gcc.target/i386/fpcvt-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "cvtss2sd" } } */ float a,b; main() diff --git a/gcc/testsuite/gcc.target/i386/fpcvt-2.c b/gcc/testsuite/gcc.target/i386/fpcvt-2.c index 317aa13b887..066d84365ed 100644 --- a/gcc/testsuite/gcc.target/i386/fpcvt-2.c +++ b/gcc/testsuite/gcc.target/i386/fpcvt-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "cvtss2sd" } } */ float a,b; main() diff --git a/gcc/testsuite/gcc.target/i386/fpcvt-3.c b/gcc/testsuite/gcc.target/i386/fpcvt-3.c index 70377c3d627..569d21a5aa7 100644 --- a/gcc/testsuite/gcc.target/i386/fpcvt-3.c +++ b/gcc/testsuite/gcc.target/i386/fpcvt-3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "cvtss2sd" } } */ extern double fabs (double); float a,b; diff --git a/gcc/testsuite/gcc.target/i386/funcspec-9.c b/gcc/testsuite/gcc.target/i386/funcspec-9.c index 1c05f134ab5..78714e12417 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-9.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-9.c @@ -1,7 +1,6 @@ /* Test whether using target specific options, we can generate FMA4 code. */ /* { dg-do compile } */ /* { dg-options "-O2 -march=k8 -mfpmath=sse -msse2" } */ -/* { dg-require-effective-target sse2 } */ extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 8b31231b61c..65abf58db81 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -27,8 +27,7 @@ load_lib gcc-dg.exp # Return 1 if attribute ms_hook_prologue is supported. proc check_effective_target_ms_hook_prologue { } { - if { [check_effective_target_ilp32] - && [check_no_compiler_messages ms_hook_prologue object { + if { [check_no_compiler_messages ms_hook_prologue object { void __attribute__ ((__ms_hook_prologue__)) foo (); } ""] } { return 1 diff --git a/gcc/testsuite/gcc.target/i386/incoming-1.c b/gcc/testsuite/gcc.target/i386/incoming-1.c index 9129ad00e17..86e98a79b47 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-1.c +++ b/gcc/testsuite/gcc.target/i386/incoming-1.c @@ -1,7 +1,6 @@ /* PR middle-end/37009 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-12.c b/gcc/testsuite/gcc.target/i386/incoming-12.c index b6bfa418d90..d7ef1038bb5 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-12.c +++ b/gcc/testsuite/gcc.target/i386/incoming-12.c @@ -1,7 +1,6 @@ /* PR target/40838 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ -/* { dg-require-effective-target sse2 } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-2.c b/gcc/testsuite/gcc.target/i386/incoming-2.c index 18451669612..2947d3347cd 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-2.c +++ b/gcc/testsuite/gcc.target/i386/incoming-2.c @@ -1,7 +1,6 @@ /* PR middle-end/37009 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-3.c b/gcc/testsuite/gcc.target/i386/incoming-3.c index bb9653a4067..1edbfda0b39 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-3.c +++ b/gcc/testsuite/gcc.target/i386/incoming-3.c @@ -1,7 +1,6 @@ /* PR middle-end/37009 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-4.c b/gcc/testsuite/gcc.target/i386/incoming-4.c index e1d1b751e7b..80c169c2469 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-4.c +++ b/gcc/testsuite/gcc.target/i386/incoming-4.c @@ -1,7 +1,6 @@ /* PR middle-end/37009 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ -/* { dg-require-effective-target sse2 } */ #include <stdarg.h> #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/incoming-6.c b/gcc/testsuite/gcc.target/i386/incoming-6.c index f6b64b7abd2..5cc4ab3f766 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-6.c +++ b/gcc/testsuite/gcc.target/i386/incoming-6.c @@ -1,7 +1,6 @@ /* PR target/40838 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ -/* { dg-require-effective-target sse2 } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-7.c b/gcc/testsuite/gcc.target/i386/incoming-7.c index fb5380490d6..cdd60379683 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-7.c +++ b/gcc/testsuite/gcc.target/i386/incoming-7.c @@ -1,7 +1,6 @@ /* PR target/40838 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ -/* { dg-require-effective-target sse2 } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/incoming-8.c b/gcc/testsuite/gcc.target/i386/incoming-8.c index 0f27af72078..2dd8800fd6c 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-8.c +++ b/gcc/testsuite/gcc.target/i386/incoming-8.c @@ -1,7 +1,6 @@ /* PR target/40838 */ /* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */ /* { dg-options "-w -mstackrealign -O3 -msse2 -mpreferred-stack-boundary=4" } */ -/* { dg-require-effective-target sse2 } */ float foo (float f) diff --git a/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp b/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp index a0e7b8d1eaa..2b1d63de17a 100644 --- a/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp +++ b/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp @@ -28,19 +28,23 @@ if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { set MATH_TORTURE_OPTIONS [list \ { -O0 } \ { -O0 -mfpmath=387 } \ + { -O0 -mfpmath=387 -ffast-math } \ + { -O2 } \ + { -O2 -mfpmath=387 } \ + { -O2 -mfpmath=387 -ffast-math } \ +] + +if { [check_effective_target_sse] } { + lappend MATH_TORTURE_OPTIONS \ { -O0 -msse -mno-sse2 -mfpmath=sse } \ { -O0 -msse -mno-sse2 -mfpmath=sse,387 } \ - { -O0 -mfpmath=387 -ffast-math } \ { -O0 -msse -mno-sse2 -mfpmath=sse -ffast-math } \ { -O0 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \ - { -O2 } \ - { -O2 -mfpmath=387 } \ { -O2 -msse -mno-sse2 -mfpmath=sse } \ { -O2 -msse -mno-sse2 -mfpmath=sse,387 } \ - { -O2 -mfpmath=387 -ffast-math } \ { -O2 -msse -mno-sse2 -mfpmath=sse -ffast-math } \ { -O2 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \ -] +} if { [check_effective_target_sse2] } { lappend MATH_TORTURE_OPTIONS \ diff --git a/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c b/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c index f945492dfde..e11bcc049cb 100644 --- a/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c +++ b/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c @@ -11,7 +11,7 @@ int __attribute__ ((__ms_hook_prologue__)) foo () /* The NOP mov must not be optimized away by optimizations. The push %ebp, mov %esp, %ebp must not be removed by -fomit-frame-pointer */ - +#ifndef __x86_64__ /* movl.s %edi, %edi */ if(*ptr++ != 0x8b) return 1; if(*ptr++ != 0xff) return 1; @@ -20,6 +20,15 @@ int __attribute__ ((__ms_hook_prologue__)) foo () /* movl.s %esp, %ebp */ if(*ptr++ != 0x8b) return 1; if(*ptr++ != 0xec) return 1; +#else + /* leaq 0(%rsp), %rsp */ + if (*ptr++ != 0x48) return 1; + if (*ptr++ != 0x8d) return 1; + if (*ptr++ != 0xa4) return 1; + if (*ptr++ != 0x24) return 1; + if (ptr[0] != 0 || ptr[1] != 0 || ptr[2] != 0 || ptr[3] != 0) + return 1; +#endif return 0; } diff --git a/gcc/testsuite/gcc.target/i386/opt-1.c b/gcc/testsuite/gcc.target/i386/opt-1.c index 74d3e8d1046..28e2ef38c34 100644 --- a/gcc/testsuite/gcc.target/i386/opt-1.c +++ b/gcc/testsuite/gcc.target/i386/opt-1.c @@ -2,7 +2,6 @@ whether we vectorize a simple loop. */ /* { dg-do compile } */ /* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "prefetcht0" } } */ /* { dg-final { scan-assembler "addps" } } */ /* { dg-final { scan-assembler "subss" } } */ diff --git a/gcc/testsuite/gcc.target/i386/opt-2.c b/gcc/testsuite/gcc.target/i386/opt-2.c index d247d71fc23..d2791e071c3 100644 --- a/gcc/testsuite/gcc.target/i386/opt-2.c +++ b/gcc/testsuite/gcc.target/i386/opt-2.c @@ -2,7 +2,6 @@ whether we vectorize a simple loop. */ /* { dg-do compile } */ /* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "prefetcht0" } } */ /* { dg-final { scan-assembler "addps" } } */ /* { dg-final { scan-assembler "subss" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ordcmp-1.c b/gcc/testsuite/gcc.target/i386/ordcmp-1.c index 9be97e52b91..a136182aca9 100644 --- a/gcc/testsuite/gcc.target/i386/ordcmp-1.c +++ b/gcc/testsuite/gcc.target/i386/ordcmp-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "cmpordss" } } */ /* { dg-final { scan-assembler "cmpordps" } } */ /* { dg-final { scan-assembler "cmpordsd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h b/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h index 550e49904d9..750e25c5069 100644 --- a/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h +++ b/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h @@ -22,7 +22,8 @@ main () return 0; /* Run PCLMUL + AVX test only if host has PCLMUL + AVX support. */ - if ((ecx & (bit_AVX | bit_PCLMUL)) == (bit_AVX | bit_PCLMUL)) + if ((ecx & (bit_AVX | bit_OSXSAVE | bit_PCLMUL)) + == (bit_AVX | bit_OSXSAVE | bit_PCLMUL)) { do_test (); #ifdef DEBUG diff --git a/gcc/testsuite/gcc.target/i386/pr13685.c b/gcc/testsuite/gcc.target/i386/pr13685.c index 159112d1666..a50681bea26 100644 --- a/gcc/testsuite/gcc.target/i386/pr13685.c +++ b/gcc/testsuite/gcc.target/i386/pr13685.c @@ -1,6 +1,7 @@ /* PR target/13685 */ /* { dg-do run } */ /* { dg-options "-Os -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/pr17692.c b/gcc/testsuite/gcc.target/i386/pr17692.c index f8aed82750f..476d8e3de3f 100644 --- a/gcc/testsuite/gcc.target/i386/pr17692.c +++ b/gcc/testsuite/gcc.target/i386/pr17692.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O -mfpmath=sse -msse2" } */ -/* { dg-require-effective-target sse2 } */ + /* The fact that t1 and t2 are uninitialized is critical. With them uninitialized, the register allocator is free to put them in the same hard register, which results in diff --git a/gcc/testsuite/gcc.target/i386/pr18614-1.c b/gcc/testsuite/gcc.target/i386/pr18614-1.c index 6e16616cae6..1a499753760 100644 --- a/gcc/testsuite/gcc.target/i386/pr18614-1.c +++ b/gcc/testsuite/gcc.target/i386/pr18614-1.c @@ -1,7 +1,6 @@ /* PR rtl-optimization/18614 */ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef double v2df __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc/testsuite/gcc.target/i386/pr22152.c index 4dce76cc947..d12597703ea 100644 --- a/gcc/testsuite/gcc.target/i386/pr22152.c +++ b/gcc/testsuite/gcc.target/i386/pr22152.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <mmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr23570.c b/gcc/testsuite/gcc.target/i386/pr23570.c index f220a8cb80d..1542663fa22 100644 --- a/gcc/testsuite/gcc.target/i386/pr23570.c +++ b/gcc/testsuite/gcc.target/i386/pr23570.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef float __v4sf __attribute__ ((__vector_size__ (16))); typedef float __m128 __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr23575.c b/gcc/testsuite/gcc.target/i386/pr23575.c index 1b0ec7f88c3..522226ef7a2 100644 --- a/gcc/testsuite/gcc.target/i386/pr23575.c +++ b/gcc/testsuite/gcc.target/i386/pr23575.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ -/* { dg-require-effective-target sse2 } */ /* We used to ICE because of a bogous pattern. */ diff --git a/gcc/testsuite/gcc.target/i386/pr24306.c b/gcc/testsuite/gcc.target/i386/pr24306.c index c578475bbea..1319918c350 100644 --- a/gcc/testsuite/gcc.target/i386/pr24306.c +++ b/gcc/testsuite/gcc.target/i386/pr24306.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/pr26449-1.c b/gcc/testsuite/gcc.target/i386/pr26449-1.c index e83375d6d0f..b4ef7804887 100644 --- a/gcc/testsuite/gcc.target/i386/pr26449-1.c +++ b/gcc/testsuite/gcc.target/i386/pr26449-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -mtune=k8" } */ -/* { dg-require-effective-target sse2 } */ typedef short __v8hi __attribute__ ((__vector_size__ (16))); typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr26600.c b/gcc/testsuite/gcc.target/i386/pr26600.c index 61941de70e4..bbe0663da7e 100644 --- a/gcc/testsuite/gcc.target/i386/pr26600.c +++ b/gcc/testsuite/gcc.target/i386/pr26600.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O -ftree-vectorize -msse2" } */ -/* { dg-require-effective-target sse2 } */ void foo(int *p, int N) { diff --git a/gcc/testsuite/gcc.target/i386/pr27790.c b/gcc/testsuite/gcc.target/i386/pr27790.c index 4c5cdb6dc74..e8986c4158a 100644 --- a/gcc/testsuite/gcc.target/i386/pr27790.c +++ b/gcc/testsuite/gcc.target/i386/pr27790.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O -ftree-vectorize -msse2" } */ -/* { dg-require-effective-target sse2 } */ void binarize (int npixels, unsigned char *b) { diff --git a/gcc/testsuite/gcc.target/i386/pr28839.c b/gcc/testsuite/gcc.target/i386/pr28839.c index ccb715d7478..6a215164c58 100644 --- a/gcc/testsuite/gcc.target/i386/pr28839.c +++ b/gcc/testsuite/gcc.target/i386/pr28839.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -ftree-vectorize -funswitch-loops" } */ -/* { dg-require-effective-target sse2 } */ static int ready[10]; void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr30970.c b/gcc/testsuite/gcc.target/i386/pr30970.c index 25f773915f8..96d64e5a962 100644 --- a/gcc/testsuite/gcc.target/i386/pr30970.c +++ b/gcc/testsuite/gcc.target/i386/pr30970.c @@ -1,6 +1,5 @@ /* { dg-do compile } /* { dg-options "-msse2 -O2 -ftree-vectorize" } */ -/* { dg-require-effective-target sse2 } */ #define N 256 int b[N]; diff --git a/gcc/testsuite/gcc.target/i386/pr32065-2.c b/gcc/testsuite/gcc.target/i386/pr32065-2.c index e1a88592d3c..5f055b59c3a 100644 --- a/gcc/testsuite/gcc.target/i386/pr32065-2.c +++ b/gcc/testsuite/gcc.target/i386/pr32065-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target dfp } */ +/* { dg-require-effective-target sse } */ /* { dg-options "-Os -msse -std=gnu99" } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/pr32280.c b/gcc/testsuite/gcc.target/i386/pr32280.c index 49865ea4ba6..d48a635a4b8 100644 --- a/gcc/testsuite/gcc.target/i386/pr32280.c +++ b/gcc/testsuite/gcc.target/i386/pr32280.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr32661.c b/gcc/testsuite/gcc.target/i386/pr32661.c index 2eb1544e336..247ae131923 100644 --- a/gcc/testsuite/gcc.target/i386/pr32661.c +++ b/gcc/testsuite/gcc.target/i386/pr32661.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef int __v4si __attribute__ ((__vector_size__ (16))); typedef float __v4sf __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr32708-1.c b/gcc/testsuite/gcc.target/i386/pr32708-1.c index 5200f3f6547..c5308937bb0 100644 --- a/gcc/testsuite/gcc.target/i386/pr32708-1.c +++ b/gcc/testsuite/gcc.target/i386/pr32708-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef long long __v2di __attribute__ ((__vector_size__ (16))); typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr32961.c b/gcc/testsuite/gcc.target/i386/pr32961.c index 8b513623111..a2326289af9 100644 --- a/gcc/testsuite/gcc.target/i386/pr32961.c +++ b/gcc/testsuite/gcc.target/i386/pr32961.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O0 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <xmmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr33329.c b/gcc/testsuite/gcc.target/i386/pr33329.c index e8036082cf1..bb589ee2780 100644 --- a/gcc/testsuite/gcc.target/i386/pr33329.c +++ b/gcc/testsuite/gcc.target/i386/pr33329.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -msse2" } */ -/* { dg-require-effective-target sse2 } */ extern void g (int *); diff --git a/gcc/testsuite/gcc.target/i386/pr35714.c b/gcc/testsuite/gcc.target/i386/pr35714.c index d5d2755ed07..13ca47c23a3 100644 --- a/gcc/testsuite/gcc.target/i386/pr35714.c +++ b/gcc/testsuite/gcc.target/i386/pr35714.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr35767-5.c b/gcc/testsuite/gcc.target/i386/pr35767-5.c index 9f533033b71..4372d2e5746 100644 --- a/gcc/testsuite/gcc.target/i386/pr35767-5.c +++ b/gcc/testsuite/gcc.target/i386/pr35767-5.c @@ -1,7 +1,6 @@ /* Test that we generate aligned load when memory is aligned. */ /* { dg-do compile } */ /* { dg-options "-O -msse2 -mtune=generic" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "movups" } } */ /* { dg-final { scan-assembler "movaps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr36222-1.c b/gcc/testsuite/gcc.target/i386/pr36222-1.c index 647e1039619..2d4c5b9b76c 100644 --- a/gcc/testsuite/gcc.target/i386/pr36222-1.c +++ b/gcc/testsuite/gcc.target/i386/pr36222-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); typedef int __v4si __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr36992-1.c b/gcc/testsuite/gcc.target/i386/pr36992-1.c index 017616bcc5b..7cd24cccf3e 100644 --- a/gcc/testsuite/gcc.target/i386/pr36992-1.c +++ b/gcc/testsuite/gcc.target/i386/pr36992-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr37101.c b/gcc/testsuite/gcc.target/i386/pr37101.c index 69b913c4103..8fd3bfc5f85 100644 --- a/gcc/testsuite/gcc.target/i386/pr37101.c +++ b/gcc/testsuite/gcc.target/i386/pr37101.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -ftree-vectorize -march=nocona" } */ -/* { dg-require-effective-target sse2 } */ typedef __SIZE_TYPE__ size_t; extern void *malloc (size_t); diff --git a/gcc/testsuite/gcc.target/i386/pr37275.c b/gcc/testsuite/gcc.target/i386/pr37275.c index ca9612bba30..070dab554c7 100644 --- a/gcc/testsuite/gcc.target/i386/pr37275.c +++ b/gcc/testsuite/gcc.target/i386/pr37275.c @@ -1,6 +1,7 @@ /* PR middle-end/37275 */ /* { dg-do compile { target ilp32 } } */ /* { dg-options "-g -dA -O2 -march=i686 -fstack-protector" } */ +/* { dg-require-visibility "" } */ typedef __SIZE_TYPE__ size_t; extern void *memcpy (void *, const void *, size_t); diff --git a/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc/testsuite/gcc.target/i386/pr37434-1.c index 00ed55e3234..b556bf0848e 100644 --- a/gcc/testsuite/gcc.target/i386/pr37434-1.c +++ b/gcc/testsuite/gcc.target/i386/pr37434-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef short __v8hi __attribute__ ((__vector_size__ (16))); typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc/testsuite/gcc.target/i386/pr37434-2.c index b92d52100da..00ff9fd2e6c 100644 --- a/gcc/testsuite/gcc.target/i386/pr37434-2.c +++ b/gcc/testsuite/gcc.target/i386/pr37434-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mtune=core2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef short __v8hi __attribute__ ((__vector_size__ (16))); typedef long long __m128i __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc/testsuite/gcc.target/i386/pr37434-3.c index 916c99fe02f..2cc597b04f5 100644 --- a/gcc/testsuite/gcc.target/i386/pr37434-3.c +++ b/gcc/testsuite/gcc.target/i386/pr37434-3.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ -/* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -msse4.1" } */ typedef char __v16qi __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc/testsuite/gcc.target/i386/pr37434-4.c index 15f8292b029..6848c63505e 100644 --- a/gcc/testsuite/gcc.target/i386/pr37434-4.c +++ b/gcc/testsuite/gcc.target/i386/pr37434-4.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ -/* { dg-require-effective-target sse4 } */ /* { dg-options "-O2 -mtune=core2 -msse4.1" } */ typedef char __v16qi __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc/testsuite/gcc.target/i386/pr39162.c index 1a5e3e7aab0..2d114b8fd00 100644 --- a/gcc/testsuite/gcc.target/i386/pr39162.c +++ b/gcc/testsuite/gcc.target/i386/pr39162.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -mno-avx" } */ -/* { dg-require-effective-target sse2 } */ typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/pr39315-1.c b/gcc/testsuite/gcc.target/i386/pr39315-1.c index 9f4d484639f..16ba5d59fe4 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-1.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-1.c @@ -1,7 +1,6 @@ /* PR middle-end/39315 */ /* { dg-do compile } */ /* { dg-options "-O -msse2 -mtune=generic" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "movups" } } */ /* { dg-final { scan-assembler-not "movlps" } } */ /* { dg-final { scan-assembler-not "movhps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr39315-2.c b/gcc/testsuite/gcc.target/i386/pr39315-2.c index 5363e97509b..c1a3da75a36 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-2.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-2.c @@ -1,7 +1,7 @@ /* PR middle-end/39315 */ /* { dg-do run } */ /* { dg-options "-O -msse2 -mtune=generic" } */ -/* { dg-require-effective-target sse2 } */ +/* { dg-require-effective-target sse2_runtime } */ /* { dg-additional-sources pr39315-check.c } */ typedef float __m128 __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr39315-3.c b/gcc/testsuite/gcc.target/i386/pr39315-3.c index 38ea7aed745..07862db603a 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-3.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-3.c @@ -1,7 +1,6 @@ /* PR middle-end/39315 */ /* { dg-do compile } */ /* { dg-options "-O -msse2 -mtune=generic" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler-not "movups" } } */ /* { dg-final { scan-assembler-not "movlps" } } */ /* { dg-final { scan-assembler-not "movhps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr39315-4.c b/gcc/testsuite/gcc.target/i386/pr39315-4.c index 4a62a1d51b9..77258a7c76c 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-4.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-4.c @@ -1,7 +1,7 @@ /* PR middle-end/39315 */ /* { dg-do run } */ /* { dg-options "-O -msse2 -mtune=generic" } */ -/* { dg-require-effective-target sse2 } */ +/* { dg-require-effective-target sse2_runtime } */ /* { dg-additional-sources pr39315-check.c } */ typedef float __m128 __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr39315-check.c b/gcc/testsuite/gcc.target/i386/pr39315-check.c index 8f7376015d0..cb09d3f2be5 100644 --- a/gcc/testsuite/gcc.target/i386/pr39315-check.c +++ b/gcc/testsuite/gcc.target/i386/pr39315-check.c @@ -1,4 +1,5 @@ -/* { dg-compile } */ +/* { dg-do compile } */ + typedef float __m128 __attribute__ ((__vector_size__ (16))); __extension__ typedef __PTRDIFF_TYPE__ ptrdiff_t; diff --git a/gcc/testsuite/gcc.target/i386/pr39496.c b/gcc/testsuite/gcc.target/i386/pr39496.c index bdaca2e55a8..e4132a1165b 100644 --- a/gcc/testsuite/gcc.target/i386/pr39496.c +++ b/gcc/testsuite/gcc.target/i386/pr39496.c @@ -1,7 +1,6 @@ /* PR target/39496 */ /* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */ /* { dg-options "-O0 -fverbose-asm -fno-omit-frame-pointer -mtune=i686 -msse2 -mfpmath=sse" } */ -/* { dg-require-effective-target sse2 } */ /* Verify that {foo,bar}{,2}param are all passed on the stack, using normal calling conventions, when not optimizing. */ /* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*fooparam," } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr40957.c b/gcc/testsuite/gcc.target/i386/pr40957.c index 56762d7e810..b7ee26dffcd 100644 --- a/gcc/testsuite/gcc.target/i386/pr40957.c +++ b/gcc/testsuite/gcc.target/i386/pr40957.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ -/* { dg-require-effective-target avx } */ /* { dg-options "-O2 -mavx" } */ typedef int __v8si __attribute__((__vector_size__(32))); diff --git a/gcc/testsuite/gcc.target/i386/pr42542-3a.c b/gcc/testsuite/gcc.target/i386/pr42542-3a.c index 89c9ed4945b..754e59e8487 100644 --- a/gcc/testsuite/gcc.target/i386/pr42542-3a.c +++ b/gcc/testsuite/gcc.target/i386/pr42542-3a.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O1 -msse2 -ftree-vectorize" } */ -/* { dg-require-effective-target sse2 } */ #include "pr42542-3.c" diff --git a/gcc/testsuite/gcc.target/i386/pr44942.c b/gcc/testsuite/gcc.target/i386/pr44942.c new file mode 100644 index 00000000000..4664f7e0d53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr44942.c @@ -0,0 +1,44 @@ +/* PR target/44942 */ +/* { dg-do run { target lp64 } } */ + +#include <stdarg.h> +#include <emmintrin.h> + +void +test1 (double a, double b, double c, double d, double e, double f, + double g, __m128d h, ...) +{ + double i; + va_list ap; + + va_start (ap, h); + i = va_arg (ap, double); + if (i != 1234.0) + __builtin_abort (); + va_end (ap); +} + +void +test2 (double a, double b, double c, double d, double e, double f, double g, + __m128d h, double i, __m128d j, double k, __m128d l, + double m, __m128d n, ...) +{ + double o; + va_list ap; + + va_start (ap, n); + o = va_arg (ap, double); + if (o != 1234.0) + __builtin_abort (); + va_end (ap); +} + +int +main () +{ + __m128d m = _mm_set1_pd (7.0); + test1 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 1234.0); + test2 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 0.0, m, + 0.0, m, 0.0, m, 1234.0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/push-1.c b/gcc/testsuite/gcc.target/i386/push-1.c index 797ad575dd1..09464bf9229 100644 --- a/gcc/testsuite/gcc.target/i386/push-1.c +++ b/gcc/testsuite/gcc.target/i386/push-1.c @@ -1,6 +1,5 @@ /* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */ /* { dg-options "-w -msse2 -Os" } */ -/* { dg-require-effective-target sse2 } */ typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/quad-sse.c b/gcc/testsuite/gcc.target/i386/quad-sse.c index 8c594452618..4b6fe792575 100644 --- a/gcc/testsuite/gcc.target/i386/quad-sse.c +++ b/gcc/testsuite/gcc.target/i386/quad-sse.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ __float128 x, y; diff --git a/gcc/testsuite/gcc.target/i386/rdfsbase-1.c b/gcc/testsuite/gcc.target/i386/rdfsbase-1.c new file mode 100644 index 00000000000..c4808e9683b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdfsbase-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)eax" } } */ + +#include <immintrin.h> + +unsigned int +read_fs_base32 (void) +{ + return _readfsbase_u32 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdfsbase-2.c b/gcc/testsuite/gcc.target/i386/rdfsbase-2.c new file mode 100644 index 00000000000..40b8f4a999f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdfsbase-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)rax" } } */ + +#include <immintrin.h> + +unsigned long long +read_fs_base64 (void) +{ + return _readfsbase_u64 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdgsbase-1.c b/gcc/testsuite/gcc.target/i386/rdgsbase-1.c new file mode 100644 index 00000000000..1e5a302085e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdgsbase-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)eax" } } */ + +#include <immintrin.h> + +unsigned int +read_gs_base32 (void) +{ + return _readgsbase_u32 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdgsbase-2.c b/gcc/testsuite/gcc.target/i386/rdgsbase-2.c new file mode 100644 index 00000000000..13215825069 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdgsbase-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)rax" } } */ + +#include <immintrin.h> + +unsigned long long +read_gs_base64 (void) +{ + return _readgsbase_u64 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdrand-1.c b/gcc/testsuite/gcc.target/i386/rdrand-1.c new file mode 100644 index 00000000000..4f6b9e177e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdrand-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mrdrnd " } */ +/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)ax" } } */ +/* { dg-final { scan-assembler "jnc\[ \t]+" } } */ + +#include <immintrin.h> + +unsigned short +read_rdrand16 (void) +{ + return _rdrand_u16 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdrand-2.c b/gcc/testsuite/gcc.target/i386/rdrand-2.c new file mode 100644 index 00000000000..22973834dca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdrand-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mrdrnd " } */ +/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)eax" } } */ +/* { dg-final { scan-assembler "jnc\[ \t]+" } } */ + +#include <immintrin.h> + +unsigned int +read_rdrand32 (void) +{ + return _rdrand_u32 (); +} diff --git a/gcc/testsuite/gcc.target/i386/rdrand-3.c b/gcc/testsuite/gcc.target/i386/rdrand-3.c new file mode 100644 index 00000000000..17c7c6fff24 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdrand-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mrdrnd " } */ +/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)rax" } } */ +/* { dg-final { scan-assembler "jnc\[ \t]+" } } */ + +#include <immintrin.h> + +unsigned long long +read_rdrand64 (void) +{ + return _rdrand_u64 (); +} diff --git a/gcc/testsuite/gcc.target/i386/reload-1.c b/gcc/testsuite/gcc.target/i386/reload-1.c index 299871585e2..f8075acaed4 100644 --- a/gcc/testsuite/gcc.target/i386/reload-1.c +++ b/gcc/testsuite/gcc.target/i386/reload-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O3 -msse2 -fdump-rtl-csa" } */ /* { dg-skip-if "no stdint" { vxworks_kernel } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 77baff0f4b9..2d50f41d540 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -2,7 +2,7 @@ abmintrin.h, lwpintrin.h, popcntintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 96214e02280..01809d0cffa 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ #include <mm_malloc.h> @@ -50,6 +50,8 @@ #define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) #define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) #define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1) +#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1) /* wmmintrin.h */ #define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 96a3f210eb0..d256e68c4be 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul -mpopcnt -mabm -mlwp" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */ #include <mm_malloc.h> @@ -89,6 +89,9 @@ test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1) #endif test_1 (_mm256_round_pd, __m256d, __m256d, 1) test_1 (_mm256_round_ps, __m256, __m256, 1) +test_1 (_cvtss_sh, unsigned short, float, 1) +test_1 (_mm_cvtps_ph, __m128i, __m128, 1) +test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) /* wmmintrin.h */ test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-15.c b/gcc/testsuite/gcc.target/i386/sse-15.c index ed91ee65d38..5a1da7a755f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-15.c +++ b/gcc/testsuite/gcc.target/i386/sse-15.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse -msse2" } */ -/* { dg-require-effective-target sse2 } */ /* Test that the intrinsics compile with optimization. These were not tested in i386-sse-[12].c because these builtins require immediate diff --git a/gcc/testsuite/gcc.target/i386/sse-19.c b/gcc/testsuite/gcc.target/i386/sse-19.c index 112c3e1cfad..43c090bd4e1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-19.c +++ b/gcc/testsuite/gcc.target/i386/sse-19.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O3 -msse2" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "punpcklbw" } } */ extern void abort(); #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-2.c b/gcc/testsuite/gcc.target/i386/sse-2.c index cbaa5e6a30d..c2f3e0b17cd 100644 --- a/gcc/testsuite/gcc.target/i386/sse-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -msse" } */ + #include <xmmintrin.h> static const __m128 v_sign = {-.0f, -.0f, -.0f, -.0f}; static const __m128 v_half = {0.5f, 0.5f, 0.5f, 0.5f}; diff --git a/gcc/testsuite/gcc.target/i386/sse-20.c b/gcc/testsuite/gcc.target/i386/sse-20.c index 5aa8f7a2812..fc0744f2554 100644 --- a/gcc/testsuite/gcc.target/i386/sse-20.c +++ b/gcc/testsuite/gcc.target/i386/sse-20.c @@ -1,5 +1,6 @@ /* PR target/13685 */ /* { dg-options "-Os -msse" } */ +/* { dg-require-effective-target sse } */ typedef float __m128 __attribute__ ((vector_size (16))); typedef int __m64 __attribute__ ((vector_size (8))); diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 6d976972d28..bb0472d471c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -39,7 +39,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp") +#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp,fsgsbase,rdrnd,f16c") #endif /* Following intrinsics require immediate arguments. They @@ -179,3 +179,12 @@ test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1) test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1) test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1) #endif + +/* immintrin.h (F16C). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("f16c") +#endif +#include <x86intrin.h> +test_1 (_cvtss_sh, unsigned short, float, 1) +test_1 (_mm_cvtps_ph, __m128i, __m128, 1) +test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index f74d3a71f6e..0e15bb25418 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -126,6 +126,8 @@ #define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) #define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) #define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1) +#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1) /* xopintrin.h */ #define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1) @@ -139,7 +141,7 @@ #define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1) #define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1) -#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp") +#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp,fsgsbase,rdrnd,f16c") #include <wmmintrin.h> #include <smmintrin.h> #include <mm3dnow.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-3.c b/gcc/testsuite/gcc.target/i386/sse-3.c index 338b7c60ba7..1be1d1aa223 100644 --- a/gcc/testsuite/gcc.target/i386/sse-3.c +++ b/gcc/testsuite/gcc.target/i386/sse-3.c @@ -1,6 +1,7 @@ /* PR target/21149 */ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-4.c b/gcc/testsuite/gcc.target/i386/sse-4.c index 5d49884ab85..394ad9d7ec4 100644 --- a/gcc/testsuite/gcc.target/i386/sse-4.c +++ b/gcc/testsuite/gcc.target/i386/sse-4.c @@ -1,7 +1,6 @@ /* This testcase caused a buffer overflow in simplify_immed_subreg. */ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-7.c b/gcc/testsuite/gcc.target/i386/sse-7.c index 12b88ca53f3..30e2c13ba04 100644 --- a/gcc/testsuite/gcc.target/i386/sse-7.c +++ b/gcc/testsuite/gcc.target/i386/sse-7.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-9.c b/gcc/testsuite/gcc.target/i386/sse-9.c index 0106cb52f63..e1a0a2270cb 100644 --- a/gcc/testsuite/gcc.target/i386/sse-9.c +++ b/gcc/testsuite/gcc.target/i386/sse-9.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-addps-1.c b/gcc/testsuite/gcc.target/i386/sse-addps-1.c index 2aa1cfa411a..b280667b5d0 100644 --- a/gcc/testsuite/gcc.target/i386/sse-addps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-addps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-addss-1.c b/gcc/testsuite/gcc.target/i386/sse-addss-1.c index 911a6cd9192..43aa2d53efd 100644 --- a/gcc/testsuite/gcc.target/i386/sse-addss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-addss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-andnps-1.c b/gcc/testsuite/gcc.target/i386/sse-andnps-1.c index 06d1e07dd40..eeeec020a7d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-andnps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-andnps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-andps-1.c b/gcc/testsuite/gcc.target/i386/sse-andps-1.c index aa46b8a28b7..6094dba7d34 100644 --- a/gcc/testsuite/gcc.target/i386/sse-andps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-andps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-check.h b/gcc/testsuite/gcc.target/i386/sse-check.h index 85629cc71b9..11b71bc3e97 100644 --- a/gcc/testsuite/gcc.target/i386/sse-check.h +++ b/gcc/testsuite/gcc.target/i386/sse-check.h @@ -1,8 +1,7 @@ -#include <stdio.h> #include <stdlib.h> #include "m128-check.h" - #include "cpuid.h" +#include "sse-os-support.h" static void sse_test (void); @@ -22,7 +21,7 @@ main () return 0; /* Run SSE test only if host has SSE support. */ - if (edx & bit_SSE) + if ((edx & bit_SSE) && sse_os_support ()) do_test (); return 0; diff --git a/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c b/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c index e4be7318e06..45438bcd1b7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse -std=c99" } */ +/* { dg-require-effective-target sse } */ +/* { dg-require-effective-target c99_runtime } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-1.c b/gcc/testsuite/gcc.target/i386/sse-comiss-1.c index 2892a70a67b..ff623aa8bed 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-2.c b/gcc/testsuite/gcc.target/i386/sse-comiss-2.c index 63b6d6d113f..d674bed002b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-3.c b/gcc/testsuite/gcc.target/i386/sse-comiss-3.c index 75ac4e4faaf..d2301ad8e51 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-3.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-4.c b/gcc/testsuite/gcc.target/i386/sse-comiss-4.c index ceeeca79472..7f372e249b9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-4.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-4.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-5.c b/gcc/testsuite/gcc.target/i386/sse-comiss-5.c index 8f503512ffa..104fdd701f7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-5.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-5.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-comiss-6.c b/gcc/testsuite/gcc.target/i386/sse-comiss-6.c index 38df9b8e47b..8229b7d55d7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-comiss-6.c +++ b/gcc/testsuite/gcc.target/i386/sse-comiss-6.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c b/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c index 9342e2c7187..bd85889503d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c index e5435b6b733..740227feef4 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c index aa74e11ec55..6abc4d5afed 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c index 5740626659a..3f8c549c962 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c index e136b7198a0..44a5fafc31b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c index 8edc197eafd..667806d970f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c index 94e831e782f..eb85223450d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target sse } */ /* { dg-options "-O2 -msse" } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/i386/sse-divps-1.c b/gcc/testsuite/gcc.target/i386/sse-divps-1.c index d4d441aeb1f..321bb5ac7c6 100644 --- a/gcc/testsuite/gcc.target/i386/sse-divps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-divps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-divss-1.c b/gcc/testsuite/gcc.target/i386/sse-divss-1.c index e7449496e0a..1427e4f1a44 100644 --- a/gcc/testsuite/gcc.target/i386/sse-divss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-divss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c b/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c index 5c254772709..f2513154788 100644 --- a/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c b/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c index 4cb1f337e2a..eea03ecadea 100644 --- a/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-maxps-1.c b/gcc/testsuite/gcc.target/i386/sse-maxps-1.c index 5e6fcd654ef..9a82f665a4b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-maxps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-maxps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-maxss-1.c b/gcc/testsuite/gcc.target/i386/sse-maxss-1.c index 5b5215a5772..7b88dfce710 100644 --- a/gcc/testsuite/gcc.target/i386/sse-maxss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-maxss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-minps-1.c b/gcc/testsuite/gcc.target/i386/sse-minps-1.c index a41139f8b96..452df8318ab 100644 --- a/gcc/testsuite/gcc.target/i386/sse-minps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-minps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-minss-1.c b/gcc/testsuite/gcc.target/i386/sse-minss-1.c index 9280b07052d..b7288f85915 100644 --- a/gcc/testsuite/gcc.target/i386/sse-minss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-minss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movaps-1.c b/gcc/testsuite/gcc.target/i386/sse-movaps-1.c index 3677ac44288..ed3562ba53a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movaps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movaps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movaps-2.c b/gcc/testsuite/gcc.target/i386/sse-movaps-2.c index 46b971a9d9c..fcfa80bebbc 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movaps-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-movaps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c b/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c index 7023bf95d1e..4d7b3edc2ac 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movhps-1.c b/gcc/testsuite/gcc.target/i386/sse-movhps-1.c index 9f28927a881..44b88592701 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movhps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movhps-2.c b/gcc/testsuite/gcc.target/i386/sse-movhps-2.c index 023937b6633..11ab383977c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movhps-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-movhps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c b/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c index aba9a9aa413..4ce3edf59e7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c b/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c index f1f0d7ed5a4..8557a30214b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movntps-1.c b/gcc/testsuite/gcc.target/i386/sse-movntps-1.c index 8c45da31dde..067f29616e1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movntps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movntps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movss-1.c b/gcc/testsuite/gcc.target/i386/sse-movss-1.c index eccdf5af907..ee53d5faf11 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movss-2.c b/gcc/testsuite/gcc.target/i386/sse-movss-2.c index f64fa4db698..638666594c9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movss-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-movss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movss-3.c b/gcc/testsuite/gcc.target/i386/sse-movss-3.c index 1212622b7ea..a090aada7f5 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movss-3.c +++ b/gcc/testsuite/gcc.target/i386/sse-movss-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movups-1.c b/gcc/testsuite/gcc.target/i386/sse-movups-1.c index 222da79d940..7ea9122897a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movups-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-movups-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-movups-2.c b/gcc/testsuite/gcc.target/i386/sse-movups-2.c index 41657239c32..188967a2a37 100644 --- a/gcc/testsuite/gcc.target/i386/sse-movups-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-movups-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-mulps-1.c b/gcc/testsuite/gcc.target/i386/sse-mulps-1.c index a07b5abf610..de66a28e142 100644 --- a/gcc/testsuite/gcc.target/i386/sse-mulps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-mulps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-mulss-1.c b/gcc/testsuite/gcc.target/i386/sse-mulss-1.c index 7b45063508d..99161a811a1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-mulss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-mulss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-orps-1.c b/gcc/testsuite/gcc.target/i386/sse-orps-1.c index 6c8dac5cc5c..605603726c0 100644 --- a/gcc/testsuite/gcc.target/i386/sse-orps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-orps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-os-support.h b/gcc/testsuite/gcc.target/i386/sse-os-support.h new file mode 100644 index 00000000000..a2b4e2d3c7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-os-support.h @@ -0,0 +1,55 @@ +#if defined(__sun__) && defined(__svr4__) +/* Make sure sigaction() is declared even with -std=c99. */ +#define __EXTENSIONS__ +#include <signal.h> +#include <ucontext.h> + +static volatile sig_atomic_t sigill_caught; + +static void +sigill_hdlr (int sig __attribute((unused)), + siginfo_t *sip __attribute__((unused)), + ucontext_t *ucp) +{ + sigill_caught = 1; + /* Set PC to the instruction after the faulting one to skip over it, + otherwise we enter an infinite loop. */ + ucp->uc_mcontext.gregs[EIP] += 4; + setcontext (ucp); +} +#endif + +/* Check if the OS supports executing SSE instructions. This function is + only used in sse-check.h, sse2-check.h, and sse3-check.h so far since + Solaris 8 and 9 won't run on newer CPUs anyway. */ + +static int +sse_os_support (void) +{ +#if defined(__sun__) && defined(__svr4__) + /* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions + even if the CPU supports them. Programs receive SIGILL instead, so + check for that at runtime. */ + + struct sigaction act, oact; + + act.sa_handler = sigill_hdlr; + sigemptyset (&act.sa_mask); + /* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler. */ + act.sa_flags = SA_SIGINFO; + sigaction (SIGILL, &act, &oact); + + /* We need a single SSE instruction here so the handler can safely skip + over it. */ + __asm__ volatile ("movss %xmm2,%xmm1"); + + sigaction (SIGILL, &oact, NULL); + + if (sigill_caught) + exit (0); + else + return 1; +#else + return 1; +#endif /* __sun__ && __svr4__ */ +} diff --git a/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c b/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c index 7a1a8fa7370..4d0783515e6 100644 --- a/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-recip-vec.c b/gcc/testsuite/gcc.target/i386/sse-recip-vec.c index 202351dc987..bb1e458f92d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-recip-vec.c +++ b/gcc/testsuite/gcc.target/i386/sse-recip-vec.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-recip.c b/gcc/testsuite/gcc.target/i386/sse-recip.c index d88eb7f007b..4f7d3bf3d54 100644 --- a/gcc/testsuite/gcc.target/i386/sse-recip.c +++ b/gcc/testsuite/gcc.target/i386/sse-recip.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c b/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c index 4052c21f010..c2db7254957 100644 --- a/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c b/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c index 8232c7229c5..5a0c9b95d66 100644 --- a/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c b/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c index 9f0658d0e27..1dbd260e515 100644 --- a/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-subps-1.c b/gcc/testsuite/gcc.target/i386/sse-subps-1.c index 2e7e8d50231..e63e4784a11 100644 --- a/gcc/testsuite/gcc.target/i386/sse-subps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-subps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-subss-1.c b/gcc/testsuite/gcc.target/i386/sse-subss-1.c index 5b3ef26bd9f..5d9a5f504f9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-subss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-subss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c index b38b1fd424a..4d72b01873e 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c index e0212a4e3df..dc4ba8045b3 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c index dc728fb503b..042898bf6d2 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c index 3251c0b8fb0..a3f32bb3576 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c index ad34f01d979..821dd772640 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c b/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c index b9b2f4b2892..602a923a0a5 100644 --- a/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c +++ b/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c b/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c index be4ab3659cb..005924b5b6c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c b/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c index 5a5da2064a1..456ef201bca 100644 --- a/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse-vect-types.c b/gcc/testsuite/gcc.target/i386/sse-vect-types.c index 2658f020eff..9cb6f3e07cd 100644 --- a/gcc/testsuite/gcc.target/i386/sse-vect-types.c +++ b/gcc/testsuite/gcc.target/i386/sse-vect-types.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O0 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <xmmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-xorps-1.c b/gcc/testsuite/gcc.target/i386/sse-xorps-1.c index 6f96e691064..8ec500838ae 100644 --- a/gcc/testsuite/gcc.target/i386/sse-xorps-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-xorps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ #ifndef CHECK_H #define CHECK_H "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse2-check.h b/gcc/testsuite/gcc.target/i386/sse2-check.h index e9f17f04079..fd4a6ce1dbf 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-check.h +++ b/gcc/testsuite/gcc.target/i386/sse2-check.h @@ -1,6 +1,7 @@ #include <stdlib.h> #include "cpuid.h" #include "m128-check.h" +#include "sse-os-support.h" static void sse2_test (void); @@ -20,7 +21,7 @@ main () return 0; /* Run SSE2 test only if host has SSE2 support. */ - if (edx & bit_SSE2) + if ((edx & bit_SSE2) && sse_os_support ()) do_test (); return 0; diff --git a/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c b/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c index 953f220d1b1..153fd2bf045 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c +++ b/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse2 -std=c99" } */ /* { dg-require-effective-target sse2 } */ +/* { dg-require-effective-target c99_runtime } */ #ifndef CHECK_H #define CHECK_H "sse2-check.h" diff --git a/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c b/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c index ed067082594..a2676396cd3 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c +++ b/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ #include <emmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse3-check.h b/gcc/testsuite/gcc.target/i386/sse3-check.h index df0e63a4575..5a0a0b1a02e 100644 --- a/gcc/testsuite/gcc.target/i386/sse3-check.h +++ b/gcc/testsuite/gcc.target/i386/sse3-check.h @@ -1,7 +1,7 @@ #include <stdio.h> #include <stdlib.h> - #include "cpuid.h" +#include "sse-os-support.h" static void sse3_test (void); @@ -21,7 +21,7 @@ main () return 0; /* Run SSE3 test only if host has SSE3 support. */ - if (ecx & bit_SSE3) + if ((ecx & bit_SSE3) && sse_os_support ()) do_test (); return 0; diff --git a/gcc/testsuite/gcc.target/i386/ssefn-2.c b/gcc/testsuite/gcc.target/i386/ssefn-2.c index dfaacf6bdca..09b920ea7ca 100644 --- a/gcc/testsuite/gcc.target/i386/ssefn-2.c +++ b/gcc/testsuite/gcc.target/i386/ssefn-2.c @@ -3,7 +3,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "movss" } } */ /* { dg-final { scan-assembler "mulss" } } */ /* { dg-final { scan-assembler "movsd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssefn-3.c b/gcc/testsuite/gcc.target/i386/ssefn-3.c index adf72cce18a..b96b21179dc 100644 --- a/gcc/testsuite/gcc.target/i386/ssefn-3.c +++ b/gcc/testsuite/gcc.target/i386/ssefn-3.c @@ -3,6 +3,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -msse -mfpmath=sse" } */ +/* { dg-require-effective-target sse } */ #include "sse-check.h" diff --git a/gcc/testsuite/gcc.target/i386/ssefp-1.c b/gcc/testsuite/gcc.target/i386/ssefp-1.c index fdce233173b..621e362f490 100644 --- a/gcc/testsuite/gcc.target/i386/ssefp-1.c +++ b/gcc/testsuite/gcc.target/i386/ssefp-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "maxsd" } } */ /* { dg-final { scan-assembler "minsd" } } */ double x; diff --git a/gcc/testsuite/gcc.target/i386/ssefp-2.c b/gcc/testsuite/gcc.target/i386/ssefp-2.c index 0b8b72262b5..a6caee398b2 100644 --- a/gcc/testsuite/gcc.target/i386/ssefp-2.c +++ b/gcc/testsuite/gcc.target/i386/ssefp-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "maxsd" } } */ /* { dg-final { scan-assembler "minsd" } } */ double x; diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-3.c b/gcc/testsuite/gcc.target/i386/sseregparm-3.c index 7475e4f827f..9ee82af44ae 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-3.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-3.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-4.c b/gcc/testsuite/gcc.target/i386/sseregparm-4.c index b8fc521264e..a29cf06bf5c 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-4.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-4.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-5.c b/gcc/testsuite/gcc.target/i386/sseregparm-5.c index fa41a2c87b9..7423722d694 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-5.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-5.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-6.c b/gcc/testsuite/gcc.target/i386/sseregparm-6.c index d0358c5e693..6203b6b5971 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-6.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-6.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/sseregparm-7.c b/gcc/testsuite/gcc.target/i386/sseregparm-7.c index 99953b5aa9c..61267df9853 100644 --- a/gcc/testsuite/gcc.target/i386/sseregparm-7.c +++ b/gcc/testsuite/gcc.target/i386/sseregparm-7.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-msse2 -O2" } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* Make sure we know that mysinfp returns in %xmm0. */ diff --git a/gcc/testsuite/gcc.target/i386/ssetype-1.c b/gcc/testsuite/gcc.target/i386/ssetype-1.c index 00ea2857484..ef89059b8d8 100644 --- a/gcc/testsuite/gcc.target/i386/ssetype-1.c +++ b/gcc/testsuite/gcc.target/i386/ssetype-1.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* This test checks for absolute memory operands. */ /* { dg-require-effective-target nonpic } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2 -march=k8" } */ /* { dg-final { scan-assembler "andpd\[^\\n\]*magic" } } */ /* { dg-final { scan-assembler "andnpd\[^\\n\]*magic" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssetype-2.c b/gcc/testsuite/gcc.target/i386/ssetype-2.c index c6a8ba7b548..b68a63923fb 100644 --- a/gcc/testsuite/gcc.target/i386/ssetype-2.c +++ b/gcc/testsuite/gcc.target/i386/ssetype-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "andpd" } } */ /* { dg-final { scan-assembler "andnpd" } } */ /* { dg-final { scan-assembler "xorpd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssetype-3.c b/gcc/testsuite/gcc.target/i386/ssetype-3.c index 0e83e28c468..d6887d5cd20 100644 --- a/gcc/testsuite/gcc.target/i386/ssetype-3.c +++ b/gcc/testsuite/gcc.target/i386/ssetype-3.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* This test checks for absolute memory operands. */ /* { dg-require-effective-target nonpic } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2 -march=k8" } */ /* { dg-final { scan-assembler "andps\[^\\n\]*magic" } } */ /* { dg-final { scan-assembler "andnps\[^\\n\]*magic" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssetype-4.c b/gcc/testsuite/gcc.target/i386/ssetype-4.c index 9b68792390d..9994b07f21c 100644 --- a/gcc/testsuite/gcc.target/i386/ssetype-4.c +++ b/gcc/testsuite/gcc.target/i386/ssetype-4.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -march=k8" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "andps" } } */ /* { dg-final { scan-assembler "andnps" } } */ /* { dg-final { scan-assembler "xorps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssetype-5.c b/gcc/testsuite/gcc.target/i386/ssetype-5.c index 098ed89ad66..75133e9fa68 100644 --- a/gcc/testsuite/gcc.target/i386/ssetype-5.c +++ b/gcc/testsuite/gcc.target/i386/ssetype-5.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* This test checks for absolute memory operands. */ /* { dg-require-effective-target nonpic } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -msse2 -march=k8" } */ /* { dg-final { scan-assembler "pand\[^\\n\]*magic" } } */ /* { dg-final { scan-assembler "pandn\[^\\n\]*magic" } } */ diff --git a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c index 87210d817a8..dd2c2e8b452 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { ! { ilp32 && dfp } } { "*" } { "" } } */ /* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */ +/* { dg-require-effective-target sse } */ /* This compile only test is to detect an assertion failure in stack branch development. */ diff --git a/gcc/testsuite/gcc.target/i386/unordcmp-1.c b/gcc/testsuite/gcc.target/i386/unordcmp-1.c index 85de4865d2f..49d4b8e076a 100644 --- a/gcc/testsuite/gcc.target/i386/unordcmp-1.c +++ b/gcc/testsuite/gcc.target/i386/unordcmp-1.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "cmpunordss" } } */ /* { dg-final { scan-assembler "cmpunordps" } } */ /* { dg-final { scan-assembler "cmpunordsd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c b/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c new file mode 100644 index 00000000000..3b46671f056 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union128i_w val; + union128 res; + float exp[4]; + + exp[0] = 1; + exp[1] = -2; + exp[2] = -1; + exp[3] = 2; + + val.a[0] = 0x3c00; + val.a[1] = 0xc000; + val.a[2] = 0xbc00; + val.a[3] = 0x4000; + + res.x = _mm_cvtph_ps (val.x); + + if (check_union128 (res, exp)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c b/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c new file mode 100644 index 00000000000..1523deaa1d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union256 res; + union128i_w val; + float exp[8]; + + exp[0] = 1; + exp[1] = 2; + exp[2] = 4; + exp[3] = 8; + exp[4] = -1; + exp[5] = -2; + exp[6] = -4; + exp[7] = -8; + + val.a[0] = 0x3c00; + val.a[1] = 0x4000; + val.a[2] = 0x4400; + val.a[3] = 0x4800; + val.a[4] = 0xbc00; + val.a[5] = 0xc000; + val.a[6] = 0xc400; + val.a[7] = 0xc800; + + res.x = _mm256_cvtph_ps (val.x); + + if (check_union256 (res, exp)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c b/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c new file mode 100644 index 00000000000..49b61f678c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + unsigned short val = 0xc000; + float exp = -2; + float res; + + res = _cvtsh_ss (val); + + if (res != exp) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c b/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c new file mode 100644 index 00000000000..c114c98ad8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union128 val; + union128i_w res; + short exp[8]; + + val.a[0] = 1; + val.a[1] = -2; + val.a[2] = -1; + val.a[3] = 2; + + exp[0] = 0x3c00; + exp[1] = 0xc000; + exp[2] = 0xbc00; + exp[3] = 0x4000; + exp[4] = 0; + exp[5] = 0; + exp[6] = 0; + exp[7] = 0; + + res.x = _mm_cvtps_ph (val.x, 0); + + if (check_union128i_w (res, exp)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c b/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c new file mode 100644 index 00000000000..57436ae86bf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union256 val; + union128i_w res; + short exp[8]; + + val.a[0] = 1; + val.a[1] = 2; + val.a[2] = 4; + val.a[3] = 8; + val.a[4] = -1; + val.a[5] = -2; + val.a[6] = -4; + val.a[7] = -8; + + exp[0] = 0x3c00; + exp[1] = 0x4000; + exp[2] = 0x4400; + exp[3] = 0x4800; + exp[4] = 0xbc00; + exp[5] = 0xc000; + exp[6] = 0xc400; + exp[7] = 0xc800; + + res.x = _mm256_cvtps_ph (val.x, 0); + + if (check_union128i_w (res, exp)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c b/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c new file mode 100644 index 00000000000..3b7cb5c5ca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + float val = -2; + unsigned short exp = 0xc000; + unsigned short res; + + res = _cvtss_sh (val, 0); + + if (res != exp) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc/testsuite/gcc.target/i386/vecinit-1.c index cba7429f242..fad0c07e100 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-1.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) float a; diff --git a/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc/testsuite/gcc.target/i386/vecinit-2.c index fdfa837c698..a3a7abc5340 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-2.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) int a; diff --git a/gcc/testsuite/gcc.target/i386/vecinit-3.c b/gcc/testsuite/gcc.target/i386/vecinit-3.c index aae642ae27c..062fb1ed10a 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-3.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) char a; diff --git a/gcc/testsuite/gcc.target/i386/vecinit-4.c b/gcc/testsuite/gcc.target/i386/vecinit-4.c index 101b68badc4..2dfa29c4922 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-4.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) short a; diff --git a/gcc/testsuite/gcc.target/i386/vecinit-5.c b/gcc/testsuite/gcc.target/i386/vecinit-5.c index b9e7e27c78f..dcf8b9206aa 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-5.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) float a, b; diff --git a/gcc/testsuite/gcc.target/i386/vecinit-6.c b/gcc/testsuite/gcc.target/i386/vecinit-6.c index 3b22043273b..6817922d26b 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-6.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2" } */ -/* { dg-require-effective-target sse2 } */ + #define vector __attribute__((vector_size(16))) int a, b; diff --git a/gcc/testsuite/gcc.target/i386/vectorize1.c b/gcc/testsuite/gcc.target/i386/vectorize1.c index 7a5023aa905..f673e44c963 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize1.c +++ b/gcc/testsuite/gcc.target/i386/vectorize1.c @@ -1,5 +1,6 @@ /* PR middle-end/28915 */ /* { dg-options "-msse -O2 -ftree-vectorize -fdump-tree-vect" } */ +/* { dg-require-effective-target sse } */ extern char lanip[3][40]; typedef struct diff --git a/gcc/testsuite/gcc.target/i386/vectorize2.c b/gcc/testsuite/gcc.target/i386/vectorize2.c index a7196c70d13..41964871959 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize2.c +++ b/gcc/testsuite/gcc.target/i386/vectorize2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */ double a[256]; diff --git a/gcc/testsuite/gcc.target/i386/vectorize3.c b/gcc/testsuite/gcc.target/i386/vectorize3.c index e19f8d87bda..2947acbafda 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize3.c +++ b/gcc/testsuite/gcc.target/i386/vectorize3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */ float a[256]; diff --git a/gcc/testsuite/gcc.target/i386/vectorize4.c b/gcc/testsuite/gcc.target/i386/vectorize4.c index 9933d299729..f3d605e228a 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize4.c +++ b/gcc/testsuite/gcc.target/i386/vectorize4.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target sse2 } */ /* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 --param ggc-min-expand=0 --param ggc-min-heapsize=0" } */ /* This test, tests two thing, we vectorize square root and also we don't crash due to a GC issue. */ diff --git a/gcc/testsuite/gcc.target/i386/vectorize6.c b/gcc/testsuite/gcc.target/i386/vectorize6.c index 41e61aa2ccd..78ec53d15a8 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize6.c +++ b/gcc/testsuite/gcc.target/i386/vectorize6.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -msse2 -ftree-vectorize -mveclibabi=svml -ffast-math" } */ -/* { dg-require-effective-target sse2 } */ double x[256]; diff --git a/gcc/testsuite/gcc.target/i386/vectorize7.c b/gcc/testsuite/gcc.target/i386/vectorize7.c index eca043bdfa2..10b7ba27868 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize7.c +++ b/gcc/testsuite/gcc.target/i386/vectorize7.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -msse2" } */ -/* { dg-require-effective-target sse2 } */ unsigned int a[256]; float b[256]; diff --git a/gcc/testsuite/gcc.target/i386/vectorize8.c b/gcc/testsuite/gcc.target/i386/vectorize8.c index e26362035ad..ed1517b93ef 100644 --- a/gcc/testsuite/gcc.target/i386/vectorize8.c +++ b/gcc/testsuite/gcc.target/i386/vectorize8.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -msse2" } */ -/* { dg-require-effective-target sse2 } */ unsigned int a[256]; double b[256]; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v2df.c b/gcc/testsuite/gcc.target/i386/vperm-v2df.c index d0394635c59..40a51306fdc 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v2df.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v2df.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target sse2 } */ #include "isa-check.h" +#include "sse-os-support.h" typedef double S; typedef double V __attribute__((vector_size(16))); @@ -25,6 +26,11 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + + if (!sse_os_support ()) + exit (0); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v2di.c b/gcc/testsuite/gcc.target/i386/vperm-v2di.c index 940de68af19..8e300837da8 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v2di.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v2di.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target sse2 } */ #include "isa-check.h" +#include "sse-os-support.h" typedef long long S; typedef long long V __attribute__((vector_size(16))); @@ -25,6 +26,11 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + + if (!sse_os_support ()) + exit (0); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c b/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c index b9fc9b172fe..23608b3cf0a 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c @@ -1,7 +1,9 @@ /* { dg-do run } */ /* { dg-options "-O -msse" } */ +/* { dg-require-effective-target sse } */ #include "isa-check.h" +#include "sse-os-support.h" typedef float S; typedef float V __attribute__((vector_size(16))); @@ -26,6 +28,11 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + + if (!sse_os_support ()) + exit (0); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c b/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c index 61b0d5a80dd..a0d49874f99 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c @@ -27,6 +27,8 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c b/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c index 93c25c6826a..01b7c6fdab6 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target sse2 } */ #include "isa-check.h" +#include "sse-os-support.h" typedef int S; typedef int V __attribute__((vector_size(16))); @@ -27,6 +28,11 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + + if (!sse_os_support ()) + exit (0); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c b/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c index d77146896e4..43f88ee0935 100644 --- a/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c +++ b/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c @@ -27,6 +27,8 @@ extern int memcmp (const void *, const void *, __SIZE_TYPE__); int main() { + check_isa (); + i[0].s[0] = 0; i[0].s[1] = 1; i[0].s[2] = 2; diff --git a/gcc/testsuite/gcc.target/i386/wrfsbase-1.c b/gcc/testsuite/gcc.target/i386/wrfsbase-1.c new file mode 100644 index 00000000000..4b849269bb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/wrfsbase-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)edi" } } */ + +#include <immintrin.h> + +void +write_fs_base32 (unsigned int base) +{ + _writefsbase_u32 (base); +} diff --git a/gcc/testsuite/gcc.target/i386/wrfsbase-2.c b/gcc/testsuite/gcc.target/i386/wrfsbase-2.c new file mode 100644 index 00000000000..5e1762dfa3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/wrfsbase-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)rdi" } } */ + +#include <immintrin.h> + +void +write_fs_base64 (unsigned long long base) +{ + _writefsbase_u64 (base); +} diff --git a/gcc/testsuite/gcc.target/i386/wrgsbase-1.c b/gcc/testsuite/gcc.target/i386/wrgsbase-1.c new file mode 100644 index 00000000000..15d2d7ffb9c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/wrgsbase-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)edi" } } */ + +#include <immintrin.h> + +void +write_gs_base32 (unsigned int base) +{ + _writegsbase_u32 (base); +} diff --git a/gcc/testsuite/gcc.target/i386/wrgsbase-2.c b/gcc/testsuite/gcc.target/i386/wrgsbase-2.c new file mode 100644 index 00000000000..0a33d770710 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/wrgsbase-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)rdi" } } */ + +#include <immintrin.h> + +void +write_gs_base64 (unsigned long long base) +{ + _writegsbase_u64 (base); +} diff --git a/gcc/testsuite/gcc.target/i386/xorps-sse2.c b/gcc/testsuite/gcc.target/i386/xorps-sse2.c index 4d3994c88ef..3c268b4cbaa 100644 --- a/gcc/testsuite/gcc.target/i386/xorps-sse2.c +++ b/gcc/testsuite/gcc.target/i386/xorps-sse2.c @@ -1,7 +1,6 @@ /* Test that we generate xorps when the result is used in FP math. */ /* { dg-do compile } */ /* { dg-options "-O -msse2 -mno-sse3" } */ -/* { dg-require-effective-target sse2 } */ /* { dg-final { scan-assembler "xorps\[ \t\]" { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "pxor" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/i386/xorps.c b/gcc/testsuite/gcc.target/i386/xorps.c index bc2e97d76d6..6803a4d8916 100644 --- a/gcc/testsuite/gcc.target/i386/xorps.c +++ b/gcc/testsuite/gcc.target/i386/xorps.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-Os -msse2" } */ -/* { dg-require-effective-target sse2 } */ typedef float __m128 __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/m68k/pr45015.c b/gcc/testsuite/gcc.target/m68k/pr45015.c new file mode 100644 index 00000000000..fba9550e9ef --- /dev/null +++ b/gcc/testsuite/gcc.target/m68k/pr45015.c @@ -0,0 +1,26 @@ +/* PR debug/45015 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -g" } */ + +unsigned int +foo (unsigned int *x, const unsigned int *y, int z, unsigned int w) +{ + unsigned int a, b, c, s; + int j; + j = -z; + x -= j; + y -= j; + a = 0; + do + { + __asm__ ("move.l %2, %0; move.l %3, %1" : "=d" (b), "=d" (c) : "g<>" (y[j]), "d" (w)); + c += a; + a = (c < a) + b; + s = x[j]; + c = s + c; + a += (c < s); + x[j] = c; + } + while (++j != 0); + return a; +} diff --git a/gcc/testsuite/gcc.target/mips/cache-1.c b/gcc/testsuite/gcc.target/mips/cache-1.c index 05cb4079157..da897066d49 100644 --- a/gcc/testsuite/gcc.target/mips/cache-1.c +++ b/gcc/testsuite/gcc.target/mips/cache-1.c @@ -26,5 +26,5 @@ f4 (const volatile unsigned char *area) /* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */ /* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */ -/* { dg-final { scan-assembler "\tcache\t0x0,0\\(\\\$.\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */ /* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 02e031cd15c..0a7bc1de8dd 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -233,7 +233,7 @@ set mips_option_groups { fp "-mfp(32|64)" gp "-mgp(32|64)" long "-mlong(32|64)" - mips16 "-mips16|-mno-mips16" + mips16 "-mips16|-mno-mips16|-mflip-mips16" mips3d "-mips3d|-mno-mips3d" optimization "-O(|[0-3s])" pic "-f(no-|)(pic|PIC)" @@ -509,6 +509,14 @@ proc mips_have_option_p { upstatus option } { $option] } +# Return true if the options described by UPSTATUS require MIPS16 support. +proc mips_using_mips16_p { upstatus } { + upvar $upstatus status + + return [expr { [mips_have_option_p status "-mips16"] + || [mips_have_option_p status "-mflip-mips16"] }] +} + # Return true if the test described by UPSTATUS requires option OPTION. proc mips_have_test_option_p { upstatus option } { upvar $upstatus status @@ -763,7 +771,7 @@ proc mips-dg-finish {} { # # START END # | | -# -mips16 -mno-mips16 +# -mips16/-mflip-mips16 -mno-mips16 # | | # -mips3d -mno-mips3d # | | @@ -1011,7 +1019,7 @@ proc mips-dg-options { args } { # EABI doesn't support -mabicalls. # EABI doesn't support the combination -mgp32 -mfp64. set force_abi 1 - } elseif { [mips_have_option_p options "-mips16"] + } elseif { [mips_using_mips16_p options] && ![mips_same_option_p $abi "-mabi=32"] && ![mips_same_option_p $abi "-mabi=o64"] && (![mips_have_option_p options "addressing=absolute"] @@ -1048,7 +1056,7 @@ proc mips-dg-options { args } { mips_make_test_option options "-mfp32" } } - if { [mips_have_option_p options "-mips16"] + if { [mips_using_mips16_p options] && ![mips_same_option_p $abi "-mabi=32"] && ![mips_same_option_p $abi "-mabi=o64"] && (![mips_have_option_p options "addressing=absolute"] diff --git a/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c b/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c new file mode 100644 index 00000000000..de7cb4349b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-options "(-mips16)" } */ + +extern void abort (void); + +__complex float f = { -1.0 + -1.0i }; +__complex float __attribute__((nomips16)) foo (void) { return f; } +__complex float (*volatile foop) (void) = foo; +__complex float __attribute__((mips16, noinline)) bar (void) { return foop (); } + +int +main (void) +{ + if (bar () != f) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c b/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c index 594ec88b4e7..a2aa111459e 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c @@ -8,6 +8,6 @@ vector float *f (volatile vector float *a) { - return a; /* { dg-warning "discards qualifiers" } */ + return a; /* { dg-warning "discards 'volatile' qualifier" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/block-move-1.c b/gcc/testsuite/gcc.target/powerpc/block-move-1.c new file mode 100644 index 00000000000..7b6623fbe51 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/block-move-1.c @@ -0,0 +1,14 @@ +/* Test that we bump up low values of -mblock-move-inline-limit */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mblock-move-inline-limit=8" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *memcpy (void *, const void *, size_t); + +void +cpy16 (void *x, void *y) +{ + memcpy (x, y, 16); +} + +/* { dg-final { scan-assembler-not "memcpy" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/block-move-2.c b/gcc/testsuite/gcc.target/powerpc/block-move-2.c new file mode 100644 index 00000000000..ffaf9ef05e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/block-move-2.c @@ -0,0 +1,14 @@ +/* Test that we honor -mblock-move-inline-limit. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mblock-move-inline-limit=128" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *memcpy (void *, const void *, size_t); + +void +cpy128 (void *x, void *y) +{ + memcpy (x, y, 128); +} + +/* { dg-final { scan-assembler-not "memcpy" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c b/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c index 3d9afb25aa7..8efaeaba38a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c +++ b/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c @@ -1,5 +1,5 @@ /* { dg-do link { target { *-*-linux* && powerpc_fprs } } } */ -/* { dg-options "-W -Wall -Wno-uninitialized -mcpu=cell" } */ +/* { dg-options "-W -Wall -Wno-uninitialized -Wno-unused-but-set-variable -mcpu=cell" } */ /* Test some PPU intrinsics from <ppu_intrinsics.h>. */ #include <ppu_intrinsics.h> diff --git a/gcc/testsuite/gcc.target/powerpc/recip-1.c b/gcc/testsuite/gcc.target/powerpc/recip-1.c index d1e383dc4ea..590881bb892 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-1.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */ /* { dg-final { scan-assembler-times "frsqrte" 2 } } */ /* { dg-final { scan-assembler-times "fmsub" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-2.c b/gcc/testsuite/gcc.target/powerpc/recip-2.c index 69442733aab..3e64c07578f 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-2.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power5" } */ /* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ /* { dg-final { scan-assembler-times "fmsubs" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-3.c b/gcc/testsuite/gcc.target/powerpc/recip-3.c index 80a34e8ee59..c5ce539bb42 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-3.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */ /* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */ /* { dg-final { scan-assembler-times "xsmsub.dp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s b/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s index 5a7c91be6ee..b3b88466a62 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s +++ b/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s @@ -22,20 +22,20 @@ _snapshot: movq %r15, _r15(%rip) movdqu %xmm0, _xmm_regs+0(%rip) movdqu %xmm1, _xmm_regs+16(%rip) - movdqu %xmm2, _xmm_regs+16*2(%rip) - movdqu %xmm3, _xmm_regs+16*3(%rip) - movdqu %xmm4, _xmm_regs+16*4(%rip) - movdqu %xmm5, _xmm_regs+16*5(%rip) - movdqu %xmm6, _xmm_regs+16*6(%rip) - movdqu %xmm7, _xmm_regs+16*7(%rip) - movdqu %xmm8, _xmm_regs+16*8(%rip) - movdqu %xmm9, _xmm_regs+16*9(%rip) - movdqu %xmm10, _xmm_regs+16*10(%rip) - movdqu %xmm11, _xmm_regs+16*11(%rip) - movdqu %xmm12, _xmm_regs+16*12(%rip) - movdqu %xmm13, _xmm_regs+16*13(%rip) - movdqu %xmm14, _xmm_regs+16*14(%rip) - movdqu %xmm15, _xmm_regs+16*15(%rip) + movdqu %xmm2, _xmm_regs+32(%rip) + movdqu %xmm3, _xmm_regs+48(%rip) + movdqu %xmm4, _xmm_regs+64(%rip) + movdqu %xmm5, _xmm_regs+80(%rip) + movdqu %xmm6, _xmm_regs+96(%rip) + movdqu %xmm7, _xmm_regs+112(%rip) + movdqu %xmm8, _xmm_regs+128(%rip) + movdqu %xmm9, _xmm_regs+144(%rip) + movdqu %xmm10, _xmm_regs+160(%rip) + movdqu %xmm11, _xmm_regs+176(%rip) + movdqu %xmm12, _xmm_regs+192(%rip) + movdqu %xmm13, _xmm_regs+208(%rip) + movdqu %xmm14, _xmm_regs+224(%rip) + movdqu %xmm15, _xmm_regs+240(%rip) jmp *_callthis(%rip) .LFE3: .p2align 4,,15 diff --git a/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S b/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S index cb1e31ea785..8e0bffe8b49 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S +++ b/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S @@ -26,20 +26,20 @@ snapshot: movq %r15, r15(%rip) movdqu %xmm0, xmm_regs+0(%rip) movdqu %xmm1, xmm_regs+16(%rip) - movdqu %xmm2, xmm_regs+16*2(%rip) - movdqu %xmm3, xmm_regs+16*3(%rip) - movdqu %xmm4, xmm_regs+16*4(%rip) - movdqu %xmm5, xmm_regs+16*5(%rip) - movdqu %xmm6, xmm_regs+16*6(%rip) - movdqu %xmm7, xmm_regs+16*7(%rip) - movdqu %xmm8, xmm_regs+16*8(%rip) - movdqu %xmm9, xmm_regs+16*9(%rip) - movdqu %xmm10, xmm_regs+16*10(%rip) - movdqu %xmm11, xmm_regs+16*11(%rip) - movdqu %xmm12, xmm_regs+16*12(%rip) - movdqu %xmm13, xmm_regs+16*13(%rip) - movdqu %xmm14, xmm_regs+16*14(%rip) - movdqu %xmm15, xmm_regs+16*15(%rip) + movdqu %xmm2, xmm_regs+32(%rip) + movdqu %xmm3, xmm_regs+48(%rip) + movdqu %xmm4, xmm_regs+64(%rip) + movdqu %xmm5, xmm_regs+80(%rip) + movdqu %xmm6, xmm_regs+96(%rip) + movdqu %xmm7, xmm_regs+112(%rip) + movdqu %xmm8, xmm_regs+128(%rip) + movdqu %xmm9, xmm_regs+144(%rip) + movdqu %xmm10, xmm_regs+160(%rip) + movdqu %xmm11, xmm_regs+176(%rip) + movdqu %xmm12, xmm_regs+192(%rip) + movdqu %xmm13, xmm_regs+208(%rip) + movdqu %xmm14, xmm_regs+224(%rip) + movdqu %xmm15, xmm_regs+240(%rip) jmp *callthis(%rip) .LFE3: .size snapshot, .-snapshot diff --git a/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S b/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S index a4d002e19e4..d248ef02e84 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S +++ b/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S @@ -23,20 +23,20 @@ snapshot: movq %r15, r15(%rip) vmovdqu %ymm0, ymm_regs+0(%rip) vmovdqu %ymm1, ymm_regs+32(%rip) - vmovdqu %ymm2, ymm_regs+32*2(%rip) - vmovdqu %ymm3, ymm_regs+32*3(%rip) - vmovdqu %ymm4, ymm_regs+32*4(%rip) - vmovdqu %ymm5, ymm_regs+32*5(%rip) - vmovdqu %ymm6, ymm_regs+32*6(%rip) - vmovdqu %ymm7, ymm_regs+32*7(%rip) - vmovdqu %ymm8, ymm_regs+32*8(%rip) - vmovdqu %ymm9, ymm_regs+32*9(%rip) - vmovdqu %ymm10, ymm_regs+32*10(%rip) - vmovdqu %ymm11, ymm_regs+32*11(%rip) - vmovdqu %ymm12, ymm_regs+32*12(%rip) - vmovdqu %ymm13, ymm_regs+32*13(%rip) - vmovdqu %ymm14, ymm_regs+32*14(%rip) - vmovdqu %ymm15, ymm_regs+32*15(%rip) + vmovdqu %ymm2, ymm_regs+64(%rip) + vmovdqu %ymm3, ymm_regs+96(%rip) + vmovdqu %ymm4, ymm_regs+128(%rip) + vmovdqu %ymm5, ymm_regs+160(%rip) + vmovdqu %ymm6, ymm_regs+192(%rip) + vmovdqu %ymm7, ymm_regs+224(%rip) + vmovdqu %ymm8, ymm_regs+256(%rip) + vmovdqu %ymm9, ymm_regs+288(%rip) + vmovdqu %ymm10, ymm_regs+320(%rip) + vmovdqu %ymm11, ymm_regs+352(%rip) + vmovdqu %ymm12, ymm_regs+384(%rip) + vmovdqu %ymm13, ymm_regs+416(%rip) + vmovdqu %ymm14, ymm_regs+448(%rip) + vmovdqu %ymm15, ymm_regs+480(%rip) jmp *callthis(%rip) .LFE3: .size snapshot, .-snapshot diff --git a/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h b/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h index 7f1f8f9fc5c..e66a27e9afd 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h +++ b/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h @@ -12,7 +12,7 @@ main () return 0; /* Run AVX test only if host has AVX support. */ - if (ecx & bit_AVX) + if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE)) { avx_test (); #ifdef DEBUG |