diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c index 9722f5e6118..d7ec2688e64 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c @@ -15,8 +15,8 @@ void f0 (void * in, void *out, uint64_t x, int n) { vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 4); - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 0, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 0, 4); __riscv_vse64_v_u64m1 (out + 2, v4, 4); } @@ -32,8 +32,8 @@ void f1 (void * in, void *out, uint64_t x, int n) { vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 4); - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 0, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 0, 4); __riscv_vse64_v_u64m1 (out + 2, v4, 4); } @@ -49,8 +49,8 @@ void f2 (void * in, void *out, uint64_t x, int n) { vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 4); - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 0, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 0, 4); __riscv_vse64_v_u64m1 (out + 2, v4, 4); } @@ -66,7 +66,7 @@ void f3 (void * in, void *out, uint64_t x, int n) { vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 4); - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 0, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 0, 4); __riscv_vse64_v_u64m1 (out + 2, v4, 4); } |