diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c index 463c90550d6..dcc4811f1d8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve_fnmla_1.c @@ -1,28 +1,29 @@ /* { dg-do assemble } */ /* { dg-options "-O3 -march=armv8-a+sve -msve-vector-bits=256 --save-temps" } */ +typedef _Float16 v16hf __attribute__((vector_size(32))); typedef float v8sf __attribute__((vector_size(32))); typedef double v4df __attribute__((vector_size(32))); -#define DO_OP(TYPE) \ -void vfnmla##TYPE (TYPE *_dst, TYPE _src1, TYPE _src2) \ -{ \ - register TYPE dst asm("z0"); \ - register TYPE src1 asm("z2"); \ - register TYPE src2 asm("z4"); \ - dst = *_dst; \ - asm volatile ("" :: "w" (dst)); \ - src1 = _src1; \ - asm volatile ("" :: "w" (src1)); \ - src2 = _src2; \ - asm volatile ("" :: "w" (src2)); \ - dst = (-dst) + (-src1 * src2); \ - asm volatile ("" :: "w" (dst)); \ - *_dst = dst; \ +#define DO_OP(TYPE) \ +void vmad##TYPE (TYPE *x, TYPE y, TYPE z) \ +{ \ + register TYPE dst asm("z0"); \ + register TYPE src1 asm("z2"); \ + register TYPE src2 asm("z4"); \ + dst = *x; \ + src1 = y; \ + src2 = z; \ + asm volatile ("" :: "w" (dst), "w" (src1), "w" (src2)); \ + dst = (-src1 * src2) - dst; \ + asm volatile ("" :: "w" (dst)); \ + *x = dst; \ } +DO_OP (v16hf) DO_OP (v8sf) DO_OP (v4df) -/* { dg-final { scan-assembler-times {\tfnmla\tz0.s, p[0-7]/m, z2.s, z4.s\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tfnmla\tz0.d, p[0-7]/m, z2.d, z4.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz0\.h, p[0-7]/m, z2\.h, z4\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz0\.s, p[0-7]/m, z2\.s, z4\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz0\.d, p[0-7]/m, z2\.d, z4\.d\n} 1 } } */ |