16 files changed, 26 insertions, 26 deletions
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
index 13dd264046c..151d7364aa0 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
@@ -410,7 +410,7 @@ vint8mf8_t var_10 = __riscv_vsra_vv_i8mf8_mu(var_53, var_11, var_13, var_54, 1);
 vint8mf8_t var_1 = __riscv_vmax_vx_i8mf8_mu(var_72, var_10, var_10, var_9, 1);
 // 5, 1
 
-vint8mf8_t var_0 = __riscv_vssra_vx_i8mf8(var_1, var_85, 1);
+vint8mf8_t var_0 = __riscv_vssra_vx_i8mf8(var_1, var_85, 0, 1);
 // 5
 
 vbool64_t var_2 = __riscv_vmsbc_vx_i8mf8_b64(var_0, var_3, 1);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
index 8c6ad12d729..ea992327202 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
@@ -335,7 +335,7 @@ vbool32_t var_14 = __riscv_vmseq_vv_u32m1_b32_mu(var_39, var_40, var_41, var_42,
 // 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e32m8(27);
-vint32m8_t var_0 = __riscv_vssub_vx_i32m8(var_59, var_1, 27);
+vint32m8_t var_0 = __riscv_vssub_vx_i32m8(var_59, var_1, 0, 27);
 // -1061068412, -1776580354, -100935733, 1111812123, 840849367, 1454689778, -1416961586, 286847306, 2118070565, 1965230406, -1040658036, 587048909, 1667471177, -1452995359, 1549864288, 1955648606, -1153689461, -105253108, 1792194502, -341148625, 630712685, -1367196047, 1561028022, -599776667, 1447136930, -480839967, -1960624419
 
 __riscv_vsetvl_e32m8(19);
@@ -359,7 +359,7 @@ __riscv_vse32_v_i32m8(var_70, var_4, 10);
 __riscv_vsetvl_e32m8(27);
 __riscv_vse32_v_i32m8(var_74, var_10, 27);
 __riscv_vsetvl_e32m8(19);
-vint32m8_t var_2 = __riscv_vaadd_vx_i32m8_mu(var_8, var_0, var_57, var_11, 19);
+vint32m8_t var_2 = __riscv_vaadd_vx_i32m8_mu(var_8, var_0, var_57, var_11, 0, 19);
 // 359557953, 197431454, 20431512, -1122683440, 434907211, -719883824, 37657602, -782537125, -106566459, -1084448745, -945878036, -626712270, 778335544, -755412905, -574020956, -1028523912, 458052219, -1166885074, 732449389, -341148625, 630712685, -1367196047, 1561028022, -599776667, 1447136930, -480839967, -1960624419
 
 if(!check(var_70, var_114, var_115)) {cerr << "check 113 fails" << endl; return_value = 1;}
@@ -372,7 +372,7 @@ vint32m1_t var_6 = __riscv_vredmin_vs_i32m8_i32m1_tu(var_18, var_2, var_18, 3);
 // 20431512
 
 __riscv_vsetvl_e32m8(10);
-vint32m8_t var_9 = __riscv_vasub_vv_i32m8(var_2, var_53, 10);
+vint32m8_t var_9 = __riscv_vasub_vv_i32m8(var_2, var_53, 0, 10);
 // 679936144, 129579879, -377657770, -304070536, 173758693, 371969755, -994446215, -471795897, 314947602, 489622156
 
 __riscv_vsetvl_e32m8(19);
@@ -394,7 +394,7 @@ vint32m1_t var_12 = __riscv_vredxor_vs_i32m2_i32m1_tum(var_46, var_7, var_47, va
 // 611390260
 
 __riscv_vsetvl_e32m8(10);
-vint32m8_t var_19 = __riscv_vssra_vv_i32m8_mu(var_13, var_20, var_21, var_22, 10);
+vint32m8_t var_19 = __riscv_vssra_vv_i32m8_mu(var_13, var_20, var_21, var_22, 0, 10);
 // -816540887, 1074541498, -1467236483, -23091331, -38787, 1943479342, 1158929439, 360172, -218, 2034278775
 
 if(!check(var_85, var_105, var_106)) {cerr << "check 104 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
index d5e78d2922f..d833d4d80c5 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
@@ -382,7 +382,7 @@ vuint16m2_t var_18 = __riscv_vwmulu_vv_u16m2_mu(var_24, var_25, var_26, var_27,
 if(!check(var_91, var_142, var_143)) {cerr << "check 141 fails" << endl; return_value = 1;}
 if(!check(var_90, var_139, var_140)) {cerr << "check 138 fails" << endl; return_value = 1;}
 __riscv_vsetvl_e64m1(2);
-vuint64m1_t var_7 = __riscv_vasubu_vx_u64m1(var_42, var_15, 2);
+vuint64m1_t var_7 = __riscv_vasubu_vx_u64m1(var_42, var_15, 0, 2);
 // 13578039560782071336, 1484621602351210644
 
 if(!check(var_94, var_136, var_137)) {cerr << "check 135 fails" << endl; return_value = 1;}
@@ -415,7 +415,7 @@ int32_t var_9 = __riscv_vmv_x_s_i32m4_i32(var_10);
 // 0
 
 __riscv_vsetvl_e32mf2(2);
-vint32mf2_t var_2 = __riscv_vsadd_vx_i32mf2_mu(var_47, var_48, var_49, var_9, 2);
+vint32mf2_t var_2 = __riscv_vsadd_vx_i32mf2_mu(var_47, var_48, var_49, var_9, 0, 2);
 // 470559939, 1961139923
 
 __riscv_vsuxei64_v_i32mf2(var_115, var_112, var_2, 2);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
index 193b6feddb1..627aa9290f9 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
@@ -341,7 +341,7 @@ vuint32m4_t var_6 = __riscv_vmv_s_x_u32m4_tu(var_0, var_58, 10);
 // 1207313030, 3014603841, 234827873, 3591973177, 774620885, 1394372191, 643827065, 4045083863, 1674932769, 2206939407, 1193735501, 1704965662, 3397690693, 3455432162, 2782347083
 
 __riscv_vsetvl_e8m1(15);
-vuint8m1_t var_16 = __riscv_vnclipu_wx_u8m1_mu(var_25, var_26, var_1, var_56, 15);
+vuint8m1_t var_16 = __riscv_vnclipu_wx_u8m1_mu(var_25, var_26, var_1, var_56, 0, 15);
 // 143, 148, 202, 255, 188, 255, 0, 255, 6, 180, 211, 220, 74, 255, 255
 
 __riscv_vsetvl_e16m2(3);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
index c19d6062483..d90d2d4dc01 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
@@ -351,7 +351,7 @@ vbool1_t var_66 = __riscv_vmseq_vx_i8m8_b1(var_68, var_69, 98);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e8mf2(8);
-vuint8mf2_t var_19 = __riscv_vasubu_vx_u8mf2_tumu(var_20, var_21, var_22, var_75, 8);
+vuint8mf2_t var_19 = __riscv_vasubu_vx_u8mf2_tumu(var_20, var_21, var_22, var_75, 0, 8);
 // 197, 206, 42, 228, 104, 250, 255, 186
 
 vbool16_t var_18 = __riscv_vmfle_vv_f64m4_b16_mu(var_24, var_25, var_26, var_27, 8);
@@ -395,11 +395,11 @@ __riscv_vsetvl_e8m8(120);
 vint8m8_t var_1 = __riscv_vxor_vv_i8m8_tumu(var_11, var_0, var_2, var_2, 120);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
-vuint8m8_t var_8 = __riscv_vasubu_vx_u8m8(var_59, var_13, 120);
+vuint8m8_t var_8 = __riscv_vasubu_vx_u8m8(var_59, var_13, 0, 120);
 // 218, 246, 239, 246, 238, 166, 19, 14, 242, 1, 241, 218, 249, 179, 214, 204, 166, 219, 245, 179, 179, 4, 224, 178, 202, 253, 206, 163, 230, 251, 213, 25, 19, 195, 239, 168, 239, 17, 239, 205, 173, 251, 241, 202, 219, 223, 17, 162, 3, 6, 13, 17, 170, 229, 178, 246, 180, 249, 195, 250, 241, 229, 20, 249, 19, 174, 198, 221, 200, 11, 177, 160, 180, 216, 11, 19, 163, 17, 209, 174, 1, 9, 208, 241, 169, 190, 176, 19, 187, 198, 213, 208, 22, 4, 237, 180, 0, 188, 204, 203, 173, 188, 28, 180, 162, 218, 227, 160, 230, 214, 177, 172, 255, 15, 207, 199, 20, 165, 180, 206
 
 __riscv_vsetvl_e8m8(31);
-vint8m8_t var_17 = __riscv_vssra_vx_i8m8_tumu(var_31, var_12, var_32, var_76, 31);
+vint8m8_t var_17 = __riscv_vssra_vx_i8m8_tumu(var_31, var_12, var_32, var_76, 0, 31);
 // 41, 69, -57, 102, 86, 103, -128, 4, -118, -1, 109, 40, 7, 27, 79, -63, 35, 73, 1, 42, -85, 126, 107, 53, -114, 39, 53, 10, -94, -20, 125, -46, -52, 94, 14, -74, -97, 25, -59, 3, 68, -15, -60, 83, 80, -113, -90, -118, 7, -38, -57, -114, 88, -76, 8, 44, 45, 12, -27, 83, 43, 77, -93, 79, 6, -17, 93, 33, 22, 6, 113, -5, -13, 20, -106, -36, -57, -21, -127, -89, 102, -62, -92, -124, 73, 118, 41, -120, 94, -100, 13, -34, -86, -103, 26, -57, -16, 22, -48, -71, 15, 40, 27, -125, -94, -93, -93, -3, -33, 60, 15, -29, -16, 70, -15, 30, 108, -105, 30, -65
 
 __riscv_vsetvl_e8m8(98);
@@ -407,7 +407,7 @@ vbool1_t var_6 = __riscv_vmseq_vv_i8m8_b1(var_5, var_10, 98);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e8m8(120);
-vint8m8_t var_4 = __riscv_vssra_vv_i8m8_tumu(var_63, var_1, var_10, var_8, 120);
+vint8m8_t var_4 = __riscv_vssra_vv_i8m8_tumu(var_63, var_1, var_10, var_8, 0, 120);
 // 15, -2, 0, 0, -1, 0, 0, -2, 18, 0, 1, 0, 2, 10, 2, 0, 0, -9, 0, 0, 0, 0, 1, 0, 31, 2, 0, -5, 0, 3, -2, -17, -12, 0, 0, -1, 1, 47, -1, 0, 0, -1, 33, 0, 0, 1, 0, 0, -10, 0, 0, 61, 18, -3, 0, -1, 0, 0, 0, 14, 0, 3, 0, 0, 0, 0, 0, 0, -59, 0, 0, 55, 0, 11, 14, 0, 0, 0, 1, 0, 0, 0, -1, 17, 0, 2, 0, 0, -5, -1, 1, 0, 1, 6, 0, 0, 107, 0, 7, 0, 0, 0, 5, 7, 0, 0, 0, -1, 0, 0, -8, 0, 0, 0, -1, 0, -8, 1, 0, 0
 
 __riscv_vsetvl_e8m8(31);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C
index cdd3cc3e0b8..c29d6379ab5 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C
@@ -375,7 +375,7 @@ vuint16m1_t var_8 = __riscv_vor_vv_u16m1_tumu(var_1, var_43, var_44, var_45, 1);
 vfloat32m2_t var_12 = __riscv_vfdiv_vv_f32m2_tumu(var_1, var_16, var_16, var_18, 1);
 // 4.841275101341818e-29, 4.841275101341818e-29, 4.841275101341818e-29, 4.841275101341818e-29, 4.841275101341818e-29
 
-vint8mf2_t var_19 = __riscv_vaadd_vv_i8mf2_tumu(var_1, var_20, var_21, var_22, 1);
+vint8mf2_t var_19 = __riscv_vaadd_vv_i8mf2_tumu(var_1, var_20, var_21, var_22, 0, 1);
 // -108, 37, -34
 
 __riscv_vse8_v_i8mf2(var_66, var_6, 1);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
index 868ec1ef90f..71dec9f21c8 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
@@ -121,7 +121,7 @@ asm volatile ("ttt":::"memory");
   if (check(k, ab, aa))
     cerr << "check 8 fails" << endl;
   vbool64_t var_2 = __riscv_vmsne_vx_u32mf2_b64_mu(var_55, var_56, var_3, au, 2);
-  vint16mf4_t var_1 = __riscv_vssub_vv_i16mf4_mu(var_2, var_0, var_4, cg, 2);
+  vint16mf4_t var_1 = __riscv_vssub_vv_i16mf4_mu(var_2, var_0, var_4, cg, 0, 2);
   vint16mf4_t var_5 = __riscv_vxor_vv_i16mf4_mu(var_46, var_1, bw, bx, 2);
   vint32mf2_t var_18 = __riscv_vwmaccsu_vv_i32mf2(bf, var_1, bg, 2);
   vint8mf8_t var_6 = __riscv_vncvt_x_x_w_i8mf8_mu(var_8, var_7, var_5, 1);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
index a6ba9580416..fc5e09b89fc 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
@@ -131,7 +131,7 @@
  vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58, var_0, var_59, 1);
  __riscv_vse64_v_i64m8(var_74, var_3, 2);
  vuint64m8_t var_10 = __riscv_vmadd_vv_u64m8_mu(var_13, var_6, var_51, var_52, 13);
- vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 13);
+ vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 0, 13);
  vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55, var_56, 1);
  vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8, var_47, var_48, 1);
  if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
index 2a8591f1d3e..81d0cd74465 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
@@ -131,7 +131,7 @@
  vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58, var_0, var_59, 1);
  __riscv_vse64_v_i64m8(var_74, var_3, 2);
  vuint64m8_t var_10 = __riscv_vmacc_vv_u64m8_mu(var_13, var_6, var_51, var_52, 13);
- vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 13);
+ vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 0, 13);
  vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55, var_56, 1);
  vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8, var_47, var_48, 1);
  if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
index 77e06bf1f10..5c6e8283c48 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
@@ -131,7 +131,7 @@
  vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58, var_0, var_59, 1);
  __riscv_vse64_v_i64m8(var_74, var_3, 2);
  vuint64m8_t var_10 = __riscv_vnmsub_vv_u64m8_mu(var_13, var_6, var_51, var_52, 13);
- vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 13);
+ vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 0, 13);
  vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55, var_56, 1);
  vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8, var_47, var_48, 1);
  if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
index 8ba18a02b83..aaacb320e0a 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
@@ -131,7 +131,7 @@
  vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58, var_0, var_59, 1);
  __riscv_vse64_v_i64m8(var_74, var_3, 2);
  vuint64m8_t var_10 = __riscv_vnmsac_vv_u64m8_mu(var_13, var_6, var_51, var_52, 13);
- vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 13);
+ vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34, var_35, 0, 13);
  vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55, var_56, 1);
  vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8, var_47, var_48, 1);
  if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
index 061063bf44d..d750a77bd77 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
@@ -354,7 +354,7 @@ vbool64_t var_63 = __riscv_vmseq_vx_u8mf8_b64(var_69, var_70, 2);
 vuint8mf8_t var_19 = __riscv_vsub_vx_u8mf8_tumu(var_20, var_21, var_22, var_73, 2);
 // 225, 96
 
-vuint32mf2_t var_16 = __riscv_vssubu_vx_u32mf2_tumu(var_33, var_34, var_35, var_74, 2);
+vuint32mf2_t var_16 = __riscv_vssubu_vx_u32mf2_tumu(var_33, var_34, var_35, var_74, 0, 2);
 // 3077557042, 4186139873
 
 __riscv_vsetvl_e64m4(2);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
index 814a6084ecd..1c7e0181f4a 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
@@ -309,7 +309,7 @@ __riscv_vsetvl_e32m2(8);
 vbool16_t var_49 = __riscv_vmseq_vv_i32m2_b16(var_50, var_51, 8);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
-vint16m1_t var_13 = __riscv_vsadd_vx_i16m1(var_0, var_60, 8);
+vint16m1_t var_13 = __riscv_vsadd_vx_i16m1(var_0, var_60, 0, 8);
 // -9364, 32767, 11538, -10536, 32767, 30906, 30906, 4977
 
 __riscv_vsetvl_e16m8(7);
@@ -328,7 +328,7 @@ vuint32m2_t var_12 = __riscv_vfcvt_rtz_xu_f_v_u32m2_mu(var_35, var_36, var_37, 8
 
 __riscv_vse16_v_i16m1(var_79, var_13, 8);
 __riscv_vsetvl_e16m8(7);
-vint16m8_t var_9 = __riscv_vaadd_vx_i16m8_mu(var_15, var_43, var_44, var_63, 7);
+vint16m8_t var_9 = __riscv_vaadd_vx_i16m8_mu(var_15, var_43, var_44, var_63, 0, 7);
 // -6442, 2757, 1437, -18340, -12668, -27551, 29648
 
 __riscv_vsetvl_e32m2(8);
@@ -347,7 +347,7 @@ vint16m8_t var_4 = __riscv_vmerge_vxm_i16m8(var_48, var_8, var_11, 7);
 // -6442, -6442, -6442, -6442, -6442, -6442, -6442
 
 __riscv_vsetvl_e16m1(1);
-vint16m1_t var_6 = __riscv_vaadd_vx_i16m1(var_14, var_8, 1);
+vint16m1_t var_6 = __riscv_vaadd_vx_i16m1(var_14, var_8, 0, 1);
 // -6554
 
 if(!check(var_96, var_107, var_108)) {cerr << "check 106 fails" << endl; return_value = 1;}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C
index 591fda5762b..caa826a5587 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C
@@ -304,7 +304,7 @@ vuint8mf8_t var_59 = __riscv_vle8_v_u8mf8(var_66, 1);
 // 54
 
 __riscv_vsetvl_e8mf8(2);
-vint8mf8_t var_19 = __riscv_vsmul_vx_i8mf8(var_20, var_63, 2);
+vint8mf8_t var_19 = __riscv_vsmul_vx_i8mf8(var_20, var_63, 0,2);
 // 79, 28
 
 __riscv_vsetvl_e16mf2(2);
@@ -358,7 +358,7 @@ vbool64_t var_0 = __riscv_vmsne_vx_i16mf4_b64(var_9, var_16, 2);
 // 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e8mf8(1);
-vuint8mf8_t var_1 = __riscv_vnclipu_wx_u8mf8_mu(var_0, var_59, var_2, var_65, 1);
+vuint8mf8_t var_1 = __riscv_vnclipu_wx_u8mf8_mu(var_0, var_59, var_2, var_65, 0, 1);
 // 255
 
 __riscv_vsetvl_e8mf8(2);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C
index 2dc05ab9211..ec6e2903884 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C
@@ -292,7 +292,7 @@ vint8m8_t var_10 = __riscv_vmulh_vv_i8m8(var_11, var_38, 45);
 // -9, -3, 9, -3, 3, -35, 5, 3, 0, 17, -1, -10, 6, -10, 21, -18, 37, 24, 15, -8, -29, 18, 0, -7, -6, -2, -46, 44, 3, -5, -6, -9, 21, -3, -42, -9, 9, -12, -2, -18, 7, 4, -1, -1, 39
 
 if(!check(var_62, var_80, var_81)) {cerr << "check 79 fails" << endl; return_value = 1;}
-vint8m8_t var_8 = __riscv_vasub_vx_i8m8(var_10, var_12, 45);
+vint8m8_t var_8 = __riscv_vasub_vx_i8m8(var_10, var_12, 0, 45);
 // -32, -29, -23, -29, -26, -45, -25, -26, -28, -19, -28, -33, -25, -33, -17, -37, -9, -16, -20, -32, -42, -19, -28, -31, -31, -29, -51, -6, -26, -30, -31, -32, -17, -29, -49, -32, -23, -34, -29, -37, -24, -26, -28, -28, -8
 
 __riscv_vse8_v_i8m8_m(var_15, var_63, var_8, 45);
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
index 7e1d6dbac7c..97459c6b666 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
@@ -379,7 +379,7 @@ if(!check(var_87, var_122, var_123)) {cerr << "check 121 fails" << endl; return_
 vint8m4_t var_5 = __riscv_vnsra_wv_i8m4(var_12, var_48, 43);
 // 0, -2, -5, -7, 0, -3, -1, -1, 0, 0, -5, -90, -1, 0, -15, -1, 0, 0, 0, 0, 0, 0, -3, -1, -3, 0, 0, -13, 0, -1, -1, -1, 0, -1, 39, 0, 0, -2, 0, 0, -24, -45, 1
 
-vint16m8_t var_4 = __riscv_vssub_vx_i16m8_mu(var_6, var_12, var_49, var_10, 43);
+vint16m8_t var_4 = __riscv_vssub_vx_i16m8_mu(var_6, var_12, var_49, var_10, 0, 43);
 // -27921, -25052, -17, -20337, 15054, 1382, -12, -16, 16159, -32768, 17832, -12646, 16746, 20, -15, -16, 4, 7798, 14967, 3, -29916, 11, -6168, -32768, 14361, -14023, -32768, -12646, 10, -12646, 18748, -12646, 8473, -32768, -32768, 16, -32768, -14720, -11479, 6985, -24591, -28243, 11
 
 __riscv_vsetvl_e16m8(16);