diff options
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/contrib.texi | 2 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 240 | ||||
| -rw-r--r-- | gcc/doc/install.texi | 12 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 208 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 222 | ||||
| -rw-r--r-- | gcc/doc/tm.texi | 8 | ||||
| -rw-r--r-- | gcc/doc/tm.texi.in | 8 |
7 files changed, 684 insertions, 16 deletions
diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index 939f6dea1dd..f76cce8d234 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -746,7 +746,7 @@ Volker Reichelt for keeping up with the problem reports. @item Joern Rennecke for maintaining the sh port, loop, regmove & reload -hacking. +hacking and developing and maintaining the Epiphany port. @item Loren J. Rittle for improvements to libstdc++-v3 including the FreeBSD diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 7c773882423..c7e8ede9cb0 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -79,7 +79,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Return Address:: Getting the return or frame address of a function. * Vector Extensions:: Using vector instructions through built-in functions. * Offsetof:: Special syntax for implementing @code{offsetof}. -* Atomic Builtins:: Built-in functions for atomic memory access. +* __sync Builtins:: Legacy built-in functions for atomic memory access. +* __atomic Builtins:: Atomic built-in functions with memory model. * Object Size Checking:: Built-in functions for limited buffer overflow checking. * Other Builtins:: Other built-in functions. @@ -2192,7 +2193,7 @@ types (@pxref{Variable Attributes}, @pxref{Type Attributes}.) @item disinterrupt @cindex @code{disinterrupt} attribute -On MeP targets, this attribute causes the compiler to emit +On Epiphany and MeP targets, this attribute causes the compiler to emit instructions to disable interrupts for the duration of the given function. @@ -2551,7 +2552,7 @@ This attribute is ignored for R8C target. @item interrupt @cindex interrupt handler functions -Use this attribute on the ARM, AVR, M32C, M32R/D, m68k, MeP, MIPS, +Use this attribute on the ARM, AVR, Epiphany, M32C, M32R/D, m68k, MeP, MIPS, RX and Xstormy16 ports to indicate that the specified function is an interrupt handler. The compiler will generate function entry and exit sequences suitable for use in an interrupt handler when this attribute @@ -2723,7 +2724,8 @@ attribute is not allowed on types to annotate indirect calls. @item long_call/short_call @cindex indirect calls on ARM This attribute specifies how a particular function is called on -ARM@. Both attributes override the @option{-mlong-calls} (@pxref{ARM Options}) +ARM and Epiphany. Both attributes override the +@option{-mlong-calls} (@pxref{ARM Options}) command-line switch and @code{#pragma long_calls} settings. The @code{long_call} attribute indicates that the function might be far away from the call site and require a different (more expensive) @@ -6682,8 +6684,8 @@ is a suitable definition of the @code{offsetof} macro. In C++, @var{type} may be dependent. In either case, @var{member} may consist of a single identifier, or a sequence of member accesses and array references. -@node Atomic Builtins -@section Built-in functions for atomic memory access +@node __sync Builtins +@section Legacy __sync built-in functions for atomic memory access The following builtins are intended to be compatible with those described in the @cite{Intel Itanium Processor-specific Application Binary Interface}, @@ -6815,6 +6817,232 @@ previous memory loads have been satisfied, but following memory reads are not prevented from being speculated to before the barrier. @end table +@node __atomic Builtins +@section Built-in functions for memory model aware atomic operations + +The following built-in functions approximately match the requirements for +C++11 memory model. Many are similar to the @samp{__sync} prefixed built-in +functions, but all also have a memory model parameter. These are all +identified by being prefixed with @samp{__atomic}, and most are overloaded +such that they work with multiple types. + +GCC will allow any integral scalar or pointer type that is 1, 2, 4, or 8 +bytes in length. 16-byte integral types are also allowed if +@samp{__int128} (@pxref{__int128}) is supported by the architecture. + +Target architectures are encouraged to provide their own patterns for +each of these built-in functions. If no target is provided, the original +non-memory model set of @samp{__sync} atomic built-in functions will be +utilized, along with any required synchronization fences surrounding it in +order to achieve the proper behaviour. Execution in this case is subject +to the same restrictions as those built-in functions. + +If there is no pattern or mechanism to provide a lock free instruction +sequence, a call is made to an external routine with the same parameters +to be resolved at runtime. + +The four non-arithmetic functions (load, store, exchange, and +compare_exchange) all have a generic version as well. This generic +version will work on any data type. If the data type size maps to one +of the integral sizes which may have lock free support, the generic +version will utilize the lock free built-in function. Otherwise an +external call is left to be resolved at runtime. This external call will +be the same format with the addition of a @samp{size_t} parameter inserted +as the first parameter indicating the size of the object being pointed to. +All objects must be the same size. + +There are 6 different memory models which can be specified. These map +to the same names in the C++11 standard. Refer there or to the +@uref{http://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync,GCC wiki on +atomic synchronization} for more detailed definitions. These memory +models integrate both barriers to code motion as well as synchronization +requirements with other threads. These are listed in approximately +ascending order of strength. + +@table @code +@item __ATOMIC_RELAXED +No barriers or synchronization. +@item __ATOMIC_CONSUME +Data dependency only for both barrier and synchronization with another +thread. +@item __ATOMIC_ACQUIRE +Barrier to hoisting of code and synchronizes with release (or stronger) +semantic stores from another thread. +@item __ATOMIC_RELEASE +Barrier to sinking of code and synchronizes with acquire (or stronger) +semantic loads from another thread. +@item __ATOMIC_ACQ_REL +Full barrier in both directions and synchronizes with acquire loads and +release stores in another thread. +@item __ATOMIC_SEQ_CST +Full barrier in both directions and synchronizes with acquire loads and +release stores in all threads. +@end table + +When implementing patterns for these built-in functions , the memory model +parameter can be ignored as long as the pattern implements the most +restrictive @code{__ATOMIC_SEQ_CST} model. Any of the other memory models +will execute correctly with this memory model but they may not execute as +efficiently as they could with a more appropriate implemention of the +relaxed requirements. + +Note that the C++11 standard allows for the memory model parameter to be +determined at runtime rather than at compile time. These built-in +functions will map any runtime value to @code{__ATOMIC_SEQ_CST} rather +than invoke a runtime library call or inline a switch statement. This is +standard compliant, safe, and the simplest approach for now. + +@deftypefn {Built-in Function} @var{type} __atomic_load_n (@var{type} *ptr, int memmodel) +This built-in function implements an atomic load operation. It returns the +contents of @code{*@var{ptr}}. + +The valid memory model variants are +@code{__ATOMIC_RELAXED}, @code{__ATOMIC_SEQ_CST}, @code{__ATOMIC_ACQUIRE}, +and @code{__ATOMIC_CONSUME}. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_load (@var{type} *ptr, @var{type} *ret, int memmodel) +This is the generic version of an atomic load. It will return the +contents of @code{*@var{ptr}} in @code{*@var{ret}}. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_store_n (@var{type} *ptr, @var{type} val, int memmodel) +This built-in function implements an atomic store operation. It writes +@code{@var{val}} into @code{*@var{ptr}}. + +The valid memory model variants are +@code{__ATOMIC_RELAXED}, @code{__ATOMIC_SEQ_CST}, and @code{__ATOMIC_RELEASE}. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_store (@var{type} *ptr, @var{type} *val, int memmodel) +This is the generic version of an atomic store. It will store the value +of @code{*@var{val}} into @code{*@var{ptr}}. + +@end deftypefn + +@deftypefn {Built-in Function} @var{type} __atomic_exchange_n (@var{type} *ptr, @var{type} val, int memmodel) +This built-in function implements an atomic exchange operation. It writes +@var{val} into @code{*@var{ptr}}, and returns the previous contents of +@code{*@var{ptr}}. + +The valid memory model variants are +@code{__ATOMIC_RELAXED}, @code{__ATOMIC_SEQ_CST}, @code{__ATOMIC_ACQUIRE}, +@code{__ATOMIC_RELEASE}, and @code{__ATOMIC_ACQ_REL}. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_exchange (@var{type} *ptr, @var{type} *val, @var{type} *ret, int memmodel) +This is the generic version of an atomic exchange. It will store the +contents of @code{*@var{val}} into @code{*@var{ptr}}. The original value +of @code{*@var{ptr}} will be copied into @code{*@var{ret}}. + +@end deftypefn + +@deftypefn {Built-in Function} bool __atomic_compare_exchange_n (@var{type} *ptr, @var{type} *expected, @var{type} desired, bool weak, int success_memmodel, int failure_memmodel) +This built-in function implements an atomic compare and exchange operation. +This compares the contents of @code{*@var{ptr}} with the contents of +@code{*@var{expected}} and if equal, writes @var{desired} into +@code{*@var{ptr}}. If they are not equal, the current contents of +@code{*@var{ptr}} is written into @code{*@var{expected}}. + +True is returned if @code{*@var{desired}} is written into +@code{*@var{ptr}} and the execution is considered to conform to the +memory model specified by @var{success_memmodel}. There are no +restrictions on what memory model can be used here. + +False is returned otherwise, and the execution is considered to conform +to @var{failure_memmodel}. This memory model cannot be +@code{__ATOMIC_RELEASE} nor @code{__ATOMIC_ACQ_REL}. It also cannot be a +stronger model than that specified by @var{success_memmodel}. + +@end deftypefn + +@deftypefn {Built-in Function} bool __atomic_compare_exchange (@var{type} *ptr, @var{type} *expected, @var{type} *desired, bool weak, int success_memmodel, int failure_memmodel) +This built-in function implements the generic version of +@code{__atomic_compare_exchange}. The function is virtually identical to +@code{__atomic_compare_exchange_n}, except the desired value is also a +pointer. + +@end deftypefn + +@deftypefn {Built-in Function} @var{type} __atomic_add_fetch (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_sub_fetch (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_and_fetch (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_xor_fetch (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_or_fetch (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_nand_fetch (@var{type} *ptr, @var{type} val, int memmodel) +These built-in functions perform the operation suggested by the name, and +return the result of the operation. That is, + +@smallexample +@{ *ptr @var{op}= val; return *ptr; @} +@end smallexample + +All memory models are valid. + +@end deftypefn + +@deftypefn {Built-in Function} @var{type} __atomic_fetch_add (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_fetch_sub (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_fetch_and (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_fetch_xor (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_fetch_or (@var{type} *ptr, @var{type} val, int memmodel) +@deftypefnx {Built-in Function} @var{type} __atomic_fetch_nand (@var{type} *ptr, @var{type} val, int memmodel) +These built-in functions perform the operation suggested by the name, and +return the value that had previously been in @code{*@var{ptr}}. That is, + +@smallexample +@{ tmp = *ptr; *ptr @var{op}= val; return tmp; @} +@end smallexample + +All memory models are valid. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_thread_fence (int memmodel) + +This built-in function acts as a synchronization fence between threads +based on the specified memory model. + +All memory orders are valid. + +@end deftypefn + +@deftypefn {Built-in Function} void __atomic_signal_fence (int memmodel) + +This built-in function acts as a synchronization fence between a thread +and signal handlers based in the same thread. + +All memory orders are valid. + +@end deftypefn + +@deftypefn {Built-in Function} bool __atomic_always_lock_free (size_t size) + +This built-in function returns true if objects of size bytes will always +generate lock free atomic instructions for the target architecture. +Otherwise false is returned. + +size must resolve to a compile time constant. + +@smallexample +if (_atomic_always_lock_free (sizeof (long long))) +@end smallexample + +@end deftypefn + +@deftypefn {Built-in Function} bool __atomic_is_lock_free (size_t size) + +This built-in function returns true if objects of size bytes will always +generate lock free atomic instructions for the target architecture. If +it is not known to be lock free a call is made to a runtime routine named +@code{__atomic_is_lock_free}. + +@end deftypefn + @node Object Size Checking @section Object Size Checking Builtins @findex __builtin_object_size diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 730f82baff8..643ba7208e6 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1208,6 +1208,11 @@ of the arguments depend on the target. Specify if the compiler should default to @option{-marm} or @option{-mthumb}. This option is only supported on ARM targets. +@item --with-stack-offset=@var{num} +This option sets the default for the -mstack-offset=@var{num} option, +and will thus generally also control the setting of this option for +libraries. This option is only supported on Epiphany targets. + @item --with-fpmath=@var{isa} This options sets @option{-mfpmath=sse} by default and specifies the default ISA for floating-point arithmetics. You can select either @samp{sse} which @@ -3315,6 +3320,13 @@ and includes all the necessary compilation tools and libraries. @html <hr /> @end html +@heading @anchor{epiphany-x-elf}epiphany-*-elf +Adapteva Epiphany. +This configuration is intended for embedded systems. + +@html +<hr /> +@end html @heading @anchor{x-x-freebsd}*-*-freebsd* Support for FreeBSD 1 was discontinued in GCC 3.2. Support for diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 47b49bf5c6b..3a5a3414cd9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -458,6 +458,14 @@ Objective-C and Objective-C++ Dialects}. @c Try and put the significant identifier (CPU or system) first, @c so users have a clue at guessing where the ones they want will be. +@emph{Adapteva Epiphany Options} +@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol +-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol +-msplit-lohi -mpost-inc -mpost-modify -mstack-offset=@var{num} @gol +-mround-nearest -mlong-calls -mshort-calls -msmall16 @gol +-mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol +-msplit-vecmove-early -m1reg-@var{reg}} + @emph{ARM Options} @gccoptlist{-mapcs-frame -mno-apcs-frame @gol -mabi=@var{name} @gol @@ -2376,17 +2384,22 @@ an instance of a derived class through a pointer to a base class if the base class does not have a virtual destructor. This warning is enabled by @option{-Wall}. -@item -Wno-narrowing @r{(C++ and Objective-C++ only)} +@item -Wnarrowing @r{(C++ and Objective-C++ only)} @opindex Wnarrowing @opindex Wno-narrowing -With -std=c++11, suppress the diagnostic required by the standard for -narrowing conversions within @samp{@{ @}}, e.g. +Warn when a narrowing conversion prohibited by C++11 occurs within +@samp{@{ @}}, e.g. @smallexample int i = @{ 2.2 @}; // error: narrowing from double to int @end smallexample -This flag can be useful for compiling valid C++98 code in C++11 mode. +This flag is included in @option{-Wall} and @option{-Wc++11-compat}. + +With -std=c++11, @option{-Wno-narrowing} suppresses the diagnostic +required by the standard. Note that this does not affect the meaning +of well-formed code; narrowing conversions are still considered +ill-formed in SFINAE context. @item -Wnoexcept @r{(C++ and Objective-C++ only)} @opindex Wnoexcept @@ -4075,9 +4088,10 @@ ISO C and ISO C++, e.g.@: request for implicit conversion from @code{void *} to a pointer to non-@code{void} type. @item -Wc++11-compat @r{(C++ and Objective-C++ only)} -Warn about C++ constructs whose meaning differs between ISO C++ 1998 and -ISO C++ 2011, e.g., identifiers in ISO C++ 1998 that will become keywords -in ISO C++ 2011. This warning is enabled by @option{-Wall}. +Warn about C++ constructs whose meaning differs between ISO C++ 1998 +and ISO C++ 2011, e.g., identifiers in ISO C++ 1998 that are keywords +in ISO C++ 2011. This warning turns on @option{-Wnarrowing} and is +enabled by @option{-Wall}. @item -Wcast-qual @opindex Wcast-qual @@ -4155,6 +4169,12 @@ unsigned integers are disabled by default in C++ unless Do not warn for conversions between @code{NULL} and non-pointer types. @option{-Wconversion-null} is enabled by default. +@item -Wzero-as-null-pointer-constant @r{(C++ and Objective-C++ only)} +@opindex Wzero-as-null-pointer-constant +@opindex Wno-zero-as-null-pointer-constant +Warn when a literal '0' is used as null pointer constant. This can +be useful to facilitate the conversion to @code{nullptr} in C++11. + @item -Wempty-body @opindex Wempty-body @opindex Wno-empty-body @@ -9163,11 +9183,26 @@ The maximum number of conditional stores paires that can be sunk. Set to 0 if either vectorization (@option{-ftree-vectorize}) or if-conversion (@option{-ftree-loop-if-convert}) is disabled. The default is 2. +@item allow-load-data-races +Allow optimizers to introduce new data races on loads. +Set to 1 to allow, otherwise to 0. This option is enabled by default +unless implicitly set by the @option{-fmemory-model=} option. + @item allow-store-data-races Allow optimizers to introduce new data races on stores. Set to 1 to allow, otherwise to 0. This option is enabled by default unless implicitly set by the @option{-fmemory-model=} option. +@item allow-packed-load-data-races +Allow optimizers to introduce new data races on packed data loads. +Set to 1 to allow, otherwise to 0. This option is enabled by default +unless implicitly set by the @option{-fmemory-model=} option. + +@item allow-packed-store-data-races +Allow optimizers to introduce new data races on packed data stores. +Set to 1 to allow, otherwise to 0. This option is enabled by default +unless implicitly set by the @option{-fmemory-model=} option. + @item case-values-threshold The smallest number of different values for which it is best to use a jump-table instead of a tree of conditional branches. If the value is @@ -10234,6 +10269,7 @@ platform. @c in Machine Dependent Options @menu +* Adapteva Epiphany Options:: * ARM Options:: * AVR Options:: * Blackfin Options:: @@ -10282,6 +10318,161 @@ platform. * zSeries Options:: @end menu +@node Adapteva Epiphany Options +@subsection Adapteva Epiphany Options + +These @samp{-m} options are defined for Adapteva Epiphany: + +@table @gcctabopt +@item -mhalf-reg-file +@opindex mhalf-reg-file +Don't allocate any register in the range @code{r32}@dots{}@code{r63}. +That allows code to run on hardware variants that lack these registers. + +@item -mprefer-short-insn-regs +@opindex mprefer-short-insn-regs +Preferrentially allocate registers that allow short instruction generation. +This can result in increasesd instruction count, so if this reduces or +increases code size might vary from case to case. + +@item -mbranch-cost=@var{num} +@opindex mbranch-cost +Set the cost of branches to roughly @var{num} ``simple'' instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. + +@item -mcmove +@opindex mcmove +Enable the generation of conditional moves. + +@item -mnops=@var{num} +@opindex mnops +Emit @var{num} nops before every other generated instruction. + +@item -mno-soft-cmpsf +@opindex mno-soft-cmpsf +For single-precision floating point comparisons, emit an fsub instruction +and test the flags. This is faster than a software comparison, but can +get incorrect results in the presence of NaNs, or when two different small +numbers are compared such that their difference is calculated as zero. +The default is @option{-msoft-cmpsf}, which uses slower, but IEEE-compliant, +software comparisons. + +@item -mstack-offset=@var{num} +@opindex mstack-offset +Set the offset between the top of the stack and the stack pointer. +E.g., a value of 8 means that the eight bytes in the range sp+0@dots{}sp+7 +can be used by leaf functions without stack allocation. +Values other than @samp{8} or @samp{16} are untested and unlikely to work. +Note also that this option changes the ABI, compiling a program with a +different stack offset than the libraries have been compiled with +will generally not work. +This option can be useful if you want to evaluate if a different stack +offset would give you better code, but to actually use a different stack +offset to build working programs, it is recommended to configure the +toolchain with the appropriate @samp{--with-stack-offset=@var{num}} option. + +@item -mno-round-nearest +@opindex mno-round-nearest +Make the scheduler assume that the rounding mode has been set to +truncating. The default is @option{-mround-nearest}. + +@item -mlong-calls +@opindex mlong-calls +If not otherwise specified by an attribute, assume all calls might be beyond +the offset range of the b / bl instructions, and therefore load the +function address into a register before performing a (otherwise direct) call. +This is the default. + +@item -mshort-calls +@opindex short-calls +If not otherwise specified by an attribute, assume all direct calls are +in the range of the b / bl instructions, so use these instructions +for direct calls. The default is @option{-mlong-calls}. + +@item -msmall16 +@opindex msmall16 +Assume addresses can be loaded as 16 bit unsigned values. This does not +apply to function addresses for which @option{-mlong-calls} semantics +are in effect. + +@item -mfp-mode=@var{mode} +@opindex mfp-mode +Set the prevailing mode of the floating point unit. +This determines the floating point mode that is provided and expected +at function call and return time. Making this mode match the mode you +predominantly need at function start can make your programs smaller and +faster by avoiding unnecessary mode switches. + +@var{mode} can be set to one the following values: + +@table @samp +@item caller +Any mode at function entry is valid, and retained or restored when +the function returns, and when it calls other functions. +This mode is useful for compiling libraries or other compilation units +you might want to incorporate into different programs with different +prevailing FPU modes, and the convenience of being able to use a single +object file outweighs the size and speed overhead for any extra +mode switching that might be needed, compared with what would be needed +with a more specific choice of prevailing FPU mode. + +@item truncate +This is the mode used for floating point calculations with +truncating (i.e.@: round towards zero) rounding mode. That includes +conversion from floating point to integer. + +@item round-nearest +This is the mode used for floating point calculations with +round-to-nearest-or-even rounding mode. + +@item int +This is the mode used to perform integer calculations in the FPU, e.g.@: +integer multiply, or integer multiply-and-accumulate. +@end table + +The default is @option{-mfp-mode=caller} + +@item -mnosplit-lohi +@opindex mnosplit-lohi +@item -mno-postinc +@opindex mno-postinc +@item -mno-postmodify +@opindex mno-postmodify +Code generation tweaks that disable, respectively, splitting of 32 +bit loads, generation of post-increment addresses, and generation of +post-modify addresses. The defaults are @option{msplit-lohi}, +@option{-mpost-inc}, and @option{-mpost-modify}. + +@item -mnovect-double +@opindex mno-vect-double +Change the preferred SIMD mode to SImode. The default is +@option{-mvect-double}, which uses DImode as preferred SIMD mode. + +@item -max-vect-align=@var{num} +@opindex max-vect-align +The maximum alignment for SIMD vector mode types. +@var{num} may be 4 or 8. The default is 8. +Note that this is an ABI change, even though many library function +interfaces will be unaffected, if they don't use SIMD vector modes +in places where they affect size and/or alignment of relevant types. + +@item -msplit-vecmove-early +@opindex msplit-vecmove-early +Split vector moves into single word moves before reload. In theory this +could give better register allocation, but so far the reverse seems to be +generally the case. + +@item -m1reg-@var{reg} +@opindex m1reg- +Specify a register to hold the constant @minus{}1, which makes loading small negative +constants and certain bitmasks faster. +Allowable values for reg are r43 and r63, which specify to use that register +as a fixed register, and none, which means that no register is used for this +purpose. The default is @option{-m1reg-none}. + +@end table + @node ARM Options @subsection ARM Options @cindex ARM options @@ -13024,7 +13215,8 @@ This option will enable GCC to use CMPXCHG16B instruction in generated code. CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). This instruction is generated as part of -atomic built-in functions: see @ref{Atomic Builtins} for details. +atomic built-in functions: see @ref{__sync Builtins} or +@ref{__atomic Builtins} for details. @item -msahf @opindex msahf diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 4a0bcfa1bf1..6b75f2bce28 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1,5 +1,5 @@ @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, -@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 @c Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -1778,6 +1778,77 @@ A memory address based on Y or Z pointer with displacement. Constant integer 4 @end table +@item Epiphany---@file{config/epiphany/constraints.md} +@table @code +@item U16 +An unsigned 16-bit constant. + +@item K +An unsigned 5-bit constant. + +@item L +A signed 11-bit constant. + +@item Cm1 +A signed 11-bit constant added to @minus{}1. +Can only match when the @option{-m1reg-@var{reg}} option is active. + +@item Cl1 +Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest +being a block of trailing zeroes. +Can only match when the @option{-m1reg-@var{reg}} option is active. + +@item Cr1 +Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the +rest being zeroes. Or to put it another way, one less than a power of two. +Can only match when the @option{-m1reg-@var{reg}} option is active. + +@item Cal +Constant for arithmetic/logical operations. +This is like @code{i}, except that for position independent code, +no symbols / expressions needing relocations are allowed. + +@item Csy +Symbolic constant for call/jump instruction. + +@item Rcs +The register class usable in short insns. This is a register class +constraint, and can thus drive register allocation. +This constraint won't match unless @option{-mprefer-short-insn-regs} is +in effect. + +@item Rsc +The the register class of registers that can be used to hold a +sibcall call address. I.e., a caller-saved register. + +@item Rct +Core control register class. + +@item Rgs +The register group usable in short insns. +This constraint does not use a register class, so that it only +passively matches suitable registers, and doesn't drive register allocation. + +@ifset INTERNALS +@item Car +Constant suitable for the addsi3_r pattern. This is a valid offset +For byte, halfword, or word addressing. +@end ifset + +@item Rra +Matches the return address if it can be replaced with the link register. + +@item Rcc +Matches the integer condition code register. + +@item Sra +Matches the return address if it is in a stack slot. + +@item Cfm +Matches control register values to switch fp mode, which are encapsulated in +@code{UNSPEC_FP_MODE}. +@end table + @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h} @table @code @item a @@ -5628,6 +5699,155 @@ released only after all previous memory operations have completed. If this pattern is not defined, then a @code{memory_barrier} pattern will be emitted, followed by a store of the value to the memory operand. +@cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern +@item @samp{atomic_compare_and_swap@var{mode}} +This pattern, if defined, emits code for an atomic compare-and-swap +operation with memory model semantics. Operand 2 is the memory on which +the atomic operation is performed. Operand 0 is an output operand which +is set to true or false based on whether the operation succeeded. Operand +1 is an output operand which is set to the contents of the memory before +the operation was attempted. Operand 3 is the value that is expected to +be in memory. Operand 4 is the value to put in memory if the expected +value is found there. Operand 5 is set to 1 if this compare and swap is to +be treated as a weak operation. Operand 6 is the memory model to be used +if the operation is a success. Operand 7 is the memory model to be used +if the operation fails. + +If memory referred to in operand 2 contains the value in operand 3, then +operand 4 is stored in memory pointed to by operand 2 and fencing based on +the memory model in operand 6 is issued. + +If memory referred to in operand 2 does not contain the value in operand 3, +then fencing based on the memory model in operand 7 is issued. + +If a target does not support weak compare-and-swap operations, or the port +elects not to implement weak operations, the argument in operand 5 can be +ignored. Note a strong implementation must be provided. + +If this pattern is not provided, the @code{__atomic_compare_exchange} +built-in functions will utilize the legacy @code{sync_compare_and_swap} +pattern with an @code{__ATOMIC_SEQ_CST} memory model. + +@cindex @code{atomic_load@var{mode}} instruction pattern +@item @samp{atomic_load@var{mode}} +This pattern implements an atomic load operation with memory model +semantics. Operand 1 is the memory address being loaded from. Operand 0 +is the result of the load. Operand 2 is the memory model to be used for +the load operation. + +If not present, the @code{__atomic_load} built-in function will either +resort to a normal load with memory barriers, or a compare-and-swap +operation if a normal load would not be atomic. + +@cindex @code{atomic_store@var{mode}} instruction pattern +@item @samp{atomic_store@var{mode}} +This pattern implements an atomic store operation with memory model +semantics. Operand 0 is the memory address being stored to. Operand 1 +is the value to be written. Operand 2 is the memory model to be used for +the operation. + +If not present, the @code{__atomic_store} built-in function will attempt to +perform a normal store and surround it with any required memory fences. If +the store would not be atomic, then an @code{__atomic_exchange} is +attempted with the result being ignored. + +@cindex @code{atomic_exchange@var{mode}} instruction pattern +@item @samp{atomic_exchange@var{mode}} +This pattern implements an atomic exchange operation with memory model +semantics. Operand 1 is the memory location the operation is performed on. +Operand 0 is an output operand which is set to the original value contained +in the memory pointed to by operand 1. Operand 2 is the value to be +stored. Operand 3 is the memory model to be used. + +If this pattern is not present, the built-in function +@code{__atomic_exchange} will attempt to preform the operation with a +compare and swap loop. + +@cindex @code{atomic_add@var{mode}} instruction pattern +@cindex @code{atomic_sub@var{mode}} instruction pattern +@cindex @code{atomic_or@var{mode}} instruction pattern +@cindex @code{atomic_and@var{mode}} instruction pattern +@cindex @code{atomic_xor@var{mode}} instruction pattern +@cindex @code{atomic_nand@var{mode}} instruction pattern +@item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}} +@itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}} +@itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}} + +These patterns emit code for an atomic operation on memory with memory +model semantics. Operand 0 is the memory on which the atomic operation is +performed. Operand 1 is the second operand to the binary operator. +Operand 2 is the memory model to be used by the operation. + +If these patterns are not defined, attempts will be made to use legacy +@code{sync} patterns, or equivilent patterns which return a result. If +none of these are available a compare-and-swap loop will be used. + +@cindex @code{atomic_fetch_add@var{mode}} instruction pattern +@cindex @code{atomic_fetch_sub@var{mode}} instruction pattern +@cindex @code{atomic_fetch_or@var{mode}} instruction pattern +@cindex @code{atomic_fetch_and@var{mode}} instruction pattern +@cindex @code{atomic_fetch_xor@var{mode}} instruction pattern +@cindex @code{atomic_fetch_nand@var{mode}} instruction pattern +@item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}} +@itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}} +@itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}} + +These patterns emit code for an atomic operation on memory with memory +model semantics, and return the original value. Operand 0 is an output +operand which contains the value of the memory location before the +operation was performed. Operand 1 is the memory on which the atomic +operation is performed. Operand 2 is the second operand to the binary +operator. Operand 3 is the memory model to be used by the operation. + +If these patterns are not defined, attempts will be made to use legacy +@code{sync} patterns. If none of these are available a compare-and-swap +loop will be used. + +@cindex @code{atomic_add_fetch@var{mode}} instruction pattern +@cindex @code{atomic_sub_fetch@var{mode}} instruction pattern +@cindex @code{atomic_or_fetch@var{mode}} instruction pattern +@cindex @code{atomic_and_fetch@var{mode}} instruction pattern +@cindex @code{atomic_xor_fetch@var{mode}} instruction pattern +@cindex @code{atomic_nand_fetch@var{mode}} instruction pattern +@item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}} +@itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}} +@itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}} + +These patterns emit code for an atomic operation on memory with memory +model semantics and return the result after the operation is performed. +Operand 0 is an output operand which contains the value after the +operation. Operand 1 is the memory on which the atomic operation is +performed. Operand 2 is the second operand to the binary operator. +Operand 3 is the memory model to be used by the operation. + +If these patterns are not defined, attempts will be made to use legacy +@code{sync} patterns, or equivilent patterns which return the result before +the operation followed by the arithmetic operation required to produce the +result. If none of these are available a compare-and-swap loop will be +used. + +@cindex @code{mem_thread_fence@var{mode}} instruction pattern +@item @samp{mem_thread_fence@var{mode}} +This pattern emits code required to implement a thread fence with +memory model semantics. Operand 0 is the memory model to be used. + +If this pattern is not specified, all memory models except +@code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} +barrier pattern. + +@cindex @code{mem_signal_fence@var{mode}} instruction pattern +@item @samp{mem_signal_fence@var{mode}} +This pattern emits code required to implement a signal fence with +memory model semantics. Operand 0 is the memory model to be used. + +This pattern should impact the compiler optimizers the same way that +mem_signal_fence does, but it does not need to issue any barrier +instructions. + +If this pattern is not specified, all memory models except +@code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} +barrier pattern. + @cindex @code{stack_protect_set} instruction pattern @item @samp{stack_protect_set} diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 737b48e0de8..d96932b4e48 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -5766,6 +5766,14 @@ This hook should return the built-in decl needed to load a vector of the given t This hook should return the built-in decl needed to store a vector of the given type within a transaction. @end deftypefn +@deftypefn {Target Hook} tree TARGET_VECTORIZE_BUILTIN_GATHER (const_tree @var{mem_vectype}, const_tree @var{index_type}, int @var{scale}) +Target builtin that implements vector gather operation. @var{mem_vectype} +is the vector type of the load and @var{index_type} is scalar type of +the index, scaled by @var{scale}. +The default is @code{NULL_TREE} which means to not vectorize gather +loads. +@end deftypefn + @node Anchored Addresses @section Anchored Addresses @cindex anchored addresses diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 348b7e6dee5..146e38a35e1 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -5700,6 +5700,14 @@ The default is zero which means to not iterate over other vector sizes. @hook TARGET_VECTORIZE_BUILTIN_TM_STORE +@hook TARGET_VECTORIZE_BUILTIN_GATHER +Target builtin that implements vector gather operation. @var{mem_vectype} +is the vector type of the load and @var{index_type} is scalar type of +the index, scaled by @var{scale}. +The default is @code{NULL_TREE} which means to not vectorize gather +loads. +@end deftypefn + @node Anchored Addresses @section Anchored Addresses @cindex anchored addresses |