diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 261 |
1 files changed, 177 insertions, 84 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e4ca1b4b4fc..5ae9dc4128d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -294,7 +294,7 @@ Objective-C and Objective-C++ Dialects}. -Wmain -Wmaybe-uninitialized -Wmemset-elt-size -Wmemset-transposed-args @gol -Wmisleading-indentation -Wmissing-braces @gol -Wmissing-field-initializers -Wmissing-include-dirs @gol --Wno-multichar -Wnonnull -Wnonnull-compare @gol +-Wno-multichar -Wmultistatement-macros -Wnonnull -Wnonnull-compare @gol -Wnormalized=@r{[}none@r{|}id@r{|}nfc@r{|}nfkc@r{]} @gol -Wnull-dereference -Wodr -Wno-overflow -Wopenmp-simd @gol -Woverride-init-side-effects -Woverlength-strings @gol @@ -587,15 +587,14 @@ Objective-C and Objective-C++ Dialects}. -mgeneral-regs-only @gol -mcmodel=tiny -mcmodel=small -mcmodel=large @gol -mstrict-align @gol --momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol +-momit-leaf-frame-pointer @gol -mtls-dialect=desc -mtls-dialect=traditional @gol -mtls-size=@var{size} @gol --mfix-cortex-a53-835769 -mno-fix-cortex-a53-835769 @gol --mfix-cortex-a53-843419 -mno-fix-cortex-a53-843419 @gol --mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt@gol --mlow-precision-sqrt -mno-low-precision-sqrt@gol --mlow-precision-div -mno-low-precision-div @gol --march=@var{name} -mcpu=@var{name} -mtune=@var{name}} +-mfix-cortex-a53-835769 -mfix-cortex-a53-843419 @gol +-mlow-precision-recip-sqrt -mlow-precision-sqrt -mlow-precision-div @gol +-mpc-relative-literal-loads @gol +-msign-return-address=@var{scope} @gol +-march=@var{name} -mcpu=@var{name} -mtune=@var{name} -moverride=@var{string}} @emph{Adapteva Epiphany Options} @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol @@ -632,6 +631,7 @@ Objective-C and Objective-C++ Dialects}. -mapcs-reentrant -mno-apcs-reentrant @gol -msched-prolog -mno-sched-prolog @gol -mlittle-endian -mbig-endian @gol +-mbe8 -mbe32 @gol -mfloat-abi=@var{name} @gol -mfp16-format=@var{name} -mthumb-interwork -mno-thumb-interwork @gol @@ -661,7 +661,8 @@ Objective-C and Objective-C++ Dialects}. @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -mabsdata -maccumulate-args @gol -mbranch-cost=@var{cost} @gol --mcall-prologues -mint8 -mn_flash=@var{size} -mno-interrupts @gol +-mcall-prologues -mgas-isr-prologues -mint8 @gol +-mn_flash=@var{size} -mno-interrupts @gol -mrelax -mrmw -mstrict-X -mtiny-stack -mfract-convert-truncate @gol -mshort-calls -nodevicelib @gol -Waddr-space-convert -Wmisspelled-isr} @@ -1044,14 +1045,10 @@ See RS/6000 and PowerPC Options. -mquad-memory -mno-quad-memory @gol -mquad-memory-atomic -mno-quad-memory-atomic @gol -mcompat-align-parm -mno-compat-align-parm @gol --mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol --mupper-regs-di -mno-upper-regs-di @gol --mupper-regs -mno-upper-regs @gol -mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol -mgnu-attribute -mno-gnu-attribute @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol --mstack-protector-guard-offset=@var{offset} @gol --mlra -mno-lra} +-mstack-protector-guard-offset=@var{offset}} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -1125,9 +1122,10 @@ See RS/6000 and PowerPC Options. -muser-mode -mno-user-mode @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol --mcbcond -mno-cbcond -mfmaf -mno-fmaf @gol --mpopc -mno-popc -msubxc -mno-subxc@gol --mfix-at697f -mfix-ut699 @gol +-mvis4 -mno-vis4 -mvis4b -mno-vis4b @gol +-mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld @gol +-mpopc -mno-popc -msubxc -mno-subxc @gol +-mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol -mlra -mno-lra} @emph{SPU Options} @@ -3842,6 +3840,7 @@ Options} and @ref{Objective-C and Objective-C++ Dialect Options}. -Wmemset-transposed-args @gol -Wmisleading-indentation @r{(only for C/C++)} @gol -Wmissing-braces @r{(only for C/ObjC)} @gol +-Wmultistatement-macros @gol -Wnarrowing @r{(only for C++)} @gol -Wnonnull @gol -Wnonnull-compare @gol @@ -4514,6 +4513,32 @@ This warning is enabled by @option{-Wall}. @opindex Wno-missing-include-dirs Warn if a user-supplied include directory does not exist. +@item -Wmultistatement-macros +@opindex Wmultistatement-macros +@opindex Wno-multistatement-macros +Warn about unsafe multiple statement macros that appear to be guarded +by a clause such as @code{if}, @code{else}, @code{for}, @code{switch}, or +@code{while}, in which only the first statement is actually guarded after +the macro is expanded. + +For example: + +@smallexample +#define DOIT x++; y++ +if (c) + DOIT; +@end smallexample + +will increment @code{y} unconditionally, not just when @code{c} holds. +The can usually be fixed by wrapping the macro in a do-while loop: +@smallexample +#define DOIT do @{ x++; y++; @} while (0) +if (c) + DOIT; +@end smallexample + +This warning is enabled by @option{-Wall} in C and C++. + @item -Wparentheses @opindex Wparentheses @opindex Wno-parentheses @@ -8672,7 +8697,7 @@ into separate sections of the assembly and @file{.o} files, to improve paging and cache locality performance. This optimization is automatically turned off in the presence of -exception handling, for linkonce sections, for functions with a user-defined +exception handling or unwind tables (on targets using setjump/longjump or target specific scheme), for linkonce sections, for functions with a user-defined section attribute and on any architecture that does not support named sections. When @option{-fsplit-stack} is used this option is not enabled by default (to avoid linker errors), but may be enabled @@ -11493,6 +11518,34 @@ of the function name, it is considered to be a match. For C99 and C++ extended identifiers, the function name must be given in UTF-8, not using universal character names. +@item -fpatchable-function-entry=@var{N}[,@var{M}] +@opindex fpatchable-function-entry +Generate @var{N} NOPs right at the beginning +of each function, with the function entry point before the @var{M}th NOP. +If @var{M} is omitted, it defaults to @code{0} so the +function entry points to the address just at the first NOP. +The NOP instructions reserve extra space which can be used to patch in +any desired instrumentation at run time, provided that the code segment +is writable. The amount of space is controllable indirectly via +the number of NOPs; the NOP instruction used corresponds to the instruction +emitted by the internal GCC back-end interface @code{gen_nop}. This behavior +is target-specific and may also depend on the architecture variant and/or +other compilation options. + +For run-time identification, the starting addresses of these areas, +which correspond to their respective function entries minus @var{M}, +are additionally collected in the @code{__patchable_function_entries} +section of the resulting binary. + +Note that the value of @code{__attribute__ ((patchable_function_entry +(N,M)))} takes precedence over command-line option +@option{-fpatchable-function-entry=N,M}. This can be used to increase +the area size or to remove it completely on a single function. +If @code{N=0}, no pad location is recorded. + +The NOP instructions are inserted at---and maybe before, depending on +@var{M}---the function entry address, even before the prologue. + @end table @@ -14055,7 +14108,7 @@ support for the ARMv8.2-A architecture extensions. The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler support for the ARMv8.1-A architecture extension. In particular, it -enables the @samp{+crc} and @samp{+lse} features. +enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. The value @samp{native} is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This @@ -14131,8 +14184,10 @@ across releases. This option is only intended to be useful when developing GCC. @item -mpc-relative-literal-loads +@itemx -mno-pc-relative-literal-loads @opindex mpc-relative-literal-loads -Enable PC-relative literal loads. With this option literal pools are +@opindex mno-pc-relative-literal-loads +Enable or disable PC-relative literal loads. With this option literal pools are accessed using a single instruction and emitted after each function. This limits the maximum size of functions to 1MB. This is enabled by default for @option{-mcmodel=tiny}. @@ -14171,8 +14226,15 @@ instructions. This is on by default for all possible values for options @item lse Enable Large System Extension instructions. This is on by default for @option{-march=armv8.1-a}. +@item rdma +Enable Round Double Multiply Accumulate instructions. This is on by default +for @option{-march=armv8.1-a}. @item fp16 Enable FP16 extension. This also enables floating-point instructions. +@item rcpc +Enable the RcPc extension. This does not change code generation from GCC, +but is passed on to the assembler, enabling inline asm statements to use +instructions from the RcPc extension. @end table @@ -14871,7 +14933,7 @@ Enable pre-reload use of the @code{cbranchsi} pattern. @item -mexpand-adddi @opindex mexpand-adddi Expand @code{adddi3} and @code{subdi3} at RTL generation time into -@code{add.f}, @code{adc} etc. +@code{add.f}, @code{adc} etc. This option is deprecated. @item -mindexed-loads @opindex mindexed-loads @@ -15161,7 +15223,16 @@ the default for all standard configurations. Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. -@item -march=@var{name@r{[}+extension@dots{}@r{]}} +@item -mbe8 +@itemx -mbe32 +@opindex mbe8 +When linking a big-endian image select between BE8 and BE32 formats. +The option has no effect for little-endian images and is ignored. The +default is dependent on the selected target architecture. For ARMv6 +and later architectures the default is BE8, for older architectures +the default is BE32. BE32 format has been deprecated by ARM. + +@item -march=@var{name}@r{[}+extension@dots{}@r{]} @opindex march This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating @@ -15176,6 +15247,7 @@ Permissible names are: @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv7-r}, +@samp{armv8-r}, @samp{armv6-m}, @samp{armv6s-m}, @samp{armv7-m}, @samp{armv7e-m}, @samp{armv8-m.base}, @samp{armv8-m.main}, @@ -15442,7 +15514,22 @@ The single- and double-precision floating-point instructions. @item +nofp Disable the floating-point extension. +@end table +@item armv8-r +@table @samp +@item +crc +The Cyclic Redundancy Check (CRC) instructions. +@item +fp.sp +The single-precision FPv5 floating-point instructions. +@item +simd +The ARMv8 Advanced SIMD and floating-point instructions. +@item +crypto +The cryptographic instructions. +@item +nocrypto +Disable the cryptographic isntructions. +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. @end table @end table @@ -15477,9 +15564,10 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, -@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4}, -@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, +@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, +@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, +@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, +@samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7}, @@ -15502,7 +15590,8 @@ Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, -@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}. +@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}, +@samp{cortex-a75.cortex-a55}. @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}. @@ -15519,7 +15608,7 @@ of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -mcpu=@var{name@r{[}+extension@dots{}@r{]}} +@item -mcpu=@var{name}@r{[}+extension@dots{}@r{]} @opindex mcpu This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified @@ -15563,17 +15652,25 @@ Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7}, -@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35} -and @samp{cortex-a53}. +@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35}, +@samp{cortex-a53} and @samp{cortex-a55}. @item +nofp.dp Disables the double-precision component of the floating-point instructions -on @samp{cortex-r5} and @samp{cortex-m7}. +on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}. @item +nosimd Disables the SIMD (but not floating-point) instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7} and @samp{cortex-a9}. + +@item +crypto +Enables the cryptographic instructions on @samp{cortex-a32}, +@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, +@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{exynos-m1}, +@samp{xgene1}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} and +@samp{cortex-a75.cortex-a55}. @end table Additionally the @samp{generic-armv7-a} pseudo target defaults to @@ -15641,6 +15738,8 @@ incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions. +This option is deprecated. + @item -mabort-on-noreturn @opindex mabort-on-noreturn Generate a call to the function @code{abort} at the end of a @@ -15918,6 +16017,16 @@ integers. The default branch cost is 0. Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller. +@item -mgas-isr-prologues +@opindex mgas-isr-prologues +Interrupt service routines (ISRs) may use the @code{__gcc_isr} pseudo +instruction supported by GNU Binutils. +If this option is on, the feature can still be disabled for individual +ISRs by means of the @ref{AVR Function Attributes,,@code{no_gccisr}} +function attribute. This feature is activated per default +if optimization is on (but not with @option{-Og}, @pxref{Optimize Options}), +and if GNU Binutils support @w{@uref{https://sourceware.org/PR21683,PR21683}}. + @item -mint8 @opindex mint8 Assume @code{int} to be 8-bit integer. This affects the sizes of all types: a @@ -21731,11 +21840,6 @@ This switch enables or disables the generation of ISEL instructions. This switch has been deprecated. Use @option{-misel} and @option{-mno-isel} instead. -@item -mlra -@opindex mlra -Enable Local Register Allocation. By default the port uses LRA. -(i.e. @option{-mno-lra}). - @item -mspe @itemx -mno-spe @opindex mspe @@ -21819,50 +21923,6 @@ Generate code that uses (does not use) the atomic quad word memory instructions. The @option{-mquad-memory-atomic} option requires use of 64-bit mode. -@item -mupper-regs-di -@itemx -mno-upper-regs-di -@opindex mupper-regs-di -@opindex mno-upper-regs-di -Generate code that uses (does not use) the scalar instructions that -target all 64 registers in the vector/scalar floating point register -set that were added in version 2.06 of the PowerPC ISA when processing -integers. @option{-mupper-regs-di} is turned on by default if you use -any of the @option{-mcpu=power7}, @option{-mcpu=power8}, -@option{-mcpu=power9}, or @option{-mvsx} options. - -@item -mupper-regs-df -@itemx -mno-upper-regs-df -@opindex mupper-regs-df -@opindex mno-upper-regs-df -Generate code that uses (does not use) the scalar double precision -instructions that target all 64 registers in the vector/scalar -floating point register set that were added in version 2.06 of the -PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you -use any of the @option{-mcpu=power7}, @option{-mcpu=power8}, -@option{-mcpu=power9}, or @option{-mvsx} options. - -@item -mupper-regs-sf -@itemx -mno-upper-regs-sf -@opindex mupper-regs-sf -@opindex mno-upper-regs-sf -Generate code that uses (does not use) the scalar single precision -instructions that target all 64 registers in the vector/scalar -floating point register set that were added in version 2.07 of the -PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you -use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or -@option{-mcpu=power9} options. - -@item -mupper-regs -@itemx -mno-upper-regs -@opindex mupper-regs -@opindex mno-upper-regs -Generate code that uses (does not use) the scalar -instructions that target all 64 registers in the vector/scalar -floating point register set, depending on the model of the machine. - -If the @option{-mno-upper-regs} option is used, it turns off both -@option{-mupper-regs-sf} and @option{-mupper-regs-df} options. - @item -mfloat128 @itemx -mno-float128 @opindex mfloat128 @@ -23835,7 +23895,7 @@ for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, -@samp{niagara3}, @samp{niagara4} and @samp{niagara7}. +@samp{niagara3}, @samp{niagara4}, @samp{niagara7} and @samp{m8}. Native Solaris and GNU/Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -23863,7 +23923,8 @@ f930, f934, sparclite86x tsc701 @item v9 -ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7 +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, +niagara7, m8 @end table By default (unless configured otherwise), GCC generates code for the V7 @@ -23907,7 +23968,8 @@ additionally optimizes it for Sun UltraSPARC T2 chips. With UltraSPARC T3 chips. With @option{-mcpu=niagara4}, the compiler additionally optimizes it for Sun UltraSPARC T4 chips. With @option{-mcpu=niagara7}, the compiler additionally optimizes it for -Oracle SPARC M7 chips. +Oracle SPARC M7 chips. With @option{-mcpu=m8}, the compiler +additionally optimizes it for Oracle M8 chips. @item -mtune=@var{cpu_type} @opindex mtune @@ -23922,8 +23984,8 @@ that select a particular CPU implementation. Those are @samp{leon3}, @samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, -@samp{niagara4} and @samp{niagara7}. With native Solaris and -GNU/Linux toolchains, @samp{native} can also be used. +@samp{niagara4}, @samp{niagara7} and @samp{m8}. With native Solaris +and GNU/Linux toolchains, @samp{native} can also be used. @item -mv8plus @itemx -mno-v8plus @@ -23971,6 +24033,18 @@ default is @option{-mvis4} when targeting a cpu that supports such instructions, such as niagara-7 and later. Setting @option{-mvis4} also sets @option{-mvis3}, @option{-mvis2} and @option{-mvis}. +@item -mvis4b +@itemx -mno-vis4b +@opindex mvis4b +@opindex mno-vis4b +With @option{-mvis4b}, GCC generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus +the additional VIS instructions introduced in the Oracle SPARC +Architecture 2017. The default is @option{-mvis4b} when targeting a +cpu that supports such instructions, such as m8 and later. Setting +@option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3}, +@option{-mvis2} and @option{-mvis}. + @item -mcbcond @itemx -mno-cbcond @opindex mcbcond @@ -23989,6 +24063,15 @@ Fused Multiply-Add Floating-point instructions. The default is @option{-mfmaf} when targeting a CPU that supports such instructions, such as Niagara-3 and later. +@item -mfsmuld +@itemx -mno-fsmuld +@opindex mfsmuld +@opindex mno-fsmuld +With @option{-mfsmuld}, GCC generates code that takes advantage of the +Floating-point Multiply Single to Double (FsMULd) instruction. The default is +@option{-mfsmuld} when targeting a CPU supporting the architecture versions V8 +or V9 with FPU except @option{-mcpu=leon}. + @item -mpopc @itemx -mno-popc @opindex mpopc @@ -24016,6 +24099,16 @@ processor (which corresponds to erratum #13 of the AT697E processor). @opindex mfix-ut699 Enable the documented workarounds for the floating-point errata and the data cache nullify errata of the UT699 processor. + +@item -mfix-ut700 +@opindex mfix-ut700 +Enable the documented workaround for the back-to-back store errata of +the UT699E/UT700 processor. + +@item -mfix-gr712rc +@opindex mfix-gr712rc +Enable the documented workaround for the back-to-back store errata of +the GR712RC processor. @end table These @samp{-m} options are supported in addition to the above |