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-rw-r--r--gcc/config/arm/arm-cores.def1
-rw-r--r--gcc/config/arm/arm-tune.md2
-rw-r--r--gcc/config/arm/arm.c1
-rw-r--r--gcc/config/arm/arm.h13
-rw-r--r--gcc/config/arm/arm.md77
-rw-r--r--gcc/config/arm/bpabi.h2
-rw-r--r--gcc/config/arm/linux-atomic.c280
-rw-r--r--gcc/config/arm/neon.md74
-rw-r--r--gcc/config/arm/t-linux-eabi2
-rw-r--r--gcc/config/i386/cygwin.h23
-rw-r--r--gcc/config/i386/i386.md14
-rw-r--r--gcc/config/i386/sol2-10.h11
-rw-r--r--gcc/config/mips/mips.c2
-rw-r--r--gcc/config/rs6000/rs6000-protos.h1
-rw-r--r--gcc/config/rs6000/rs6000.c20
-rw-r--r--gcc/config/rs6000/rs6000.md75
-rw-r--r--gcc/config/rs6000/rs6000.opt4
-rw-r--r--gcc/config/s390/s390.md102
-rw-r--r--gcc/config/sparc/linux.h4
-rw-r--r--gcc/config/sparc/linux64.h4
-rw-r--r--gcc/config/sparc/sysv4.h16
21 files changed, 562 insertions, 166 deletions
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index fe2f2b53792..ca868fe2d0c 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -102,6 +102,7 @@ ARM_CORE("arm1020e", arm1020e, 5TE, FL_LDSCHED, fastmul)
ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul)
ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
+ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
/* V5TEJ Architecture Processors */
ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index beb8f9f4173..ea728dcb67c 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune"
- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1"
+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1"
(const (symbol_ref "arm_tune")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 209682bb0fe..ddcdf5a619b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -665,6 +665,7 @@ static const struct processors all_architectures[] =
{"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
{"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
{"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
+ {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
{NULL, arm_none, NULL, 0 , NULL}
};
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f83aabac038..fb636f3d540 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -564,6 +564,19 @@ extern int arm_arch_hwdiv;
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
+/* Align definitions of arrays, unions and structures so that
+ initializations and copies can be made more efficient. This is not
+ ABI-changing, so it only affects places where we can see the
+ definition. */
+#define DATA_ALIGNMENT(EXP, ALIGN) \
+ ((((ALIGN) < BITS_PER_WORD) \
+ && (TREE_CODE (EXP) == ARRAY_TYPE \
+ || TREE_CODE (EXP) == UNION_TYPE \
+ || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
+
+/* Similarly, make sure that objects on the stack are sensibly aligned. */
+#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
+
/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
value set in previous versions of this toolchain was 8, which produces more
compact structures. The command line option -mstructure_size_boundary=<n>
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 96e2f3b1bb3..0acf257cb43 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -250,6 +250,75 @@
; initialized by arm_override_options()
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
+;; Classification of NEON instructions for scheduling purposes.
+;; Do not set this attribute and the "type" attribute together in
+;; any one instruction pattern.
+(define_attr "neon_type"
+ "neon_int_1,\
+ neon_int_2,\
+ neon_int_3,\
+ neon_int_4,\
+ neon_int_5,\
+ neon_vqneg_vqabs,\
+ neon_vmov,\
+ neon_vaba,\
+ neon_vsma,\
+ neon_vaba_qqq,\
+ neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mul_qqq_8_16_32_ddd_32,\
+ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
+ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mla_qqq_8_16,\
+ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
+ neon_mla_qqq_32_qqd_32_scalar,\
+ neon_mul_ddd_16_scalar_32_16_long_scalar,\
+ neon_mul_qqd_32_scalar,\
+ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
+ neon_shift_1,\
+ neon_shift_2,\
+ neon_shift_3,\
+ neon_vshl_ddd,\
+ neon_vqshl_vrshl_vqrshl_qqq,\
+ neon_vsra_vrsra,\
+ neon_fp_vadd_ddd_vabs_dd,\
+ neon_fp_vadd_qqq_vabs_qq,\
+ neon_fp_vsum,\
+ neon_fp_vmul_ddd,\
+ neon_fp_vmul_qqd,\
+ neon_fp_vmla_ddd,\
+ neon_fp_vmla_qqq,\
+ neon_fp_vmla_ddd_scalar,\
+ neon_fp_vmla_qqq_scalar,\
+ neon_fp_vrecps_vrsqrts_ddd,\
+ neon_fp_vrecps_vrsqrts_qqq,\
+ neon_bp_simple,\
+ neon_bp_2cycle,\
+ neon_bp_3cycle,\
+ neon_ldr,\
+ neon_str,\
+ neon_vld1_1_2_regs,\
+ neon_vld1_3_4_regs,\
+ neon_vld2_2_regs_vld1_vld2_all_lanes,\
+ neon_vld2_4_regs,\
+ neon_vld3_vld4,\
+ neon_vst1_1_2_regs_vst2_2_regs,\
+ neon_vst1_3_4_regs,\
+ neon_vst2_4_regs_vst3_vst4,\
+ neon_vst3_vst4,\
+ neon_vld1_vld2_lane,\
+ neon_vld3_vld4_lane,\
+ neon_vst1_vst2_lane,\
+ neon_vst3_vst4_lane,\
+ neon_vld3_vld4_all_lanes,\
+ neon_mcr,\
+ neon_mcr_2_mcrr,\
+ neon_mrc,\
+ neon_mrrc,\
+ neon_ldm_2,\
+ neon_stm_2,\
+ none"
+ (const_string "none"))
+
; condition codes: this one is used by final_prescan_insn to speed up
; conditionalizing instructions. It saves having to scan the rtl to see if
; it uses or alters the condition codes.
@@ -267,13 +336,17 @@
; JUMP_CLOB is used when the condition cannot be represented by a single
; instruction (UNEQ and LTGT). These cannot be predicated.
;
+; UNCONDITIONAL means the instions can not be conditionally executed.
+;
; NOCOND means that the condition codes are neither altered nor affect the
; output of this insn
-(define_attr "conds" "use,set,clob,jump_clob,nocond"
+(define_attr "conds" "use,set,clob,jump_clob,unconditional,nocond"
(if_then_else (eq_attr "type" "call")
(const_string "clob")
- (const_string "nocond")))
+ (if_then_else (eq_attr "neon_type" "none")
+ (const_string "nocond")
+ (const_string "unconditional"))))
; Predicable means that the insn can be conditionally executed based on
; an automatically added predicate (additional patterns are generated by
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index bc716593c17..bbd58da4d42 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -55,7 +55,7 @@
/* Tell the assembler to build BPABI binaries. */
#undef SUBTARGET_EXTRA_ASM_SPEC
-#define SUBTARGET_EXTRA_ASM_SPEC "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=4}" TARGET_FIX_V4BX_SPEC
+#define SUBTARGET_EXTRA_ASM_SPEC "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC
#ifndef SUBTARGET_EXTRA_LINK_SPEC
#define SUBTARGET_EXTRA_LINK_SPEC ""
diff --git a/gcc/config/arm/linux-atomic.c b/gcc/config/arm/linux-atomic.c
new file mode 100644
index 00000000000..ac0b4d6d14b
--- /dev/null
+++ b/gcc/config/arm/linux-atomic.c
@@ -0,0 +1,280 @@
+/* Linux-specific atomic operations for ARM EABI.
+ Copyright (C) 2008 Free Software Foundation, Inc.
+ Contributed by CodeSourcery.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to the Free
+Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+02110-1301, USA. */
+
+/* Kernel helper for compare-and-exchange. */
+typedef int (__kernel_cmpxchg_t) (int oldval, int newval, int *ptr);
+#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *) 0xffff0fc0)
+
+/* Kernel helper for memory barrier. */
+typedef void (__kernel_dmb_t) (void);
+#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
+
+/* Note: we implement byte, short and int versions of atomic operations using
+ the above kernel helpers, but there is no support for "long long" (64-bit)
+ operations as yet. */
+
+#define HIDDEN __attribute__ ((visibility ("hidden")))
+
+#ifdef __ARMEL__
+#define INVERT_MASK_1 0
+#define INVERT_MASK_2 0
+#else
+#define INVERT_MASK_1 24
+#define INVERT_MASK_2 16
+#endif
+
+#define MASK_1 0xffu
+#define MASK_2 0xffffu
+
+#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \
+ int HIDDEN \
+ __sync_fetch_and_##OP##_4 (int *ptr, int val) \
+ { \
+ int failure, tmp; \
+ \
+ do { \
+ tmp = *ptr; \
+ failure = __kernel_cmpxchg (tmp, PFX_OP tmp INF_OP val, ptr); \
+ } while (failure != 0); \
+ \
+ return tmp; \
+ }
+
+FETCH_AND_OP_WORD (add, , +)
+FETCH_AND_OP_WORD (sub, , -)
+FETCH_AND_OP_WORD (or, , |)
+FETCH_AND_OP_WORD (and, , &)
+FETCH_AND_OP_WORD (xor, , ^)
+FETCH_AND_OP_WORD (nand, ~, &)
+
+#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH
+#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH
+
+/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for
+ subword-sized quantities. */
+
+#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN) \
+ TYPE HIDDEN \
+ NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val) \
+ { \
+ int *wordptr = (int *) ((unsigned int) ptr & ~3); \
+ unsigned int mask, shift, oldval, newval; \
+ int failure; \
+ \
+ shift = (((unsigned int) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
+ mask = MASK_##WIDTH << shift; \
+ \
+ do { \
+ oldval = *wordptr; \
+ newval = ((PFX_OP ((oldval & mask) >> shift) \
+ INF_OP (unsigned int) val) << shift) & mask; \
+ newval |= oldval & ~mask; \
+ failure = __kernel_cmpxchg (oldval, newval, wordptr); \
+ } while (failure != 0); \
+ \
+ return (RETURN & mask) >> shift; \
+ }
+
+SUBWORD_SYNC_OP (add, , +, short, 2, oldval)
+SUBWORD_SYNC_OP (sub, , -, short, 2, oldval)
+SUBWORD_SYNC_OP (or, , |, short, 2, oldval)
+SUBWORD_SYNC_OP (and, , &, short, 2, oldval)
+SUBWORD_SYNC_OP (xor, , ^, short, 2, oldval)
+SUBWORD_SYNC_OP (nand, ~, &, short, 2, oldval)
+
+SUBWORD_SYNC_OP (add, , +, char, 1, oldval)
+SUBWORD_SYNC_OP (sub, , -, char, 1, oldval)
+SUBWORD_SYNC_OP (or, , |, char, 1, oldval)
+SUBWORD_SYNC_OP (and, , &, char, 1, oldval)
+SUBWORD_SYNC_OP (xor, , ^, char, 1, oldval)
+SUBWORD_SYNC_OP (nand, ~, &, char, 1, oldval)
+
+#define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \
+ int HIDDEN \
+ __sync_##OP##_and_fetch_4 (int *ptr, int val) \
+ { \
+ int tmp, failure; \
+ \
+ do { \
+ tmp = *ptr; \
+ failure = __kernel_cmpxchg (tmp, PFX_OP tmp INF_OP val, ptr); \
+ } while (failure != 0); \
+ \
+ return PFX_OP tmp INF_OP val; \
+ }
+
+OP_AND_FETCH_WORD (add, , +)
+OP_AND_FETCH_WORD (sub, , -)
+OP_AND_FETCH_WORD (or, , |)
+OP_AND_FETCH_WORD (and, , &)
+OP_AND_FETCH_WORD (xor, , ^)
+OP_AND_FETCH_WORD (nand, ~, &)
+
+SUBWORD_SYNC_OP (add, , +, short, 2, newval)
+SUBWORD_SYNC_OP (sub, , -, short, 2, newval)
+SUBWORD_SYNC_OP (or, , |, short, 2, newval)
+SUBWORD_SYNC_OP (and, , &, short, 2, newval)
+SUBWORD_SYNC_OP (xor, , ^, short, 2, newval)
+SUBWORD_SYNC_OP (nand, ~, &, short, 2, newval)
+
+SUBWORD_SYNC_OP (add, , +, char, 1, newval)
+SUBWORD_SYNC_OP (sub, , -, char, 1, newval)
+SUBWORD_SYNC_OP (or, , |, char, 1, newval)
+SUBWORD_SYNC_OP (and, , &, char, 1, newval)
+SUBWORD_SYNC_OP (xor, , ^, char, 1, newval)
+SUBWORD_SYNC_OP (nand, ~, &, char, 1, newval)
+
+int HIDDEN
+__sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
+{
+ int actual_oldval, fail;
+
+ while (1)
+ {
+ actual_oldval = *ptr;
+
+ if (oldval != actual_oldval)
+ return actual_oldval;
+
+ fail = __kernel_cmpxchg (actual_oldval, newval, ptr);
+
+ if (!fail)
+ return oldval;
+ }
+}
+
+#define SUBWORD_VAL_CAS(TYPE, WIDTH) \
+ TYPE HIDDEN \
+ __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
+ TYPE newval) \
+ { \
+ int *wordptr = (int *)((unsigned int) ptr & ~3), fail; \
+ unsigned int mask, shift, actual_oldval, actual_newval; \
+ \
+ shift = (((unsigned int) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
+ mask = MASK_##WIDTH << shift; \
+ \
+ while (1) \
+ { \
+ actual_oldval = *wordptr; \
+ \
+ if (((actual_oldval & mask) >> shift) != (unsigned int) oldval) \
+ return (actual_oldval & mask) >> shift; \
+ \
+ actual_newval = (actual_oldval & ~mask) \
+ | (((unsigned int) newval << shift) & mask); \
+ \
+ fail = __kernel_cmpxchg (actual_oldval, actual_newval, \
+ wordptr); \
+ \
+ if (!fail) \
+ return oldval; \
+ } \
+ }
+
+SUBWORD_VAL_CAS (short, 2)
+SUBWORD_VAL_CAS (char, 1)
+
+typedef unsigned char bool;
+
+bool HIDDEN
+__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval)
+{
+ int failure = __kernel_cmpxchg (oldval, newval, ptr);
+ return (failure == 0);
+}
+
+#define SUBWORD_BOOL_CAS(TYPE, WIDTH) \
+ bool HIDDEN \
+ __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
+ TYPE newval) \
+ { \
+ TYPE actual_oldval \
+ = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval); \
+ return (oldval == actual_oldval); \
+ }
+
+SUBWORD_BOOL_CAS (short, 2)
+SUBWORD_BOOL_CAS (char, 1)
+
+void HIDDEN
+__sync_synchronize (void)
+{
+ __kernel_dmb ();
+}
+
+int HIDDEN
+__sync_lock_test_and_set_4 (int *ptr, int val)
+{
+ int failure, oldval;
+
+ do {
+ oldval = *ptr;
+ failure = __kernel_cmpxchg (oldval, val, ptr);
+ } while (failure != 0);
+
+ return oldval;
+}
+
+#define SUBWORD_TEST_AND_SET(TYPE, WIDTH) \
+ TYPE HIDDEN \
+ __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \
+ { \
+ int failure; \
+ unsigned int oldval, newval, shift, mask; \
+ int *wordptr = (int *) ((unsigned int) ptr & ~3); \
+ \
+ shift = (((unsigned int) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
+ mask = MASK_##WIDTH << shift; \
+ \
+ do { \
+ oldval = *wordptr; \
+ newval = (oldval & ~mask) \
+ | (((unsigned int) val << shift) & mask); \
+ failure = __kernel_cmpxchg (oldval, newval, wordptr); \
+ } while (failure != 0); \
+ \
+ return (oldval & mask) >> shift; \
+ }
+
+SUBWORD_TEST_AND_SET (short, 2)
+SUBWORD_TEST_AND_SET (char, 1)
+
+#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \
+ void HIDDEN \
+ __sync_lock_release_##WIDTH (TYPE *ptr) \
+ { \
+ *ptr = 0; \
+ __kernel_dmb (); \
+ }
+
+SYNC_LOCK_RELEASE (int, 4)
+SYNC_LOCK_RELEASE (short, 2)
+SYNC_LOCK_RELEASE (char, 1)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 8d10c1e5b42..dbbd209f79c 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -427,76 +427,7 @@
;; neon_type attribute definitions.
(define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd"))
-;; Classification of NEON instructions for scheduling purposes.
-;; Do not set this attribute and the "type" attribute together in
-;; any one instruction pattern.
-(define_attr "neon_type"
- "neon_int_1,\
- neon_int_2,\
- neon_int_3,\
- neon_int_4,\
- neon_int_5,\
- neon_vqneg_vqabs,\
- neon_vmov,\
- neon_vaba,\
- neon_vsma,\
- neon_vaba_qqq,\
- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mul_qqq_8_16_32_ddd_32,\
- neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mla_qqq_8_16,\
- neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
- neon_mla_qqq_32_qqd_32_scalar,\
- neon_mul_ddd_16_scalar_32_16_long_scalar,\
- neon_mul_qqd_32_scalar,\
- neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
- neon_shift_1,\
- neon_shift_2,\
- neon_shift_3,\
- neon_vshl_ddd,\
- neon_vqshl_vrshl_vqrshl_qqq,\
- neon_vsra_vrsra,\
- neon_fp_vadd_ddd_vabs_dd,\
- neon_fp_vadd_qqq_vabs_qq,\
- neon_fp_vsum,\
- neon_fp_vmul_ddd,\
- neon_fp_vmul_qqd,\
- neon_fp_vmla_ddd,\
- neon_fp_vmla_qqq,\
- neon_fp_vmla_ddd_scalar,\
- neon_fp_vmla_qqq_scalar,\
- neon_fp_vrecps_vrsqrts_ddd,\
- neon_fp_vrecps_vrsqrts_qqq,\
- neon_bp_simple,\
- neon_bp_2cycle,\
- neon_bp_3cycle,\
- neon_ldr,\
- neon_str,\
- neon_vld1_1_2_regs,\
- neon_vld1_3_4_regs,\
- neon_vld2_2_regs_vld1_vld2_all_lanes,\
- neon_vld2_4_regs,\
- neon_vld3_vld4,\
- neon_vst1_1_2_regs_vst2_2_regs,\
- neon_vst1_3_4_regs,\
- neon_vst2_4_regs_vst3_vst4,\
- neon_vst3_vst4,\
- neon_vld1_vld2_lane,\
- neon_vld3_vld4_lane,\
- neon_vst1_vst2_lane,\
- neon_vst3_vst4_lane,\
- neon_vld3_vld4_all_lanes,\
- neon_mcr,\
- neon_mcr_2_mcrr,\
- neon_mrc,\
- neon_mrrc,\
- neon_ldm_2,\
- neon_stm_2,\
- none"
- (const_string "none"))
-
-;; Predicates used for setting the above attribute.
+;; Predicates used for setting neon_type
(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
(V4HI "false") (V8HI "false")
@@ -639,7 +570,8 @@
default: gcc_unreachable ();
}
}
- [(set_attr "length" "<V_slen>,<V_slen>,<V_slen>")])
+ [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_ldm_2")
+ (set_attr "length" "<V_slen>,<V_slen>,<V_slen>")])
(define_split
[(set (match_operand:EI 0 "s_register_operand" "")
diff --git a/gcc/config/arm/t-linux-eabi b/gcc/config/arm/t-linux-eabi
index 5e8d94d7a28..5c364be94fa 100644
--- a/gcc/config/arm/t-linux-eabi
+++ b/gcc/config/arm/t-linux-eabi
@@ -12,3 +12,5 @@ LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx
# Multilib the standard Linux files. Don't include crti.o or crtn.o,
# which are provided by glibc.
EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
+
+LIB2FUNCS_STATIC_EXTRA += $(srcdir)/config/arm/linux-atomic.c
diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h
index f61cacb3e1a..9b2fd7f2b7d 100644
--- a/gcc/config/i386/cygwin.h
+++ b/gcc/config/i386/cygwin.h
@@ -49,9 +49,26 @@ along with GCC; see the file COPYING3. If not see
GCC without making a new CYGWIN.DLL, so we leave it. Profiling is handled
by calling the init function from main. */
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC \
- "%{mno-cygwin: %{mthreads:-lmingwthrd} -lmingw32} -lgcc \
+#ifdef ENABLE_SHARED_LIBGCC
+#define SHARED_LIBGCC_SPEC " \
+ %{static|static-libgcc:-lgcc -lgcc_eh} \
+ %{!static: \
+ %{!static-libgcc: \
+ %{!shared: \
+ %{!shared-libgcc:-lgcc -lgcc_eh} \
+ %{shared-libgcc:-lgcc_s -lgcc} \
+ } \
+ %{shared:-lgcc_s -lgcc} \
+ } \
+ } "
+#else
+#define SHARED_LIBGCC_SPEC " -lgcc "
+#endif
+
+#undef REAL_LIBGCC_SPEC
+#define REAL_LIBGCC_SPEC \
+ "%{mno-cygwin: %{mthreads:-lmingwthrd} -lmingw32} \
+ " SHARED_LIBGCC_SPEC " \
%{mno-cygwin:-lmoldname -lmingwex -lmsvcrt}"
/* We have to dynamic link to get to the system DLLs. All of libc, libm and
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0569f0413a8..89a3b17607b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1534,7 +1534,7 @@
gcc_unreachable ();
}
- case TYPE_MMXADD:
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MMXMOV:
@@ -1552,7 +1552,7 @@
}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "3,4,5")
(const_string "mmxmov")
(eq_attr "alternative" "6")
@@ -2370,7 +2370,7 @@
case TYPE_SSELOG1:
return "%vpxor\t%0, %d0";
- case TYPE_MMXADD:
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MULTI:
@@ -2391,7 +2391,7 @@
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "6,7,8,9,10")
(const_string "mmxmov")
(eq_attr "alternative" "11")
@@ -15299,7 +15299,7 @@
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
+ (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
@@ -15307,7 +15307,9 @@
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
+ (unspec:DI
+ [(label_ref (match_operand 1 "" ""))]
+ UNSPEC_SET_GOT_OFFSET))]
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
diff --git a/gcc/config/i386/sol2-10.h b/gcc/config/i386/sol2-10.h
index bd5c63781af..6e7f13d8f26 100644
--- a/gcc/config/i386/sol2-10.h
+++ b/gcc/config/i386/sol2-10.h
@@ -1,5 +1,5 @@
/* Solaris 10 configuration.
- Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by CodeSourcery, LLC.
This file is part of GCC.
@@ -39,6 +39,15 @@ along with GCC; see the file COPYING3. If not see
#ifndef HAVE_AS_IX86_DIFF_SECT_DELTA
#undef JUMP_TABLES_IN_TEXT_SECTION
#define JUMP_TABLES_IN_TEXT_SECTION 1
+
+/* The native Solaris assembler cannot handle the SYMBOL-. syntax, but
+ requires SYMBOL@rel/@rel64 instead. */
+#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
+ do { \
+ fputs (integer_asm_op (SIZE, FALSE), FILE); \
+ assemble_name (FILE, LABEL); \
+ fputs (SIZE == 8 ? "@rel64" : "@rel", FILE); \
+ } while (0)
#endif
#undef NO_PROFILE_COUNTERS
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 55b1c22be66..c98528e7eb4 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13296,7 +13296,7 @@ mips_reorg (void)
mips16_lay_out_constants ();
if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
r10k_insert_cache_barriers ();
- if (flag_delayed_branch)
+ if (optimize > 0 && flag_delayed_branch)
dbr_schedule (get_insns ());
mips_reorg_process_insns ();
if (!TARGET_MIPS16
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 2f1b04c4f38..4e2ecd3ec4a 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -42,6 +42,7 @@ extern void validate_condition_mode (enum rtx_code, enum machine_mode);
extern bool legitimate_constant_pool_address_p (rtx);
extern bool legitimate_indirect_address_p (rtx, int);
extern bool legitimate_indexed_address_p (rtx, int);
+extern bool avoiding_indexed_address_p (enum machine_mode);
extern rtx rs6000_got_register (rtx);
extern rtx find_addr_reg (rtx);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6d7327b5ea4..d2ebf628f57 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1987,6 +1987,13 @@ rs6000_override_options (const char *default_cpu)
rs6000_single_float = rs6000_double_float = 1;
}
+ /* If not explicitly specified via option, decide whether to generate indexed
+ load/store instructions. */
+ if (TARGET_AVOID_XFORM == -1)
+ /* Avoid indexed addressing when targeting Power6 in order to avoid
+ the DERAT mispredict penalty. */
+ TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB);
+
rs6000_init_hard_regno_mode_ok ();
}
@@ -3704,6 +3711,14 @@ legitimate_indexed_address_p (rtx x, int strict)
&& INT_REG_OK_FOR_INDEX_P (op0, strict))));
}
+bool
+avoiding_indexed_address_p (enum machine_mode mode)
+{
+ /* Avoid indexed addressing for modes that have non-indexed
+ load/store instruction forms. */
+ return TARGET_AVOID_XFORM && !ALTIVEC_VECTOR_MODE (mode);
+}
+
inline bool
legitimate_indirect_address_p (rtx x, int strict)
{
@@ -3830,6 +3845,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
|| ((mode != DImode && mode != DFmode && mode != DDmode)
|| (TARGET_E500_DOUBLE && mode != DDmode)))
&& (TARGET_POWERPC64 || mode != DImode)
+ && !avoiding_indexed_address_p (mode)
&& mode != TImode
&& mode != TFmode
&& mode != TDmode)
@@ -4441,6 +4457,7 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
|| (mode != DFmode && mode != DDmode)
|| (TARGET_E500_DOUBLE && mode != DDmode))
&& (TARGET_POWERPC64 || mode != DImode)
+ && !avoiding_indexed_address_p (mode)
&& legitimate_indexed_address_p (x, reg_ok_strict))
return 1;
if (GET_CODE (x) == PRE_MODIFY
@@ -4459,7 +4476,8 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
&& TARGET_UPDATE
&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
&& (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
- || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
+ || (!avoiding_indexed_address_p (mode)
+ && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
return 1;
if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a5a6ec17b26..b6f41814eba 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -10055,7 +10055,9 @@
(match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
(set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
(plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && TARGET_UPDATE"
+ "TARGET_POWERPC64 && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (DImode)
+ || !gpc_reg_operand (operands[2], DImode))"
"@
ldux %3,%0,%2
ldu %3,%2(%0)"
@@ -10067,7 +10069,11 @@
(match_operand:DI 3 "gpc_reg_operand" "r,r"))
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
(plus:P (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && TARGET_UPDATE"
+ "TARGET_POWERPC64 && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (Pmode)
+ || !gpc_reg_operand (operands[2], Pmode)
+ || (REG_P (operands[0])
+ && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
"@
stdux %3,%0,%2
stdu %3,%2(%0)"
@@ -10079,7 +10085,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
{lux|lwzux} %3,%0,%2
{lu|lwzu} %3,%2(%0)"
@@ -10092,7 +10100,8 @@
(match_operand:DI 2 "gpc_reg_operand" "r")))))
(set (match_operand:DI 0 "gpc_reg_operand" "=b")
(plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
+ "TARGET_POWERPC64 && rs6000_gen_cell_microcode
+ && !avoiding_indexed_address_p (DImode)"
"lwaux %3,%0,%2"
[(set_attr "type" "load_ext_ux")])
@@ -10102,7 +10111,11 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode)
+ || (REG_P (operands[0])
+ && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
"@
{stux|stwux} %3,%0,%2
{stu|stwu} %3,%2(%0)"
@@ -10114,7 +10127,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lhzux %3,%0,%2
lhzu %3,%2(%0)"
@@ -10127,7 +10142,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lhzux %3,%0,%2
lhzu %3,%2(%0)"
@@ -10140,7 +10157,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE && rs6000_gen_cell_microcode"
+ "TARGET_UPDATE && rs6000_gen_cell_microcode
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lhaux %3,%0,%2
lhau %3,%2(%0)"
@@ -10152,7 +10171,9 @@
(match_operand:HI 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
sthux %3,%0,%2
sthu %3,%2(%0)"
@@ -10164,7 +10185,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lbzux %3,%0,%2
lbzu %3,%2(%0)"
@@ -10177,7 +10200,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lbzux %3,%0,%2
lbzu %3,%2(%0)"
@@ -10189,7 +10214,9 @@
(match_operand:QI 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE"
+ "TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
stbux %3,%0,%2
stbu %3,%2(%0)"
@@ -10201,7 +10228,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lfsux %3,%0,%2
lfsu %3,%2(%0)"
@@ -10213,7 +10242,9 @@
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
stfsux %3,%0,%2
stfsu %3,%2(%0)"
@@ -10225,7 +10256,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
+ "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
{lux|lwzux} %3,%0,%2
{lu|lwzu} %3,%2(%0)"
@@ -10237,7 +10270,9 @@
(match_operand:SF 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
+ "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
{stux|stwux} %3,%0,%2
{stu|stwu} %3,%2(%0)"
@@ -10249,7 +10284,9 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
lfdux %3,%0,%2
lfdu %3,%2(%0)"
@@ -10261,7 +10298,9 @@
(match_operand:DF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ && (!avoiding_indexed_address_p (SImode)
+ || !gpc_reg_operand (operands[2], SImode))"
"@
stfdux %3,%0,%2
stfdu %3,%2(%0)"
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 8a40fc3539b..ec5373eb877 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -119,6 +119,10 @@ mupdate
Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
Generate load/store with update instructions
+mavoid-indexed-addresses
+Target Report Var(TARGET_AVOID_XFORM) Init(-1)
+Avoid generation of indexed load/store instructions when possible
+
mno-fused-madd
Target Report RejectNegative Mask(NO_FUSED_MADD)
Do not generate fused multiply/add instructions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index e8b50830d58..9c21977d506 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -558,7 +558,8 @@
"@
tmh\t%0,%i1
tml\t%0,%i1"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tm<mode>_full"
[(set (reg CC_REGNUM)
@@ -566,7 +567,8 @@
(match_operand:HQI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
"tml\t%0,<max_uint>"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super")])
;
@@ -604,7 +606,7 @@
lt<g>r\t%2,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
- (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ])
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm"
@@ -617,7 +619,7 @@
lt<g>r\t%0,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
- (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")])
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
(define_insn "*tstdi"
[(set (reg CC_REGNUM)
@@ -715,7 +717,7 @@
cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")
- (set_attr "z10prop" "z10_super,z10_super,*")])
+ (set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>"
[(set (reg CC_REGNUM)
@@ -856,7 +858,8 @@
"s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
"clhrl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "larl")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super")])
; clhrl, clghrl
(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
@@ -1003,7 +1006,7 @@
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
+; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
(compare (match_operand:FP 0 "register_operand" "f,f")
@@ -1527,7 +1530,7 @@
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_super_A1")])
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
@@ -1593,7 +1596,7 @@
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
- z10_super,
+ z10_rec,
z10_rec,
*,
*,
@@ -1628,7 +1631,7 @@
(set_attr "z10prop" "z10_fwd_A1,
z10_fr_E1,
z10_fwd_A3,
- z10_super,
+ z10_rec,
*,
*,
*,
@@ -1766,7 +1769,7 @@
z10_super_E1,
z10_super_E1,
z10_super_E1,
- z10_super,
+ z10_rec,
z10_rec,
z10_rec,
z10_super")])
@@ -1822,7 +1825,7 @@
z10_fwd_A1,
z10_super_E1,
z10_super_E1,
- z10_super,
+ z10_rec,
z10_rec,
z10_super,
z10_super")])
@@ -1849,7 +1852,7 @@
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super")])
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstricthi instruction pattern(s).
@@ -2167,7 +2170,7 @@
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
- z10_super,
+ z10_rec,
z10_rec")])
;
@@ -2188,7 +2191,7 @@
ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,store,store,load,load")
- (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")])
+ (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
;
; Block move (MVC) patterns.
@@ -3153,7 +3156,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"icmh\t%0,%2,%S1"
- [(set_attr "op_type" "RSY")])
+ [(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
(define_insn "*sethighpartdi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3696,7 +3700,7 @@
[(set_attr "op_type" "RXY,RRE,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
- (set_attr "z10prop" "z10_fwd_A3")])
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
@@ -4873,7 +4877,7 @@
; sub(tf|df|sf|td|dd)3 instruction pattern(s).
;
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "sub<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f, f")
(minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
@@ -4886,7 +4890,7 @@
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
@@ -4901,7 +4905,7 @@
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
@@ -6630,7 +6634,8 @@
(neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -6638,7 +6643,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
; lcr, lcgr
(define_insn "*neg<mode>2_cc"
@@ -6774,7 +6780,8 @@
(abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -6782,7 +6789,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
; lpr, lpgr
(define_insn "*abs<mode>2_cc"
@@ -6890,7 +6898,8 @@
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -6899,7 +6908,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lngfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
; lnr, lngr
(define_insn "*negabs<mode>2_cc"
@@ -7516,7 +7526,7 @@
c<g>it%C0\t%1,%h2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
- (set_attr "z10prop" "z10_c,*")])
+ (set_attr "z10prop" "z10_super_c,z10_super")])
; clrt, clgrt, clfit, clgit
(define_insn "*cmp_and_trap_unsigned_int<mode>"
@@ -7530,7 +7540,7 @@
cl<gf>it%C0\t%1,%x2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
- (set_attr "z10prop" "z10_c,*")])
+ (set_attr "z10prop" "z10_super_c,z10_super")])
;;
;;- Loop instructions.
@@ -7594,7 +7604,7 @@
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
- (set_attr "z10prop" "z10_super")
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
@@ -7636,7 +7646,7 @@
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
- (set_attr "z10prop" "z10_super")
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
@@ -7667,7 +7677,8 @@
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
- (set_attr "atype" "agen")])
+ (set_attr "atype" "agen")
+ (set_attr "z10prop" "z10_cobra")])
(define_insn_and_split "doloop_di"
[(set (pc)
@@ -7705,7 +7716,7 @@
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
- (set_attr "z10prop" "z10_super")
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
@@ -7772,8 +7783,7 @@
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
- (set_attr "atype" "agen")
- (set_attr "z10prop" "z10_super")])
+ (set_attr "atype" "agen")])
;
; casesi instruction pattern(s).
@@ -8129,6 +8139,7 @@
l\t%0,%1%J2
ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "load")
(set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
(define_insn "*bras_tls"
@@ -8468,7 +8479,8 @@
[(const_int 0)]
""
"lr\t0,0"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "z10prop" "z10_fr_E1")])
(define_insn "nop1"
[(const_int 1)]
@@ -8536,7 +8548,7 @@
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_super_A1")])
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "main_pool"
[(set (match_operand 0 "register_operand" "=a")
@@ -8564,7 +8576,7 @@
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_super_A1")])
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
@@ -8729,3 +8741,19 @@
[(set_attr "type" "load,larl")
(set_attr "op_type" "RXY,RIL")
(set_attr "z10prop" "z10_super")])
+
+
+;
+; Byte swap instructions
+;
+
+(define_insn "bswap<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
+ ""
+ "@
+ lrv<g>r\t%0,%1
+ lrv<g>\t%0,%1"
+ [(set_attr "type" "*,load")
+ (set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super")])
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
index 9014ae54ca6..4d8db56518f 100644
--- a/gcc/config/sparc/linux.h
+++ b/gcc/config/sparc/linux.h
@@ -102,10 +102,6 @@ along with GCC; see the file COPYING3. If not see
"%{V} %{v:%{!V:-V}} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \
%{fpic|fPIC|fpie|fPIE:-K PIC} %(asm_cpu) %(asm_relax)"
-/* Same as sparc.h */
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
#undef ASM_OUTPUT_ALIGNED_LOCAL
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
do { \
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index 4971048a31d..8155c1af8cb 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -239,10 +239,6 @@ along with GCC; see the file COPYING3. If not see
%{mlittle-endian:-EL} \
%(asm_cpu) %(asm_arch) %(asm_relax)"
-/* Same as sparc.h */
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
#undef ASM_OUTPUT_ALIGNED_LOCAL
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
do { \
diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h
index 586c2399ae6..1c60debf850 100644
--- a/gcc/config/sparc/sysv4.h
+++ b/gcc/config/sparc/sysv4.h
@@ -93,22 +93,6 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \
fprintf (FILE, "\n"); \
} while (0)
-/* Define how the SPARC registers should be numbered for Dwarf output.
- The numbering provided here should be compatible with the native
- svr4 SDB debugger in the SPARC/svr4 reference port. The numbering
- is as follows:
-
- Assembly name gcc internal regno Dwarf regno
- ----------------------------------------------------------
- g0-g7 0-7 0-7
- o0-o7 8-15 8-15
- l0-l7 16-23 16-23
- i0-i7 24-31 24-31
- f0-f31 32-63 40-71
-*/
-
-#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 32 ? (REGNO) : (REGNO) + 8)
-
/* A set of symbol definitions for assembly pseudo-ops which will
get us switched to various sections of interest. These are used
in all places where we simply want to switch to a section, and
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