3 files changed, 7 insertions, 8 deletions
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index fb6913f2d60..7ff8cb870cd 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1453,7 +1453,7 @@ s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
 static struct machine_function *
 s390_init_machine_status (void)
 {
-  return GGC_CNEW (struct machine_function);
+  return ggc_alloc_cleared_machine_function ();
 }
 
 /* Change optimizations to be performed, depending on the
@@ -2957,10 +2957,12 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
    RCLASS requires an extra scratch or immediate register.  Return the class
    needed for the immediate register.  */
 
-static enum reg_class
-s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
 		       enum machine_mode mode, secondary_reload_info *sri)
 {
+  enum reg_class rclass = (enum reg_class) rclass_i;
+
   /* Intermediate register needed.  */
   if (reg_classes_intersect_p (CC_REGS, rclass))
     return GENERAL_REGS;
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 1d74d30c000..cbe28991c18 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -673,9 +673,6 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 /* We need current_function_outgoing_args to be valid.  */
 #define ACCUMULATE_OUTGOING_ARGS 1
 
-/* Return doesn't modify the stack.  */
-#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
-
 
 /* Register arguments.  */
 
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index df7e3dd71e2..f78af00a11c 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2079,7 +2079,7 @@
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
    (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
                      fstore<mode>,fstore<mode>,lr,load,store")
-   (set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
+   (set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
@@ -2168,7 +2168,7 @@
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
    (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
                      fstore<mode>,fstore<mode>,lr,load,load,store,store")
-   (set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
+   (set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
 
 ;
 ; movcc instruction pattern