diff options
Diffstat (limited to 'gcc/config/s390/s390.md')
-rw-r--r-- | gcc/config/s390/s390.md | 378 |
1 files changed, 158 insertions, 220 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 4cda1480cab..01a9904b068 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -429,8 +429,7 @@ (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") (match_operand:DI 1 "immediate_operand" "n,n")) (match_operand:DI 2 "immediate_operand" "n,n")))] - "TARGET_64BIT - && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) + "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) && s390_single_qi (operands[1], DImode, 0) >= 0" { int part = s390_single_qi (operands[1], DImode, 0); @@ -1237,7 +1236,7 @@ (define_insn "*movsi_lli" [(set (match_operand:SI 0 "register_operand" "=d") (match_operand:SI 1 "immediate_operand" "n"))] - "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 + "TARGET_ZARCH && s390_single_hi (operands[1], SImode, 0) >= 0 && !FP_REG_P (operands[0])" { int part = s390_single_hi (operands[1], SImode, 0); @@ -1262,6 +1261,15 @@ [(set_attr "op_type" "RXY") (set_attr "type" "la")]) +(define_insn "*movsi_larl" + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "larl_operand" "X"))] + "!TARGET_64BIT && TARGET_CPU_ZARCH + && !FP_REG_P (operands[0])" + "larl\t%0,%1" + [(set_attr "op_type" "RIL") + (set_attr "type" "larl")]) + (define_insn "*movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))] @@ -2356,14 +2364,14 @@ (define_insn "*extendqisi2" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" + "TARGET_LONG_DISPLACEMENT" "lb\t%0,%1" [(set_attr "op_type" "RXY")]) (define_split [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] - "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed" + "!TARGET_LONG_DISPLACEMENT && !reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) (clobber (reg:CC 33))]) @@ -2601,14 +2609,14 @@ (define_insn "*zero_extendqisi2_64" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT" + "TARGET_ZARCH" "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) @@ -2623,7 +2631,7 @@ (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] - "TARGET_64BIT" + "TARGET_ZARCH" " { operands[1] = gen_lowpart (HImode, operands[1]); @@ -2635,14 +2643,14 @@ (define_insn "*zero_extendqihi2_64" [(set (match_operand:HI 0 "register_operand" "=d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT" + "TARGET_ZARCH" "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) @@ -4787,7 +4795,7 @@ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] - "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" + "TARGET_ZARCH && s390_single_hi (operands[2], SImode, -1) >= 0" { int part = s390_single_hi (operands[2], SImode, -1); operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); @@ -4840,7 +4848,7 @@ (and:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ nr\t%0,%2 nill\t%0,%x2" @@ -4882,7 +4890,7 @@ (and:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ nr\t%0,%2 nill\t%0,%b2" @@ -5041,7 +5049,7 @@ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] - "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" + "TARGET_ZARCH && s390_single_hi (operands[2], SImode, 0) >= 0" { int part = s390_single_hi (operands[2], SImode, 0); operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); @@ -5094,7 +5102,7 @@ (ior:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ or\t%0,%2 oill\t%0,%x2" @@ -5136,7 +5144,7 @@ (ior:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ or\t%0,%2 oill\t%0,%b2" @@ -5733,7 +5741,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (rotate:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "nonmemory_operand" "J,a")))] - "TARGET_64BIT" + "TARGET_CPU_ZARCH" "@ rll\t%0,%1,%c2 rll\t%0,%1,0(%2)" @@ -6164,7 +6172,7 @@ { if (get_attr_length (insn) == 4) return "j%C1\t%l0"; - else if (TARGET_64BIT) + else if (TARGET_CPU_ZARCH) return "jg%C1\t%l0"; else abort (); @@ -6174,7 +6182,7 @@ (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6213,7 +6221,7 @@ { if (get_attr_length (insn) == 4) return "j%D1\t%l0"; - else if (TARGET_64BIT) + else if (TARGET_CPU_ZARCH) return "jg%D1\t%l0"; else abort (); @@ -6223,7 +6231,7 @@ (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6332,7 +6340,7 @@ (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 10) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6473,7 +6481,7 @@ { if (get_attr_length (insn) == 4) return "j\t%l0"; - else if (TARGET_64BIT) + else if (TARGET_CPU_ZARCH) return "jg\t%l0"; else abort (); @@ -6483,7 +6491,7 @@ (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6625,6 +6633,7 @@ (use (match_operand 2 "" ""))] "" { + bool plt_call = false; rtx insn; /* Direct function calls need special treatment. */ @@ -6638,11 +6647,12 @@ { sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_CONST (Pmode, sym); + plt_call = true; } /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) { if (flag_pic) sym = legitimize_pic_address (sym, 0); @@ -6656,6 +6666,11 @@ /* Emit insn. */ insn = emit_call_insn (gen_call_exp (operands[0], operands[1], gen_rtx_REG (Pmode, RETURN_REGNUM))); + + /* 31-bit PLT stubs use the GOT register implicitly. */ + if (!TARGET_64BIT && plt_call) + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); + DONE; }) @@ -6666,62 +6681,40 @@ "" "") -(define_insn "brasl" - [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "brasl\t%2,%0" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras" - [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "TARGET_SMALL_EXEC" +(define_insn "*bras" + [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode" "bras\t%2,%0" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_64" - [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "basr\t%2,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "basr_31" - [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "!TARGET_64BIT" - "basr\t%2,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_64" - [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "bas\t%2,%a0" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr")]) - -(define_insn "bas_31" - [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "!TARGET_64BIT" - "bas\t%2,%a0" - [(set_attr "op_type" "RX") +(define_insn "*brasl" + [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode" + "brasl\t%2,%0" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) +(define_insn "*basr" + [(call (mem:QI (match_operand 0 "address_operand" "U")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "GET_MODE (operands[2]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%2,%0"; + else + return "bas\t%2,%a0"; +} + [(set (attr "op_type") + (if_then_else (match_operand 0 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ; ; call_value instruction pattern(s). @@ -6734,6 +6727,7 @@ (use (match_operand 3 "" ""))] "" { + bool plt_call = false; rtx insn; /* Direct function calls need special treatment. */ @@ -6747,11 +6741,12 @@ { sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_CONST (Pmode, sym); + plt_call = true; } /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) { if (flag_pic) sym = legitimize_pic_address (sym, 0); @@ -6766,6 +6761,11 @@ insn = emit_call_insn ( gen_call_value_exp (operands[0], operands[1], operands[2], gen_rtx_REG (Pmode, RETURN_REGNUM))); + + /* 31-bit PLT stubs use the GOT register implicitly. */ + if (!TARGET_64BIT && plt_call) + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); + DONE; }) @@ -6777,68 +6777,43 @@ "" "") -(define_insn "brasl_r" +(define_insn "*bras_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "brasl\t%3,%1" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras_r" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "TARGET_SMALL_EXEC" + (clobber (match_operand 3 "register_operand" "=r"))] + "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" "bras\t%3,%1" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_r_64" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "basr\t%3,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "basr_r_31" +(define_insn "*brasl_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "!TARGET_64BIT" - "basr\t%3,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_r_64" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "bas\t%3,%a1" - [(set_attr "op_type" "RX") + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r"))] + "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" + "brasl\t%3,%1" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) -(define_insn "bas_r_31" +(define_insn "*basr_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "!TARGET_64BIT" - "bas\t%3,%a1" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr")]) - + (call (mem:QI (match_operand 1 "address_operand" "U")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r"))] + "GET_MODE (operands[3]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%3,%1"; + else + return "bas\t%3,%a1"; +} + [(set (attr "op_type") + (if_then_else (match_operand 1 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ;; ;;- Thread-local storage support. @@ -6922,7 +6897,7 @@ /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) { if (flag_pic) sym = legitimize_pic_address (sym, 0); @@ -6956,74 +6931,46 @@ "" "") -(define_insn "brasl_tls" +(define_insn "*bras_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "brasl\t%3,%1%J4" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras_tls" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "TARGET_SMALL_EXEC" + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" "bras\t%3,%1%J4" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_tls_64" +(define_insn "*brasl_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "basr\t%3,%1%J4" - [(set_attr "op_type" "RR") + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" + "brasl\t%3,%1%J4" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) -(define_insn "basr_tls_31" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "!TARGET_64BIT" - "basr\t%3,%1%J4" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_tls_64" +(define_insn "*basr_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "bas\t%3,%a1%J4" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_tls_31" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "!TARGET_64BIT" - "bas\t%3,%a1%J4" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) + (call (mem:QI (match_operand 1 "address_operand" "U")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "GET_MODE (operands[3]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%3,%1%J4"; + else + return "bas\t%3,%a1%J4"; +} + [(set (attr "op_type") + (if_then_else (match_operand 1 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ;; ;;- Miscellaneous instructions. @@ -7207,52 +7154,52 @@ (define_insn "pool_start_31" [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] - "!TARGET_64BIT" + "!TARGET_CPU_ZARCH" ".align\t4" [(set_attr "op_type" "NN") (set_attr "length" "2")]) (define_insn "pool_end_31" [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] - "!TARGET_64BIT" + "!TARGET_CPU_ZARCH" ".align\t2" [(set_attr "op_type" "NN") (set_attr "length" "2")]) (define_insn "pool_start_64" [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] - "TARGET_64BIT" + "TARGET_CPU_ZARCH" ".section\t.rodata\;.align\t8" [(set_attr "op_type" "NN") (set_attr "length" "0")]) (define_insn "pool_end_64" [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] - "TARGET_64BIT" + "TARGET_CPU_ZARCH" ".previous" [(set_attr "op_type" "NN") (set_attr "length" "0")]) (define_insn "main_base_31_small" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] - "!TARGET_64BIT" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "basr\t%0,0" [(set_attr "op_type" "RR") (set_attr "type" "la")]) (define_insn "main_base_31_large" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) (set (pc) (label_ref (match_operand 2 "" "")))] - "!TARGET_64BIT" + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "bras\t%0,%2" [(set_attr "op_type" "RI")]) (define_insn "main_base_64" - [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] - "TARGET_64BIT" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] + "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl")]) @@ -7264,18 +7211,18 @@ [(set_attr "op_type" "NN")]) (define_insn "reload_base_31" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] - "!TARGET_64BIT" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "basr\t%0,0\;la\t%0,%1-.(%0)" [(set_attr "op_type" "NN") (set_attr "type" "la") (set_attr "length" "6")]) (define_insn "reload_base_64" - [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] - "TARGET_64BIT" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] + "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl")]) @@ -7302,24 +7249,15 @@ "" "s390_emit_epilogue (); DONE;") - -(define_insn "*return_si" +(define_insn "*return" [(return) - (use (match_operand:SI 0 "register_operand" "a"))] - "!TARGET_64BIT" + (use (match_operand 0 "register_operand" "a"))] + "GET_MODE (operands[0]) == Pmode" "br\t%0" [(set_attr "op_type" "RR") (set_attr "type" "jsr") (set_attr "atype" "agen")]) -(define_insn "*return_di" - [(return) - (use (match_operand:DI 0 "register_operand" "a"))] - "TARGET_64BIT" - "br\t%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) ;; Instruction definition to extend a 31-bit pointer into a 64-bit ;; pointer. This is used for compatability. @@ -7327,7 +7265,7 @@ (define_expand "ptr_extend" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r"))] - "" + "TARGET_64BIT" { emit_insn (gen_anddi3 (operands[0], gen_lowpart (DImode, operands[1]), |