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-rw-r--r--gcc/config/rs6000/altivec.md85
-rw-r--r--gcc/config/rs6000/darwin.md20
-rw-r--r--gcc/config/rs6000/rs6000.c23
-rw-r--r--gcc/config/rs6000/rs6000.h2
-rw-r--r--gcc/config/rs6000/rs6000.md156
-rw-r--r--gcc/config/rs6000/spe.md6
-rw-r--r--gcc/config/rs6000/vector.md16
-rw-r--r--gcc/config/rs6000/vsx.md6
8 files changed, 162 insertions, 152 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index c39a0b655b4..857f257edda 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -371,7 +371,7 @@
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
+ (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
@@ -383,9 +383,9 @@
(define_insn "*set_vrsave_internal"
[(match_parallel 0 "vrsave_operation"
- [(set (reg:SI 109)
+ [(set (reg:SI VRSAVE_REGNO)
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
- (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
+ (reg:SI VRSAVE_REGNO)] UNSPECV_SET_VRSAVE))])]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
@@ -397,7 +397,7 @@
(define_insn "*save_world"
[(match_parallel 0 "save_world_operation"
- [(clobber (reg:SI 65))
+ [(clobber (reg:SI LR_REGNO))
(use (match_operand:SI 1 "call_operand" "s"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
"bl %z1"
@@ -407,7 +407,7 @@
(define_insn "*restore_world"
[(match_parallel 0 "restore_world_operation"
[(return)
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(use (match_operand:SI 1 "call_operand" "s"))
(clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
@@ -421,7 +421,7 @@
;; to describe the operation to dwarf2out_frame_debug_expr.
(define_insn "*save_vregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(clobber (reg:P 11))
(use (reg:P 0))
@@ -435,7 +435,7 @@
(define_insn "*save_vregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(clobber (reg:P 12))
(use (reg:P 0))
@@ -449,7 +449,7 @@
(define_insn "*restore_vregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(clobber (reg:P 11))
(use (reg:P 0))
@@ -463,7 +463,7 @@
(define_insn "*restore_vregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(clobber (reg:P 12))
(use (reg:P 0))
@@ -508,7 +508,7 @@
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VADDU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"<VI_unit>"
"vaddu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -518,7 +518,7 @@
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VADDS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vadds<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -554,7 +554,7 @@
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VSUBU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vsubu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -564,7 +564,7 @@
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VSUBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vsubs<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -830,7 +830,7 @@
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")]
UNSPEC_VMSUMUHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmsumuhs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -841,7 +841,7 @@
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")]
UNSPEC_VMSUMSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmsumshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -902,7 +902,7 @@
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V8HI 3 "register_operand" "v")]
UNSPEC_VMHADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmhaddshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -913,7 +913,7 @@
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V8HI 3 "register_operand" "v")]
UNSPEC_VMHRADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmhraddshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -1699,7 +1699,7 @@
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM4UBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1709,7 +1709,7 @@
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM4S))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsum4s<VI_char>s %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1722,7 +1722,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM2SWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
(clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
{
@@ -1743,7 +1743,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUMSWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
(clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
{
@@ -1764,7 +1764,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUMSWS_DIRECT))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -2124,7 +2124,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_VCTUXS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vctuxs %0,%1,%2"
[(set_attr "type" "vecfloat")])
@@ -2134,7 +2134,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_VCTSXS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vctsxs %0,%1,%2"
[(set_attr "type" "vecfloat")])
@@ -2274,7 +2274,7 @@
;; Compare vectors producing a vector result and a predicate, setting CR6 to
;; indicate a combined status
(define_insn "*altivec_vcmpequ<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2286,7 +2286,7 @@
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgts<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2298,7 +2298,7 @@
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgtu<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2310,7 +2310,7 @@
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpeqfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2322,7 +2322,7 @@
[(set_attr "type" "veccmp")])
(define_insn "*altivec_vcmpgtfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2334,7 +2334,7 @@
[(set_attr "type" "veccmp")])
(define_insn "*altivec_vcmpgefp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2346,7 +2346,7 @@
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpbfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")]
UNSPEC_VCMPBFP))
@@ -2359,7 +2359,7 @@
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
- [(set (reg:SI 110)
+ [(set (reg:SI VSCR_REGNO)
(unspec_volatile:SI
[(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
"TARGET_ALTIVEC"
@@ -2368,7 +2368,7 @@
(define_insn "altivec_mfvscr"
[(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
+ (unspec_volatile:V8HI [(reg:SI VSCR_REGNO)] UNSPECV_MFVSCR))]
"TARGET_ALTIVEC"
"mfvscr %0"
[(set_attr "type" "vecsimple")])
@@ -2757,7 +2757,8 @@
(unspec:VI [(match_dup 2)
(match_operand:VI 1 "register_operand" "v")]
UNSPEC_VSUBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
+ (set (reg:SI VSCR_REGNO)
+ (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
(set (match_operand:VI 0 "register_operand" "=v")
(smax:VI (match_dup 1) (match_dup 3)))]
"TARGET_ALTIVEC"
@@ -3634,7 +3635,7 @@
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
UNSPEC_BCD_ADD_SUB))
- (clobber (reg:CCFP 74))]
+ (clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4")
@@ -3646,7 +3647,7 @@
;; probably should be one that can go in the VMX (Altivec) registers, so we
;; can't use DDmode or DFmode.
(define_insn "*bcd<bcd_add_sub>_test"
- [(set (reg:CCFP 74)
+ [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")
(match_operand:V1TI 2 "register_operand" "v")
@@ -3665,7 +3666,7 @@
(match_operand:V1TI 2 "register_operand" "v")
(match_operand:QI 3 "const_0_to_1_operand" "i")]
UNSPEC_BCD_ADD_SUB))
- (set (reg:CCFP 74)
+ (set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
@@ -3699,7 +3700,7 @@
[(set_attr "type" "integer")])
(define_expand "bcd<bcd_add_sub>_<code>"
- [(parallel [(set (reg:CCFP 74)
+ [(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
(match_operand:V1TI 2 "register_operand" "")
@@ -3708,7 +3709,7 @@
(match_dup 4)))
(clobber (match_scratch:V1TI 5 ""))])
(set (match_operand:SI 0 "register_operand" "")
- (BCD_TEST:SI (reg:CCFP 74)
+ (BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
{
@@ -3727,8 +3728,8 @@
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
UNSPEC_BCD_ADD_SUB))
- (clobber (reg:CCFP 74))])
- (parallel [(set (reg:CCFP 74)
+ (clobber (reg:CCFP CR6_REGNO))])
+ (parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
@@ -3742,7 +3743,7 @@
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB))
- (set (reg:CCFP 74)
+ (set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index 57ce30e0cd1..5870e0a762f 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -238,7 +238,7 @@ You should have received a copy of the GNU General Public License
"")
(define_expand "load_macho_picbase"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
@@ -252,7 +252,7 @@ You should have received a copy of the GNU General Public License
})
(define_insn "load_macho_picbase_si"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
(pc)] UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
@@ -268,7 +268,7 @@ You should have received a copy of the GNU General Public License
(set_attr "length" "4")])
(define_insn "load_macho_picbase_di"
- [(set (reg:DI 65)
+ [(set (reg:DI LR_REGNO)
(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
(pc)] UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
@@ -325,7 +325,7 @@ You should have received a copy of the GNU General Public License
[(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
(match_operand 1 "" "g,g,g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
{
return "b%T0l";
@@ -337,7 +337,7 @@ You should have received a copy of the GNU General Public License
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN)
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
{
@@ -355,7 +355,7 @@ You should have received a copy of the GNU General Public License
(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
(match_operand 2 "" "g,g,g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_DARWIN"
{
return "b%T1l";
@@ -368,7 +368,7 @@ You should have received a copy of the GNU General Public License
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN)
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
{
@@ -382,7 +382,7 @@ You should have received a copy of the GNU General Public License
(set_attr "length" "4,8")])
(define_expand "reload_macho_picbase"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
@@ -396,7 +396,7 @@ You should have received a copy of the GNU General Public License
})
(define_insn "reload_macho_picbase_si"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
(pc)] UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
@@ -419,7 +419,7 @@ You should have received a copy of the GNU General Public License
(set_attr "length" "4")])
(define_insn "reload_macho_picbase_di"
- [(set (reg:DI 65)
+ [(set (reg:DI LR_REGNO)
(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
(pc)] UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2f15a053075..ed24d96006f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8409,7 +8409,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
pointer, so it works with both GPRs and VSX registers. */
/* Make sure both operands are registers. */
else if (GET_CODE (x) == PLUS
- && (mode != TImode || !TARGET_QUAD_MEMORY))
+ && (mode != TImode || !TARGET_VSX_TIMODE))
return gen_rtx_PLUS (Pmode,
force_reg (Pmode, XEXP (x, 0)),
force_reg (Pmode, XEXP (x, 1)));
@@ -9418,12 +9418,16 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
return 1;
}
- /* For TImode, if we have load/store quad and TImode in VSX registers, only
- allow register indirect addresses. This will allow the values to go in
- either GPRs or VSX registers without reloading. The vector types would
- tend to go into VSX registers, so we allow REG+REG, while TImode seems
+ /* For TImode, if we have TImode in VSX registers, only allow register
+ indirect addresses. This will allow the values to go in either GPRs
+ or VSX registers without reloading. The vector types would tend to
+ go into VSX registers, so we allow REG+REG, while TImode seems
somewhat split, in that some uses are GPR based, and some VSX based. */
- if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
+ /* FIXME: We could loosen this by changing the following to
+ if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
+ but currently we cannot allow REG+REG addressing for TImode. See
+ PR72827 for complete details on how this ends up hoodwinking DSE. */
+ if (mode == TImode && TARGET_VSX_TIMODE)
return 0;
/* If not REG_OK_STRICT (before reload) let pass any stack offset. */
if (! reg_ok_strict
@@ -39097,10 +39101,15 @@ rtx_is_swappable_p (rtx op, unsigned int *special)
handling. */
if (GET_CODE (XEXP (op, 0)) == CONST_INT)
return 1;
- else if (GET_CODE (XEXP (op, 0)) == REG
+ else if (REG_P (XEXP (op, 0))
&& GET_MODE_INNER (GET_MODE (op)) == GET_MODE (XEXP (op, 0)))
/* This catches V2DF and V2DI splat, at a minimum. */
return 1;
+ else if (GET_CODE (XEXP (op, 0)) == TRUNCATE
+ && REG_P (XEXP (XEXP (op, 0), 0))
+ && GET_MODE_INNER (GET_MODE (op)) == GET_MODE (XEXP (op, 0)))
+ /* This catches splat of a truncated value. */
+ return 1;
else if (GET_CODE (XEXP (op, 0)) == VEC_SELECT)
/* If the duplicated item is from a select, defer to the select
processing to see if we can change the lane for the splat. */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d54eaa1b5a2..446d388469e 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1958,7 +1958,7 @@ typedef struct rs6000_args
#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
/* Definitions for __builtin_return_address and __builtin_frame_address.
- __builtin_return_address (0) should give link register (65), enable
+ __builtin_return_address (0) should give link register (LR_REGNO), enable
this. */
/* This should be uncommented, so that the link register is used, but
currently this would result in unmatched insns and spilling fixed
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 560cf1fd740..8d09c8cd2dd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4323,13 +4323,15 @@
;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
;; hardware division. This is only done before register allocation and with
;; -ffast-math. This must appear before the divsf3/divdf3 insns.
+;; We used to also check optimize_insn_for_speed_p () but problems with guessed
+;; frequencies (pr68212/pr77536) yields that unreliable so it was removed.
(define_split
[(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
(div:RECIPF (match_operand 1 "gpc_reg_operand" "")
(match_operand 2 "gpc_reg_operand" "")))]
"RS6000_RECIP_AUTO_RE_P (<MODE>mode)
- && can_create_pseudo_p () && optimize_insn_for_speed_p ()
- && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
+ && can_create_pseudo_p () && flag_finite_math_only
+ && !flag_trapping_math && flag_reciprocal_math"
[(const_int 0)]
{
rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
@@ -12455,7 +12457,7 @@
(define_insn "*save_gpregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "memory_operand" "=m")
@@ -12467,7 +12469,7 @@
(define_insn "*save_gpregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "memory_operand" "=m")
@@ -12479,7 +12481,7 @@
(define_insn "*save_gpregs_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "memory_operand" "=m")
@@ -12491,7 +12493,7 @@
(define_insn "*save_fpregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "memory_operand" "=m")
@@ -12503,7 +12505,7 @@
(define_insn "*save_fpregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:DF 2 "memory_operand" "=m")
@@ -12515,7 +12517,7 @@
(define_insn "*save_fpregs_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "memory_operand" "=m")
@@ -12620,141 +12622,139 @@
(define_insn "*restore_gpregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 11))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "bl %2"
+ "bl %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*restore_gpregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 12))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 12))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "bl %2"
+ "bl %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*restore_gpregs_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 1))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 1))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "bl %2"
+ "bl %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_gpregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 11))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_gpregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 12))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 12))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_gpregs_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 1))
- (set (match_operand:P 3 "gpc_reg_operand" "=r")
- (match_operand:P 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 1))
+ (set (match_operand:P 2 "gpc_reg_operand" "=r")
+ (match_operand:P 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_fpregs_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
- (set (match_operand:DF 3 "gpc_reg_operand" "=d")
- (match_operand:DF 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 11))
+ (set (match_operand:DF 2 "gpc_reg_operand" "=d")
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_fpregs_<mode>_r12"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 12))
- (set (match_operand:DF 3 "gpc_reg_operand" "=d")
- (match_operand:DF 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 12))
+ (set (match_operand:DF 2 "gpc_reg_operand" "=d")
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_fpregs_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
- [(return)
- (clobber (match_operand:P 1 "register_operand" "=l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 1))
- (set (match_operand:DF 3 "gpc_reg_operand" "=d")
- (match_operand:DF 4 "memory_operand" "m"))])]
+ [(return)
+ (clobber (reg:P LR_REGNO))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
+ (use (reg:P 1))
+ (set (match_operand:DF 2 "gpc_reg_operand" "=d")
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
[(match_parallel 0 "any_parallel_operand"
[(return)
- (use (match_operand:P 1 "register_operand" "l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:DF 3 "gpc_reg_operand" "=d")
- (match_operand:DF 4 "memory_operand" "m"))])]
+ (set (match_operand:DF 2 "gpc_reg_operand" "=d")
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
[(match_parallel 0 "any_parallel_operand"
[(return)
- (use (match_operand:P 1 "register_operand" "l"))
- (use (match_operand:P 2 "symbol_ref_operand" "s"))
+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:DF 3 "gpc_reg_operand" "=d")
- (match_operand:DF 4 "memory_operand" "m"))])]
+ (set (match_operand:DF 2 "gpc_reg_operand" "=d")
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
- "b %2"
+ "b %1"
[(set_attr "type" "branch")
(set_attr "length" "4")])
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 87fb787a1c1..4b2220d38bb 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -3464,7 +3464,7 @@
;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:V2SI 2 "memory_operand" "=m")
@@ -3476,7 +3476,7 @@
(define_insn "*restore_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
- [(clobber (reg:P 65))
+ [(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
@@ -3489,7 +3489,7 @@
(define_insn "*return_and_restore_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
[(return)
- (clobber (reg:P 65))
+ (clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index fbfa9bf12e4..d42de0f9d3c 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -670,7 +670,7 @@
;; setting CR6 to indicate a combined status
(define_expand "vector_eq_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
UNSPEC_PREDICATE))
@@ -682,7 +682,7 @@
(define_expand "vector_gt_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
UNSPEC_PREDICATE))
@@ -694,7 +694,7 @@
(define_expand "vector_ge_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" ""))]
UNSPEC_PREDICATE))
@@ -706,7 +706,7 @@
(define_expand "vector_gtu_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" ""))]
UNSPEC_PREDICATE))
@@ -720,14 +720,14 @@
(define_expand "cr6_test_for_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
- (eq:SI (reg:CC 74)
+ (eq:SI (reg:CC CR6_REGNO)
(const_int 0)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
(define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
- (eq:SI (reg:CC 74)
+ (eq:SI (reg:CC CR6_REGNO)
(const_int 0)))
(set (match_dup 0)
(xor:SI (match_dup 0)
@@ -737,14 +737,14 @@
(define_expand "cr6_test_for_lt"
[(set (match_operand:SI 0 "register_operand" "=r")
- (lt:SI (reg:CC 74)
+ (lt:SI (reg:CC CR6_REGNO)
(const_int 0)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
(define_expand "cr6_test_for_lt_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
- (lt:SI (reg:CC 74)
+ (lt:SI (reg:CC CR6_REGNO)
(const_int 0)))
(set (match_dup 0)
(xor:SI (match_dup 0)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60917c541c7..359e424d6b4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1499,7 +1499,7 @@
;; Compare vectors producing a vector result and a predicate, setting CR6 to
;; indicate a combined status
(define_insn "*vsx_eq_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1512,7 +1512,7 @@
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_gt_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1525,7 +1525,7 @@
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
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