diff options
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-types.def')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-types.def | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 5bd36a6524e..977ce6b1831 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -181,6 +181,12 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_EEW64_INTERPRET_OPS(TYPE, REQUIRE) #endif +/* Use "DEF_RVV_BOOL1_INTERPRET_OPS" macro include all types for BOOL1 + vinterpret which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_BOOL1_INTERPRET_OPS +#define DEF_RVV_BOOL1_INTERPRET_OPS(TYPE, REQUIRE) +#endif + /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT which will be iterated and registered as intrinsic functions. */ #ifndef DEF_RVV_X2_VLMUL_EXT_OPS @@ -665,6 +671,16 @@ DEF_RVV_EEW64_INTERPRET_OPS (vuint32m2_t, 0) DEF_RVV_EEW64_INTERPRET_OPS (vuint32m4_t, 0) DEF_RVV_EEW64_INTERPRET_OPS (vuint32m8_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vint8m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vint16m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vint32m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_BOOL1_INTERPRET_OPS (vuint8m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vuint16m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vuint32m1_t, 0) +DEF_RVV_BOOL1_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0) DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0) @@ -1052,6 +1068,7 @@ DEF_RVV_TUPLE_OPS (vfloat64m4x2_t, RVV_REQUIRE_ELEN_FP_64) #undef DEF_RVV_EEW16_INTERPRET_OPS #undef DEF_RVV_EEW32_INTERPRET_OPS #undef DEF_RVV_EEW64_INTERPRET_OPS +#undef DEF_RVV_BOOL1_INTERPRET_OPS #undef DEF_RVV_X2_VLMUL_EXT_OPS #undef DEF_RVV_X4_VLMUL_EXT_OPS #undef DEF_RVV_X8_VLMUL_EXT_OPS |