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-rw-r--r--gcc/config/nvptx/nvptx.md29
1 files changed, 29 insertions, 0 deletions
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index f2b090594e3..41a24b31edd 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -184,6 +184,7 @@
(define_mode_iterator SDCM [SC DC])
(define_mode_iterator BITS [SI SF])
(define_mode_iterator BITD [DI DF])
+(define_mode_iterator VECIM [V2SI V2DI])
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
@@ -201,6 +202,20 @@
%.\\tsetp.eq.u32\\t%0, 1, 1;")
(define_insn "*mov<mode>_insn"
+ [(set (match_operand:VECIM 0 "nonimmediate_operand" "=R,R,m")
+ (match_operand:VECIM 1 "general_operand" "Ri,m,R"))]
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
+{
+ if (which_alternative == 1)
+ return "%.\\tld%A1%u1\\t%0, %1;";
+ if (which_alternative == 2)
+ return "%.\\tst%A0%u0\\t%0, %1;";
+
+ return nvptx_output_mov_insn (operands[0], operands[1]);
+}
+ [(set_attr "subregs_ok" "true")])
+
+(define_insn "*mov<mode>_insn"
[(set (match_operand:QHSDIM 0 "nonimmediate_operand" "=R,R,m")
(match_operand:QHSDIM 1 "general_operand" "Ri,m,R"))]
"!MEM_P (operands[0]) || REG_P (operands[1])"
@@ -242,6 +257,20 @@
""
"%.\\tmov%t0\\t%0, %%ar%1;")
+ (define_expand "mov<mode>"
+ [(set (match_operand:VECIM 0 "nonimmediate_operand" "")
+ (match_operand:VECIM 1 "general_operand" ""))]
+ ""
+{
+ if (MEM_P (operands[0]) && !REG_P (operands[1]))
+ {
+ rtx tmp = gen_reg_rtx (<MODE>mode);
+ emit_move_insn (tmp, operands[1]);
+ emit_move_insn (operands[0], tmp);
+ DONE;
+ }
+})
+
(define_expand "mov<mode>"
[(set (match_operand:QHSDISDFM 0 "nonimmediate_operand" "")
(match_operand:QHSDISDFM 1 "general_operand" ""))]