diff options
Diffstat (limited to 'gcc/config/i386')
39 files changed, 995 insertions, 1632 deletions
diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index 3c8f3600d68..12ed05fe029 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -1252,7 +1252,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i32gather_pd (double const *base, __m128i index, const int scale) { __v4df src = _mm256_setzero_pd (); - __v4df mask = _mm256_set1_pd((double)(long long int) -1); + __v4df mask = _mm256_cmp_pd (src, src, _CMP_EQ_OQ); return (__m256d) __builtin_ia32_gathersiv4df (src, base, @@ -1304,7 +1304,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i64gather_pd (double const *base, __m256i index, const int scale) { __v4df src = _mm256_setzero_pd (); - __v4df mask = _mm256_set1_pd((double)(long long int) -1); + __v4df mask = _mm256_cmp_pd (src, src, _CMP_EQ_OQ); return (__m256d) __builtin_ia32_gatherdiv4df (src, base, @@ -1356,7 +1356,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i32gather_ps (float const *base, __m256i index, const int scale) { __v8sf src = _mm256_setzero_ps (); - __v8sf mask = _mm256_set1_ps((float)(int) -1); + __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ); return (__m256) __builtin_ia32_gathersiv8sf (src, base, diff --git a/gcc/config/i386/cygming-crtbegin.c b/gcc/config/i386/cygming-crtbegin.c deleted file mode 100644 index fc36cce257d..00000000000 --- a/gcc/config/i386/cygming-crtbegin.c +++ /dev/null @@ -1,135 +0,0 @@ -/* crtbegin object for windows32 targets. - Copyright (C) 2007, 2009, 2010 Free Software Foundation, Inc. - - Contributed by Danny Smith <dannysmith@users.sourceforge.net> - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -<http://www.gnu.org/licenses/>. */ - -/* Target machine header files require this define. */ -#define IN_LIBGCC2 - -#include "auto-host.h" -#include "tconfig.h" -#include "tsystem.h" -#include "coretypes.h" -#include "tm.h" -#include "unwind-dw2-fde.h" - -#define WIN32_LEAN_AND_MEAN -#include <windows.h> - -#ifndef LIBGCC_SONAME -#define LIBGCC_SONAME "libgcc_s.dll" -#endif - -#ifndef LIBGCJ_SONAME -#define LIBGCJ_SONAME "libgcj_s.dll" -#endif - - -/* Make the declarations weak. This is critical for - _Jv_RegisterClasses because it lives in libgcj.a */ -extern void __register_frame_info (const void *, struct object *) - TARGET_ATTRIBUTE_WEAK; -extern void *__deregister_frame_info (const void *) - TARGET_ATTRIBUTE_WEAK; -extern void _Jv_RegisterClasses (const void *) TARGET_ATTRIBUTE_WEAK; - -#if defined(HAVE_LD_RO_RW_SECTION_MIXING) -# define EH_FRAME_SECTION_CONST const -#else -# define EH_FRAME_SECTION_CONST -#endif - -/* Stick a label at the beginning of the frame unwind info so we can - register/deregister it with the exception handling library code. */ -#if DWARF2_UNWIND_INFO -static EH_FRAME_SECTION_CONST char __EH_FRAME_BEGIN__[] - __attribute__((used, section(EH_FRAME_SECTION_NAME), aligned(4))) - = { }; - -static struct object obj; -#endif - -#if TARGET_USE_JCR_SECTION -static void *__JCR_LIST__[] - __attribute__ ((used, section(JCR_SECTION_NAME), aligned(4))) - = { }; -#endif - -/* Pull in references from libgcc.a(unwind-dw2-fde.o) in the - startfile. These are referenced by a ctor and dtor in crtend.o. */ -extern void __gcc_register_frame (void); -extern void __gcc_deregister_frame (void); - -void -__gcc_register_frame (void) -{ -#if DWARF2_UNWIND_INFO -/* Weak undefined symbols won't be pulled in from dlls; hence - we first test if the dll is already loaded and, if so, - get the symbol's address at run-time. If the dll is not loaded, - fallback to weak linkage to static archive. */ - - void (*register_frame_fn) (const void *, struct object *); - HANDLE h = GetModuleHandle (LIBGCC_SONAME); - if (h) - register_frame_fn = (void (*) (const void *, struct object *)) - GetProcAddress (h, "__register_frame_info"); - else - register_frame_fn = __register_frame_info; - if (register_frame_fn) - register_frame_fn (__EH_FRAME_BEGIN__, &obj); -#endif - -#if TARGET_USE_JCR_SECTION - if (__JCR_LIST__[0]) - { - void (*register_class_fn) (const void *); - HANDLE h = GetModuleHandle (LIBGCJ_SONAME); - if (h) - register_class_fn = (void (*) (const void *)) - GetProcAddress (h, "_Jv_RegisterClasses"); - else - register_class_fn = _Jv_RegisterClasses; - - if (register_class_fn) - register_class_fn (__JCR_LIST__); - } -#endif -} - -void -__gcc_deregister_frame (void) -{ -#if DWARF2_UNWIND_INFO - void * (*deregister_frame_fn) (const void *); - HANDLE h = GetModuleHandle (LIBGCC_SONAME); - if (h) - deregister_frame_fn = (void* (*) (const void *)) - GetProcAddress (h, "__deregister_frame_info"); - else - deregister_frame_fn = __deregister_frame_info; - if (deregister_frame_fn) - deregister_frame_fn (__EH_FRAME_BEGIN__); -#endif -} diff --git a/gcc/config/i386/cygming-crtend.c b/gcc/config/i386/cygming-crtend.c deleted file mode 100644 index 8545420b271..00000000000 --- a/gcc/config/i386/cygming-crtend.c +++ /dev/null @@ -1,88 +0,0 @@ -/* crtend object for windows32 targets. - Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc. - - Contributed by Danny Smith <dannysmith@users.sourceforge.net> - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -<http://www.gnu.org/licenses/>. */ - -/* Target machine header files require this define. */ -#define IN_LIBGCC2 - -/* auto-host.h is needed by cygming.h for HAVE_GAS_WEAK and here - for HAVE_LD_RO_RW_SECTION_MIXING. */ -#include "auto-host.h" -#include "tconfig.h" -#include "tsystem.h" -#include "coretypes.h" -#include "tm.h" -#include "unwind-dw2-fde.h" - -#if defined(HAVE_LD_RO_RW_SECTION_MIXING) -# define EH_FRAME_SECTION_CONST const -#else -# define EH_FRAME_SECTION_CONST -#endif - -#if DWARF2_UNWIND_INFO -/* Terminate the frame unwind info section with a 0 as a sentinel; - this would be the 'length' field in a real FDE. */ - -static EH_FRAME_SECTION_CONST int __FRAME_END__[] - __attribute__ ((used, section(EH_FRAME_SECTION_NAME), - aligned(4))) - = { 0 }; -#endif - -#if TARGET_USE_JCR_SECTION -/* Null terminate the .jcr section array. */ -static void *__JCR_END__[1] - __attribute__ ((used, section(JCR_SECTION_NAME), - aligned(sizeof(void *)))) - = { 0 }; -#endif - -extern void __gcc_register_frame (void); -extern void __gcc_deregister_frame (void); - -static void register_frame_ctor (void) __attribute__ ((constructor (0))); - -static void -register_frame_ctor (void) -{ - __gcc_register_frame (); -#if DEFAULT_USE_CXA_ATEXIT - /* If we use the __cxa_atexit method to register C++ dtors - at object construction, also use atexit to register eh frame - info cleanup. */ - atexit (__gcc_deregister_frame); -#endif -} - -#if !DEFAULT_USE_CXA_ATEXIT -static void deregister_frame_dtor (void) __attribute__ ((destructor (0))); - -static void -deregister_frame_dtor (void) -{ - __gcc_deregister_frame (); -} -#endif diff --git a/gcc/config/i386/cygwin.asm b/gcc/config/i386/cygwin.asm deleted file mode 100644 index 8f9c486850e..00000000000 --- a/gcc/config/i386/cygwin.asm +++ /dev/null @@ -1,188 +0,0 @@ -/* stuff needed for libgcc on win32. - * - * Copyright (C) 1996, 1998, 2001, 2003, 2008, 2009, 2010 - * Free Software Foundation, Inc. - * Written By Steve Chamberlain - * - * This file is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 3, or (at your option) any - * later version. - * - * This file is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * Under Section 7 of GPL version 3, you are granted additional - * permissions described in the GCC Runtime Library Exception, version - * 3.1, as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License and - * a copy of the GCC Runtime Library Exception along with this program; - * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - * <http://www.gnu.org/licenses/>. - */ - -#include "auto-host.h" - -#ifdef HAVE_GAS_CFI_SECTIONS_DIRECTIVE - .cfi_sections .debug_frame -# define cfi_startproc() .cfi_startproc -# define cfi_endproc() .cfi_endproc -# define cfi_adjust_cfa_offset(X) .cfi_adjust_cfa_offset X -# define cfi_def_cfa_register(X) .cfi_def_cfa_register X -# define cfi_register(D,S) .cfi_register D, S -# ifdef _WIN64 -# define cfi_push(X) .cfi_adjust_cfa_offset 8; .cfi_rel_offset X, 0 -# define cfi_pop(X) .cfi_adjust_cfa_offset -8; .cfi_restore X -# else -# define cfi_push(X) .cfi_adjust_cfa_offset 4; .cfi_rel_offset X, 0 -# define cfi_pop(X) .cfi_adjust_cfa_offset -4; .cfi_restore X -# endif -#else -# define cfi_startproc() -# define cfi_endproc() -# define cfi_adjust_cfa_offset(X) -# define cfi_def_cfa_register(X) -# define cfi_register(D,S) -# define cfi_push(X) -# define cfi_pop(X) -#endif /* HAVE_GAS_CFI_SECTIONS_DIRECTIVE */ - -#ifdef L_chkstk -/* Function prologue calls __chkstk to probe the stack when allocating more - than CHECK_STACK_LIMIT bytes in one go. Touching the stack at 4K - increments is necessary to ensure that the guard pages used - by the OS virtual memory manger are allocated in correct sequence. */ - - .global ___chkstk - .global __alloca -#ifdef _WIN64 -/* __alloca is a normal function call, which uses %rcx as the argument. */ - cfi_startproc() -__alloca: - movq %rcx, %rax - /* FALLTHRU */ - -/* ___chkstk is a *special* function call, which uses %rax as the argument. - We avoid clobbering the 4 integer argument registers, %rcx, %rdx, - %r8 and %r9, which leaves us with %rax, %r10, and %r11 to use. */ - .align 4 -___chkstk: - popq %r11 /* pop return address */ - cfi_adjust_cfa_offset(-8) /* indicate return address in r11 */ - cfi_register(%rip, %r11) - movq %rsp, %r10 - cmpq $0x1000, %rax /* > 4k ?*/ - jb 2f - -1: subq $0x1000, %r10 /* yes, move pointer down 4k*/ - orl $0x0, (%r10) /* probe there */ - subq $0x1000, %rax /* decrement count */ - cmpq $0x1000, %rax - ja 1b /* and do it again */ - -2: subq %rax, %r10 - movq %rsp, %rax /* hold CFA until return */ - cfi_def_cfa_register(%rax) - orl $0x0, (%r10) /* less than 4k, just peek here */ - movq %r10, %rsp /* decrement stack */ - - /* Push the return value back. Doing this instead of just - jumping to %r11 preserves the cached call-return stack - used by most modern processors. */ - pushq %r11 - ret - cfi_endproc() -#else - cfi_startproc() -___chkstk: -__alloca: - pushl %ecx /* save temp */ - cfi_push(%eax) - leal 8(%esp), %ecx /* point past return addr */ - cmpl $0x1000, %eax /* > 4k ?*/ - jb 2f - -1: subl $0x1000, %ecx /* yes, move pointer down 4k*/ - orl $0x0, (%ecx) /* probe there */ - subl $0x1000, %eax /* decrement count */ - cmpl $0x1000, %eax - ja 1b /* and do it again */ - -2: subl %eax, %ecx - orl $0x0, (%ecx) /* less than 4k, just peek here */ - movl %esp, %eax /* save current stack pointer */ - cfi_def_cfa_register(%eax) - movl %ecx, %esp /* decrement stack */ - movl (%eax), %ecx /* recover saved temp */ - - /* Copy the return register. Doing this instead of just jumping to - the address preserves the cached call-return stack used by most - modern processors. */ - pushl 4(%eax) - ret - cfi_endproc() -#endif /* _WIN64 */ -#endif /* L_chkstk */ - -#ifdef L_chkstk_ms -/* ___chkstk_ms is a *special* function call, which uses %rax as the argument. - We avoid clobbering any registers. Unlike ___chkstk, it just probes the - stack and does no stack allocation. */ - .global ___chkstk_ms -#ifdef _WIN64 - cfi_startproc() -___chkstk_ms: - pushq %rcx /* save temps */ - cfi_push(%rcx) - pushq %rax - cfi_push(%rax) - cmpq $0x1000, %rax /* > 4k ?*/ - leaq 24(%rsp), %rcx /* point past return addr */ - jb 2f - -1: subq $0x1000, %rcx /* yes, move pointer down 4k */ - orq $0x0, (%rcx) /* probe there */ - subq $0x1000, %rax /* decrement count */ - cmpq $0x1000, %rax - ja 1b /* and do it again */ - -2: subq %rax, %rcx - orq $0x0, (%rcx) /* less than 4k, just peek here */ - - popq %rax - cfi_pop(%rax) - popq %rcx - cfi_pop(%rcx) - ret - cfi_endproc() -#else - cfi_startproc() -___chkstk_ms: - pushl %ecx /* save temp */ - cfi_push(%ecx) - pushl %eax - cfi_push(%eax) - cmpl $0x1000, %eax /* > 4k ?*/ - leal 12(%esp), %ecx /* point past return addr */ - jb 2f - -1: subl $0x1000, %ecx /* yes, move pointer down 4k*/ - orl $0x0, (%ecx) /* probe there */ - subl $0x1000, %eax /* decrement count */ - cmpl $0x1000, %eax - ja 1b /* and do it again */ - -2: subl %eax, %ecx - orl $0x0, (%ecx) /* less than 4k, just peek here */ - - popl %eax - cfi_pop(%eax) - popl %ecx - cfi_pop(%ecx) - ret - cfi_endproc() -#endif /* _WIN64 */ -#endif /* L_chkstk_ms */ diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index cf17e1e1d89..d84c5c3aed8 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -136,5 +136,5 @@ along with GCC; see the file COPYING3. If not see #define LIBGCC_SONAME "cyggcc_s" LIBGCC_EH_EXTN "-1.dll" /* We should find a way to not have to update this manually. */ -#define LIBGCJ_SONAME "cyggcj" /*LIBGCC_EH_EXTN*/ "-12.dll" +#define LIBGCJ_SONAME "cyggcj" /*LIBGCC_EH_EXTN*/ "-13.dll" diff --git a/gcc/config/i386/darwin-libgcc.10.4.ver b/gcc/config/i386/darwin-libgcc.10.4.ver deleted file mode 100644 index 67f5e239ca1..00000000000 --- a/gcc/config/i386/darwin-libgcc.10.4.ver +++ /dev/null @@ -1,98 +0,0 @@ -# Copyright (C) 2005 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. -__Unwind_Backtrace -__Unwind_DeleteException -__Unwind_FindEnclosingFunction -__Unwind_Find_FDE -__Unwind_ForcedUnwind -__Unwind_GetCFA -__Unwind_GetDataRelBase -__Unwind_GetGR -__Unwind_GetIP -__Unwind_GetLanguageSpecificData -__Unwind_GetRegionStart -__Unwind_GetTextRelBase -__Unwind_RaiseException -__Unwind_Resume -__Unwind_Resume_or_Rethrow -__Unwind_SetGR -__Unwind_SetIP -___absvdi2 -___absvsi2 -___addvdi3 -___addvsi3 -___ashldi3 -___ashrdi3 -___clear_cache -___clzdi2 -___clzsi2 -___cmpdi2 -___ctzdi2 -___ctzsi2 -___deregister_frame -___deregister_frame_info -___deregister_frame_info_bases -___divdc3 -___divdi3 -___divsc3 -___divxc3 -___enable_execute_stack -___ffsdi2 -___fixdfdi -___fixsfdi -___fixunsdfdi -___fixunsdfsi -___fixunssfdi -___fixunssfsi -___fixunsxfdi -___fixunsxfsi -___fixxfdi -___floatdidf -___floatdisf -___floatdixf -___gcc_personality_v0 -___lshrdi3 -___moddi3 -___muldc3 -___muldi3 -___mulsc3 -___mulvdi3 -___mulvsi3 -___mulxc3 -___negdi2 -___negvdi2 -___negvsi2 -___paritydi2 -___paritysi2 -___popcountdi2 -___popcountsi2 -___powidf2 -___powisf2 -___powixf2 -___register_frame -___register_frame_info -___register_frame_info_bases -___register_frame_info_table -___register_frame_info_table_bases -___register_frame_table -___subvdi3 -___subvsi3 -___ucmpdi2 -___udivdi3 -___udivmoddi4 -___umoddi3 diff --git a/gcc/config/i386/darwin-libgcc.10.5.ver b/gcc/config/i386/darwin-libgcc.10.5.ver deleted file mode 100644 index eeec9fbfcdf..00000000000 --- a/gcc/config/i386/darwin-libgcc.10.5.ver +++ /dev/null @@ -1,102 +0,0 @@ -# Copyright (C) 2005, 2006 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. -__Unwind_Backtrace -__Unwind_DeleteException -__Unwind_FindEnclosingFunction -__Unwind_Find_FDE -__Unwind_ForcedUnwind -__Unwind_GetCFA -__Unwind_GetDataRelBase -__Unwind_GetGR -__Unwind_GetIP -__Unwind_GetIPInfo -__Unwind_GetLanguageSpecificData -__Unwind_GetRegionStart -__Unwind_GetTextRelBase -__Unwind_RaiseException -__Unwind_Resume -__Unwind_Resume_or_Rethrow -__Unwind_SetGR -__Unwind_SetIP -___absvdi2 -___absvsi2 -___addvdi3 -___addvsi3 -___ashldi3 -___ashrdi3 -___clear_cache -___clzdi2 -___clzsi2 -___cmpdi2 -___ctzdi2 -___ctzsi2 -___deregister_frame -___deregister_frame_info -___deregister_frame_info_bases -___divdc3 -___divdi3 -___divsc3 -___divxc3 -___enable_execute_stack -___ffsdi2 -___fixdfdi -___fixsfdi -___fixunsdfdi -___fixunsdfsi -___fixunssfdi -___fixunssfsi -___fixunsxfdi -___fixunsxfsi -___fixxfdi -___floatdidf -___floatdisf -___floatdixf -___floatundidf -___floatundisf -___floatundixf -___gcc_personality_v0 -___lshrdi3 -___moddi3 -___muldc3 -___muldi3 -___mulsc3 -___mulvdi3 -___mulvsi3 -___mulxc3 -___negdi2 -___negvdi2 -___negvsi2 -___paritydi2 -___paritysi2 -___popcountdi2 -___popcountsi2 -___powidf2 -___powisf2 -___powixf2 -___register_frame -___register_frame_info -___register_frame_info_bases -___register_frame_info_table -___register_frame_info_table_bases -___register_frame_table -___subvdi3 -___subvsi3 -___ucmpdi2 -___udivdi3 -___udivmoddi4 -___umoddi3 diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h new file mode 100644 index 00000000000..ac827ca0e12 --- /dev/null +++ b/gcc/config/i386/f16cintrin.h @@ -0,0 +1,92 @@ +/* Copyright (C) 2011 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _X86INTRIN_H_INCLUDED && !defined _IMMINTRIN_H_INCLUDED +# error "Never use <f16intrin.h> directly; include <x86intrin.h> or <immintrin.h> instead." +#endif + +#ifndef __F16C__ +# error "F16C instruction set not enabled" +#else + +#ifndef _F16CINTRIN_H_INCLUDED +#define _F16CINTRIN_H_INCLUDED + +extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_cvtsh_ss (unsigned short __S) +{ + __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 }; + __v4sf __A = __builtin_ia32_vcvtph2ps (__H); + return __builtin_ia32_vec_ext_v4sf (__A, 0); +} + +extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtph_ps (__m128i __A) +{ + return (__m128) __builtin_ia32_vcvtph2ps ((__v8hi) __A); +} + +extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtph_ps (__m128i __A) +{ + return (__m256) __builtin_ia32_vcvtph2ps256 ((__v8hi) __A); +} + +#ifdef __OPTIMIZE__ +extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_cvtss_sh (float __F, const int __I) +{ + __v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 }; + __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I); + return (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtps_ph (__m128 __A, const int __I) +{ + return (__m128i) __builtin_ia32_vcvtps2ph ((__v4sf) __A, __I); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtps_ph (__m256 __A, const int __I) +{ + return (__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf) __A, __I); +} +#else +#define _cvtss_sh(__F, __I) \ + (__extension__ \ + ({ \ + __v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 }; \ + __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I); \ + (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0); \ + })) + +#define _mm_cvtps_ph(A, I) \ + ((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) A, (int) (I))) + +#define _mm256_cvtps_ph(A, I) \ + ((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) A, (int) (I))) +#endif /* __OPTIMIZE */ + +#endif /* _F16CINTRIN_H_INCLUDED */ +#endif /* __F16C__ */ diff --git a/gcc/config/i386/gthr-win32.c b/gcc/config/i386/gthr-win32.c deleted file mode 100644 index 46ecb0d4b26..00000000000 --- a/gcc/config/i386/gthr-win32.c +++ /dev/null @@ -1,260 +0,0 @@ -/* Implementation of W32-specific threads compatibility routines for - libgcc2. */ - -/* Copyright (C) 1999, 2000, 2002, 2004, 2008, 2009 Free Software Foundation, Inc. - Contributed by Mumit Khan <khan@xraylith.wisc.edu>. - Modified and moved to separate file by Danny Smith - <dannysmith@users.sourceforge.net>. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -<http://www.gnu.org/licenses/>. */ - -#include <windows.h> -#ifndef __GTHREAD_HIDE_WIN32API -# define __GTHREAD_HIDE_WIN32API 1 -#endif -#undef __GTHREAD_I486_INLINE_LOCK_PRIMITIVES -#define __GTHREAD_I486_INLINE_LOCK_PRIMITIVES -#include <gthr-win32.h> - -/* Windows32 threads specific definitions. The windows32 threading model - does not map well into pthread-inspired gcc's threading model, and so - there are caveats one needs to be aware of. - - 1. The destructor supplied to __gthread_key_create is ignored for - generic x86-win32 ports. This will certainly cause memory leaks - due to unreclaimed eh contexts (sizeof (eh_context) is at least - 24 bytes for x86 currently). - - This memory leak may be significant for long-running applications - that make heavy use of C++ EH. - - However, Mingw runtime (version 0.3 or newer) provides a mechanism - to emulate pthreads key dtors; the runtime provides a special DLL, - linked in if -mthreads option is specified, that runs the dtors in - the reverse order of registration when each thread exits. If - -mthreads option is not given, a stub is linked in instead of the - DLL, which results in memory leak. Other x86-win32 ports can use - the same technique of course to avoid the leak. - - 2. The error codes returned are non-POSIX like, and cast into ints. - This may cause incorrect error return due to truncation values on - hw where sizeof (DWORD) > sizeof (int). - - 3. We are currently using a special mutex instead of the Critical - Sections, since Win9x does not support TryEnterCriticalSection - (while NT does). - - The basic framework should work well enough. In the long term, GCC - needs to use Structured Exception Handling on Windows32. */ - -int -__gthr_win32_once (__gthread_once_t *once, void (*func) (void)) -{ - if (once == NULL || func == NULL) - return EINVAL; - - if (! once->done) - { - if (InterlockedIncrement (&(once->started)) == 0) - { - (*func) (); - once->done = TRUE; - } - else - { - /* Another thread is currently executing the code, so wait for it - to finish; yield the CPU in the meantime. If performance - does become an issue, the solution is to use an Event that - we wait on here (and set above), but that implies a place to - create the event before this routine is called. */ - while (! once->done) - Sleep (0); - } - } - return 0; -} - -/* Windows32 thread local keys don't support destructors; this leads to - leaks, especially in threaded applications making extensive use of - C++ EH. Mingw uses a thread-support DLL to work-around this problem. */ - -int -__gthr_win32_key_create (__gthread_key_t *key, - void (*dtor) (void *) __attribute__((unused))) -{ - int status = 0; - DWORD tls_index = TlsAlloc (); - if (tls_index != 0xFFFFFFFF) - { - *key = tls_index; -#ifdef MINGW32_SUPPORTS_MT_EH - /* Mingw runtime will run the dtors in reverse order for each thread - when the thread exits. */ - status = __mingwthr_key_dtor (*key, dtor); -#endif - } - else - status = (int) GetLastError (); - return status; -} - -int -__gthr_win32_key_delete (__gthread_key_t key) -{ - return (TlsFree (key) != 0) ? 0 : (int) GetLastError (); -} - -void * -__gthr_win32_getspecific (__gthread_key_t key) -{ - DWORD lasterror; - void *ptr; - lasterror = GetLastError(); - ptr = TlsGetValue(key); - SetLastError( lasterror ); - return ptr; -} - -int -__gthr_win32_setspecific (__gthread_key_t key, const void *ptr) -{ - if (TlsSetValue (key, CONST_CAST2(void *, const void *, ptr)) != 0) - return 0; - else - return GetLastError (); -} - -void -__gthr_win32_mutex_init_function (__gthread_mutex_t *mutex) -{ - mutex->counter = -1; - mutex->sema = CreateSemaphore (NULL, 0, 65535, NULL); -} - -void -__gthr_win32_mutex_destroy (__gthread_mutex_t *mutex) -{ - CloseHandle ((HANDLE) mutex->sema); -} - -int -__gthr_win32_mutex_lock (__gthread_mutex_t *mutex) -{ - if (InterlockedIncrement (&mutex->counter) == 0 || - WaitForSingleObject (mutex->sema, INFINITE) == WAIT_OBJECT_0) - return 0; - else - { - /* WaitForSingleObject returns WAIT_FAILED, and we can only do - some best-effort cleanup here. */ - InterlockedDecrement (&mutex->counter); - return 1; - } -} - -int -__gthr_win32_mutex_trylock (__gthread_mutex_t *mutex) -{ - if (__GTHR_W32_InterlockedCompareExchange (&mutex->counter, 0, -1) < 0) - return 0; - else - return 1; -} - -int -__gthr_win32_mutex_unlock (__gthread_mutex_t *mutex) -{ - if (InterlockedDecrement (&mutex->counter) >= 0) - return ReleaseSemaphore (mutex->sema, 1, NULL) ? 0 : 1; - else - return 0; -} - -void -__gthr_win32_recursive_mutex_init_function (__gthread_recursive_mutex_t *mutex) -{ - mutex->counter = -1; - mutex->depth = 0; - mutex->owner = 0; - mutex->sema = CreateSemaphore (NULL, 0, 65535, NULL); -} - -int -__gthr_win32_recursive_mutex_lock (__gthread_recursive_mutex_t *mutex) -{ - DWORD me = GetCurrentThreadId(); - if (InterlockedIncrement (&mutex->counter) == 0) - { - mutex->depth = 1; - mutex->owner = me; - } - else if (mutex->owner == me) - { - InterlockedDecrement (&mutex->counter); - ++(mutex->depth); - } - else if (WaitForSingleObject (mutex->sema, INFINITE) == WAIT_OBJECT_0) - { - mutex->depth = 1; - mutex->owner = me; - } - else - { - /* WaitForSingleObject returns WAIT_FAILED, and we can only do - some best-effort cleanup here. */ - InterlockedDecrement (&mutex->counter); - return 1; - } - return 0; -} - -int -__gthr_win32_recursive_mutex_trylock (__gthread_recursive_mutex_t *mutex) -{ - DWORD me = GetCurrentThreadId(); - if (__GTHR_W32_InterlockedCompareExchange (&mutex->counter, 0, -1) < 0) - { - mutex->depth = 1; - mutex->owner = me; - } - else if (mutex->owner == me) - ++(mutex->depth); - else - return 1; - - return 0; -} - -int -__gthr_win32_recursive_mutex_unlock (__gthread_recursive_mutex_t *mutex) -{ - --(mutex->depth); - if (mutex->depth == 0) - { - mutex->owner = 0; - - if (InterlockedDecrement (&mutex->counter) >= 0) - return ReleaseSemaphore (mutex->sema, 1, NULL) ? 0 : 1; - } - - return 0; -} diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 9a3db0725db..5dcb68c2d43 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -337,6 +337,7 @@ DEF_FUNCTION_TYPE (V16HI, V16HI, INT) DEF_FUNCTION_TYPE (V16HI, V16HI, SI) DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, INT) DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, INT) +DEF_FUNCTION_TYPE (V8SI, V4DF, V4DF) DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI) DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI) DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI) @@ -440,20 +441,24 @@ DEF_FUNCTION_TYPE (V8QI, QI, QI, QI, QI, QI, QI, QI, QI) DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, V2DF, INT) DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, V4DF, INT) +DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, V4DF, INT) DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, V2DF, INT) DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, V4DF, INT) DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, V4SF, INT) DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, V8SF, INT) DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, V4SF, INT) DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, V4SF, INT) +DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, V8SF, INT) DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, V2DI, INT) DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, V4DI, INT) +DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, V4DI, INT) DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, V2DI, INT) DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, V4DI, INT) DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, V4SI, INT) DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, V8SI, INT) DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, V4SI, INT) DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, V4SI, INT) +DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, V8SI, INT) DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4DF_FTYPE_V4DF, ROUND) diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 5486e618dc8..6bfe13d47d6 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -93,6 +93,7 @@ extern bool ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]); extern bool ix86_lea_outperforms (rtx, unsigned int, unsigned int, unsigned int, unsigned int); extern bool ix86_avoid_lea_for_add (rtx, rtx[]); +extern bool ix86_use_lea_for_mov (rtx, rtx[]); extern bool ix86_avoid_lea_for_addr (rtx, rtx[]); extern void ix86_split_lea_for_addr (rtx[], enum machine_mode); extern bool ix86_lea_for_add_ok (rtx, rtx[]); @@ -109,7 +110,8 @@ extern void ix86_expand_convert_uns_sixf_sse (rtx, rtx); extern void ix86_expand_convert_uns_sidf_sse (rtx, rtx); extern void ix86_expand_convert_uns_sisf_sse (rtx, rtx); extern void ix86_expand_convert_sign_didf_sse (rtx, rtx); -extern rtx ix86_expand_adjust_ufix_to_sfix_si (rtx); +extern void ix86_expand_vector_convert_uns_vsivsf (rtx, rtx); +extern rtx ix86_expand_adjust_ufix_to_sfix_si (rtx, rtx *); extern enum ix86_fpcmp_strategy ix86_fp_comparison_strategy (enum rtx_code); extern void ix86_expand_fp_absneg_operator (enum rtx_code, enum machine_mode, rtx[]); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 47ee8e154df..799e12b2b14 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -10913,15 +10913,28 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, it looks like we might want one, insert a NOP. */ { rtx insn = get_last_insn (); + rtx deleted_debug_label = NULL_RTX; while (insn && NOTE_P (insn) && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL) - insn = PREV_INSN (insn); + { + /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL + notes only, instead set their CODE_LABEL_NUMBER to -1, + otherwise there would be code generation differences + in between -g and -g0. */ + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL) + deleted_debug_label = insn; + insn = PREV_INSN (insn); + } if (insn && (LABEL_P (insn) || (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))) fputs ("\tnop\n", file); + else if (deleted_debug_label) + for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn)) + if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL) + CODE_LABEL_NUMBER (insn) = -1; } #endif @@ -16530,6 +16543,29 @@ ix86_avoid_lea_for_add (rtx insn, rtx operands[]) return !ix86_lea_outperforms (insn, regno0, regno1, regno2, 1); } +/* Return true if we should emit lea instruction instead of mov + instruction. */ + +bool +ix86_use_lea_for_mov (rtx insn, rtx operands[]) +{ + unsigned int regno0; + unsigned int regno1; + + /* Check if we need to optimize. */ + if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) + return false; + + /* Use lea for reg to reg moves only. */ + if (!REG_P (operands[0]) || !REG_P (operands[1])) + return false; + + regno0 = true_regnum (operands[0]); + regno1 = true_regnum (operands[1]); + + return ix86_lea_outperforms (insn, regno0, regno1, -1, 0); +} + /* Return true if we need to split lea into a sequence of instructions to avoid AGU stalls. */ @@ -17050,18 +17086,56 @@ ix86_expand_convert_uns_sisf_sse (rtx target, rtx input) emit_move_insn (target, fp_hi); } +/* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert + a vector of unsigned ints VAL to vector of floats TARGET. */ + +void +ix86_expand_vector_convert_uns_vsivsf (rtx target, rtx val) +{ + rtx tmp[8]; + REAL_VALUE_TYPE TWO16r; + enum machine_mode intmode = GET_MODE (val); + enum machine_mode fltmode = GET_MODE (target); + rtx (*cvt) (rtx, rtx); + + if (intmode == V4SImode) + cvt = gen_floatv4siv4sf2; + else + cvt = gen_floatv8siv8sf2; + tmp[0] = ix86_build_const_vector (intmode, 1, GEN_INT (0xffff)); + tmp[0] = force_reg (intmode, tmp[0]); + tmp[1] = expand_simple_binop (intmode, AND, val, tmp[0], NULL_RTX, 1, + OPTAB_DIRECT); + tmp[2] = expand_simple_binop (intmode, LSHIFTRT, val, GEN_INT (16), + NULL_RTX, 1, OPTAB_DIRECT); + tmp[3] = gen_reg_rtx (fltmode); + emit_insn (cvt (tmp[3], tmp[1])); + tmp[4] = gen_reg_rtx (fltmode); + emit_insn (cvt (tmp[4], tmp[2])); + real_ldexp (&TWO16r, &dconst1, 16); + tmp[5] = const_double_from_real_value (TWO16r, SFmode); + tmp[5] = force_reg (fltmode, ix86_build_const_vector (fltmode, 1, tmp[5])); + tmp[6] = expand_simple_binop (fltmode, MULT, tmp[4], tmp[5], NULL_RTX, 1, + OPTAB_DIRECT); + tmp[7] = expand_simple_binop (fltmode, PLUS, tmp[3], tmp[6], target, 1, + OPTAB_DIRECT); + if (tmp[7] != target) + emit_move_insn (target, tmp[7]); +} + /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc* pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*. - This is done by subtracting 0x1p32 from VAL if VAL is greater or equal - (non-signalling) than 0x1p31. */ + This is done by doing just signed conversion if < 0x1p31, and otherwise by + subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */ rtx -ix86_expand_adjust_ufix_to_sfix_si (rtx val) +ix86_expand_adjust_ufix_to_sfix_si (rtx val, rtx *xorp) { - REAL_VALUE_TYPE MTWO32r, TWO31r; - rtx two31r, mtwo32r, tmp[3]; + REAL_VALUE_TYPE TWO31r; + rtx two31r, tmp[4]; enum machine_mode mode = GET_MODE (val); enum machine_mode scalarmode = GET_MODE_INNER (mode); + enum machine_mode intmode = GET_MODE_SIZE (mode) == 32 ? V8SImode : V4SImode; rtx (*cmp) (rtx, rtx, rtx, rtx); int i; @@ -17071,22 +17145,33 @@ ix86_expand_adjust_ufix_to_sfix_si (rtx val) two31r = const_double_from_real_value (TWO31r, scalarmode); two31r = ix86_build_const_vector (mode, 1, two31r); two31r = force_reg (mode, two31r); - real_ldexp (&MTWO32r, &dconstm1, 32); - mtwo32r = const_double_from_real_value (MTWO32r, scalarmode); - mtwo32r = ix86_build_const_vector (mode, 1, mtwo32r); - mtwo32r = force_reg (mode, mtwo32r); switch (mode) { - case V8SFmode: cmp = gen_avx_cmpv8sf3; break; - case V4SFmode: cmp = gen_avx_cmpv4sf3; break; - case V4DFmode: cmp = gen_avx_cmpv4df3; break; - case V2DFmode: cmp = gen_avx_cmpv2df3; break; + case V8SFmode: cmp = gen_avx_maskcmpv8sf3; break; + case V4SFmode: cmp = gen_sse_maskcmpv4sf3; break; + case V4DFmode: cmp = gen_avx_maskcmpv4df3; break; + case V2DFmode: cmp = gen_sse2_maskcmpv2df3; break; default: gcc_unreachable (); } - emit_insn (cmp (tmp[0], val, two31r, GEN_INT (29))); - tmp[1] = expand_simple_binop (mode, AND, tmp[0], mtwo32r, tmp[1], + tmp[3] = gen_rtx_LE (mode, two31r, val); + emit_insn (cmp (tmp[0], two31r, val, tmp[3])); + tmp[1] = expand_simple_binop (mode, AND, tmp[0], two31r, tmp[1], 0, OPTAB_DIRECT); - return expand_simple_binop (mode, PLUS, val, tmp[1], tmp[2], + if (intmode == V4SImode || TARGET_AVX2) + *xorp = expand_simple_binop (intmode, ASHIFT, + gen_lowpart (intmode, tmp[0]), + GEN_INT (31), NULL_RTX, 0, + OPTAB_DIRECT); + else + { + rtx two31 = GEN_INT ((unsigned HOST_WIDE_INT) 1 << 31); + two31 = ix86_build_const_vector (intmode, 1, two31); + *xorp = expand_simple_binop (intmode, AND, + gen_lowpart (intmode, tmp[0]), + two31, NULL_RTX, 0, + OPTAB_DIRECT); + } + return expand_simple_binop (mode, MINUS, val, tmp[1], tmp[2], 0, OPTAB_DIRECT); } @@ -24779,6 +24864,7 @@ enum ix86_builtins IX86_BUILTIN_VEC_SET_V16QI, IX86_BUILTIN_VEC_PACK_SFIX, + IX86_BUILTIN_VEC_PACK_SFIX256, /* SSE4.2. */ IX86_BUILTIN_CRC32QI, @@ -25139,6 +25225,13 @@ enum ix86_builtins IX86_BUILTIN_GATHERDIV4SI, IX86_BUILTIN_GATHERDIV8SI, + /* Alternate 4 element gather for the vectorizer where + all operands are 32-byte wide. */ + IX86_BUILTIN_GATHERALTSIV4DF, + IX86_BUILTIN_GATHERALTDIV8SF, + IX86_BUILTIN_GATHERALTSIV4DI, + IX86_BUILTIN_GATHERALTDIV8SI, + /* TFmode support builtins. */ IX86_BUILTIN_INFQ, IX86_BUILTIN_HUGE_VALQ, @@ -26223,7 +26316,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT }, @@ -26300,6 +26393,8 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF }, + /* AVX2 */ { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT }, { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI }, @@ -27065,6 +27160,22 @@ ix86_init_mmx_sse_builtins (void) V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT, IX86_BUILTIN_GATHERDIV8SI); + def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ", + V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT, + IX86_BUILTIN_GATHERALTSIV4DF); + + def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ", + V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT, + IX86_BUILTIN_GATHERALTDIV8SF); + + def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ", + V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT, + IX86_BUILTIN_GATHERALTSIV4DI); + + def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ", + V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT, + IX86_BUILTIN_GATHERALTDIV8SI); + /* MMX access to the vec_init patterns. */ def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI); @@ -28123,6 +28234,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V32QI_FTYPE_V32QI_V32QI: case V16HI_FTYPE_V32QI_V32QI: case V16HI_FTYPE_V16HI_V16HI: + case V8SI_FTYPE_V4DF_V4DF: case V8SI_FTYPE_V8SI_V8SI: case V8SI_FTYPE_V16HI_V16HI: case V4DI_FTYPE_V4DI_V4DI: @@ -29052,7 +29164,7 @@ rdrand_step: icode = CODE_FOR_avx2_gatherdiv4sf; goto gather_gen; case IX86_BUILTIN_GATHERDIV8SF: - icode = CODE_FOR_avx2_gatherdiv4sf256; + icode = CODE_FOR_avx2_gatherdiv8sf; goto gather_gen; case IX86_BUILTIN_GATHERSIV2DI: icode = CODE_FOR_avx2_gathersiv2di; @@ -29076,7 +29188,20 @@ rdrand_step: icode = CODE_FOR_avx2_gatherdiv4si; goto gather_gen; case IX86_BUILTIN_GATHERDIV8SI: - icode = CODE_FOR_avx2_gatherdiv4si256; + icode = CODE_FOR_avx2_gatherdiv8si; + goto gather_gen; + case IX86_BUILTIN_GATHERALTSIV4DF: + icode = CODE_FOR_avx2_gathersiv4df; + goto gather_gen; + case IX86_BUILTIN_GATHERALTDIV8SF: + icode = CODE_FOR_avx2_gatherdiv8sf; + goto gather_gen; + case IX86_BUILTIN_GATHERALTSIV4DI: + icode = CODE_FOR_avx2_gathersiv4df; + goto gather_gen; + case IX86_BUILTIN_GATHERALTDIV8SI: + icode = CODE_FOR_avx2_gatherdiv8si; + goto gather_gen; gather_gen: arg0 = CALL_EXPR_ARG (exp, 0); @@ -29095,8 +29220,39 @@ rdrand_step: mode3 = insn_data[icode].operand[4].mode; mode4 = insn_data[icode].operand[5].mode; - if (target == NULL_RTX) - target = gen_reg_rtx (insn_data[icode].operand[0].mode); + if (target == NULL_RTX + || GET_MODE (target) != insn_data[icode].operand[0].mode) + subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); + else + subtarget = target; + + if (fcode == IX86_BUILTIN_GATHERALTSIV4DF + || fcode == IX86_BUILTIN_GATHERALTSIV4DI) + { + rtx half = gen_reg_rtx (V4SImode); + if (!nonimmediate_operand (op2, V8SImode)) + op2 = copy_to_mode_reg (V8SImode, op2); + emit_insn (gen_vec_extract_lo_v8si (half, op2)); + op2 = half; + } + else if (fcode == IX86_BUILTIN_GATHERALTDIV8SF + || fcode == IX86_BUILTIN_GATHERALTDIV8SI) + { + rtx (*gen) (rtx, rtx); + rtx half = gen_reg_rtx (mode0); + if (mode0 == V4SFmode) + gen = gen_vec_extract_lo_v8sf; + else + gen = gen_vec_extract_lo_v8si; + if (!nonimmediate_operand (op0, GET_MODE (op0))) + op0 = copy_to_mode_reg (GET_MODE (op0), op0); + emit_insn (gen (half, op0)); + op0 = half; + if (!nonimmediate_operand (op3, GET_MODE (op3))) + op3 = copy_to_mode_reg (GET_MODE (op3), op3); + emit_insn (gen (half, op3)); + op3 = half; + } /* Force memory operand only with base register here. But we don't want to do it on memory operand for other builtin @@ -29118,10 +29274,91 @@ rdrand_step: error ("last argument must be scale 1, 2, 4, 8"); return const0_rtx; } - pat = GEN_FCN (icode) (target, op0, op1, op2, op3, op4); + + /* Optimize. If mask is known to have all high bits set, + replace op0 with pc_rtx to signal that the instruction + overwrites the whole destination and doesn't use its + previous contents. */ + if (optimize) + { + if (TREE_CODE (arg3) == VECTOR_CST) + { + tree elt; + unsigned int negative = 0; + for (elt = TREE_VECTOR_CST_ELTS (arg3); + elt; elt = TREE_CHAIN (elt)) + { + tree cst = TREE_VALUE (elt); + if (TREE_CODE (cst) == INTEGER_CST + && tree_int_cst_sign_bit (cst)) + negative++; + else if (TREE_CODE (cst) == REAL_CST + && REAL_VALUE_NEGATIVE (TREE_REAL_CST (cst))) + negative++; + } + if (negative == TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg3))) + op0 = pc_rtx; + } + else if (TREE_CODE (arg3) == SSA_NAME) + { + /* Recognize also when mask is like: + __v2df src = _mm_setzero_pd (); + __v2df mask = _mm_cmpeq_pd (src, src); + or + __v8sf src = _mm256_setzero_ps (); + __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ); + as that is a cheaper way to load all ones into + a register than having to load a constant from + memory. */ + gimple def_stmt = SSA_NAME_DEF_STMT (arg3); + if (is_gimple_call (def_stmt)) + { + tree fndecl = gimple_call_fndecl (def_stmt); + if (fndecl + && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD) + switch ((unsigned int) DECL_FUNCTION_CODE (fndecl)) + { + case IX86_BUILTIN_CMPPD: + case IX86_BUILTIN_CMPPS: + case IX86_BUILTIN_CMPPD256: + case IX86_BUILTIN_CMPPS256: + if (!integer_zerop (gimple_call_arg (def_stmt, 2))) + break; + /* FALLTHRU */ + case IX86_BUILTIN_CMPEQPD: + case IX86_BUILTIN_CMPEQPS: + if (initializer_zerop (gimple_call_arg (def_stmt, 0)) + && initializer_zerop (gimple_call_arg (def_stmt, + 1))) + op0 = pc_rtx; + break; + default: + break; + } + } + } + } + + pat = GEN_FCN (icode) (subtarget, op0, op1, op2, op3, op4); if (! pat) return const0_rtx; emit_insn (pat); + + if (fcode == IX86_BUILTIN_GATHERDIV8SF + || fcode == IX86_BUILTIN_GATHERDIV8SI) + { + enum machine_mode tmode = GET_MODE (subtarget) == V8SFmode + ? V4SFmode : V4SImode; + if (target == NULL_RTX) + target = gen_reg_rtx (tmode); + if (tmode == V4SFmode) + emit_insn (gen_vec_extract_lo_v8sf (target, subtarget)); + else + emit_insn (gen_vec_extract_lo_v8si (target, subtarget)); + } + else + target = subtarget; + return target; default: @@ -29218,13 +29455,21 @@ ix86_builtin_vectorized_function (tree fndecl, tree type_out, } break; + case BUILT_IN_IRINT: case BUILT_IN_LRINT: - if (out_mode == SImode && out_n == 4 - && in_mode == DFmode && in_n == 2) - return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX]; + case BUILT_IN_LLRINT: + if (out_mode == SImode && in_mode == DFmode) + { + if (out_n == 4 && in_n == 2) + return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX]; + else if (out_n == 8 && in_n == 4) + return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX256]; + } break; + case BUILT_IN_IRINTF: case BUILT_IN_LRINTF: + case BUILT_IN_LLRINTF: if (out_mode == SImode && in_mode == SFmode) { if (out_n == 4 && in_n == 4) @@ -29626,6 +29871,73 @@ ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in) return new_fndecl; } +/* Returns a decl of a function that implements gather load with + memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE. + Return NULL_TREE if it is not available. */ + +static tree +ix86_vectorize_builtin_gather (const_tree mem_vectype, + const_tree index_type, int scale) +{ + bool si; + enum ix86_builtins code; + + if (! TARGET_AVX2) + return NULL_TREE; + + if ((TREE_CODE (index_type) != INTEGER_TYPE + && !POINTER_TYPE_P (index_type)) + || (TYPE_MODE (index_type) != SImode + && TYPE_MODE (index_type) != DImode)) + return NULL_TREE; + + if (TYPE_PRECISION (index_type) > POINTER_SIZE) + return NULL_TREE; + + /* v*gather* insn sign extends index to pointer mode. */ + if (TYPE_PRECISION (index_type) < POINTER_SIZE + && TYPE_UNSIGNED (index_type)) + return NULL_TREE; + + if (scale <= 0 + || scale > 8 + || (scale & (scale - 1)) != 0) + return NULL_TREE; + + si = TYPE_MODE (index_type) == SImode; + switch (TYPE_MODE (mem_vectype)) + { + case V2DFmode: + code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF; + break; + case V4DFmode: + code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF; + break; + case V2DImode: + code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI; + break; + case V4DImode: + code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI; + break; + case V4SFmode: + code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF; + break; + case V8SFmode: + code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF; + break; + case V4SImode: + code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI; + break; + case V8SImode: + code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI; + break; + default: + return NULL_TREE; + } + + return ix86_builtins[code]; +} + /* Returns a code for a target-specific builtin that implements reciprocal of the function, or NULL_TREE if not available. */ @@ -37835,6 +38147,9 @@ ix86_autovectorize_vector_sizes (void) #undef TARGET_VECTORIZE_BUILTIN_TM_STORE #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store +#undef TARGET_VECTORIZE_BUILTIN_GATHER +#define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather + #undef TARGET_BUILTIN_RECIPROCAL #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a8ebfa48000..35273d95683 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -248,6 +248,9 @@ ;; For BMI2 support UNSPEC_PDEP UNSPEC_PEXT + + ;; For __atomic support + UNSPEC_MOVA ]) (define_c_enum "unspecv" [ @@ -262,7 +265,10 @@ UNSPECV_ALIGN UNSPECV_MONITOR UNSPECV_MWAIT - UNSPECV_CMPXCHG + UNSPECV_CMPXCHG_1 + UNSPECV_CMPXCHG_2 + UNSPECV_CMPXCHG_3 + UNSPECV_CMPXCHG_4 UNSPECV_XCHG UNSPECV_LOCK UNSPECV_PROLOGUE_USE @@ -2047,6 +2053,8 @@ return "mov{l}\t{%k1, %k0|%k0, %k1}"; else if (which_alternative == 2) return "movabs{q}\t{%1, %0|%0, %1}"; + else if (ix86_use_lea_for_mov (insn, operands)) + return "lea{q}\t{%a1, %0|%0, %a1}"; else return "mov{q}\t{%1, %0|%0, %1}"; } @@ -2282,7 +2290,10 @@ default: gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1])); - return "mov{l}\t{%1, %0|%0, %1}"; + if (ix86_use_lea_for_mov (insn, operands)) + return "lea{l}\t{%a1, %0|%0, %a1}"; + else + return "mov{l}\t{%1, %0|%0, %1}"; } } [(set (attr "type") @@ -4922,7 +4933,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split @@ -4935,7 +4946,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5026,7 +5037,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5069,7 +5080,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5093,7 +5104,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5139,7 +5150,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5202,7 +5213,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit" @@ -5237,7 +5248,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5250,7 +5261,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp" @@ -7702,8 +7713,10 @@ [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8)) (match_dup 3)) (const_int 0)]))] - "operands[2] = gen_lowpart (SImode, operands[2]); - operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);") +{ + operands[2] = gen_lowpart (SImode, operands[2]); + operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode); +}) (define_split [(set (match_operand 0 "flags_reg_operand" "") @@ -7721,8 +7734,10 @@ [(set (match_dup 0) (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3)) (const_int 0)]))] - "operands[2] = gen_lowpart (QImode, operands[2]); - operands[3] = gen_lowpart (QImode, operands[3]);") +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_lowpart (QImode, operands[3]); +}) ;; %%% This used to optimize known byte-wide and operations to memory, ;; and sometimes to QImode registers. If this is considered useful, @@ -8147,9 +8162,11 @@ (const_int 8) (const_int 8)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode); +}) ;; Since AND can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is not set. @@ -8168,9 +8185,11 @@ (and:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (QImode, operands[0]); - operands[1] = gen_lowpart (QImode, operands[1]); - operands[2] = gen_lowpart (QImode, operands[2]);") +{ + operands[0] = gen_lowpart (QImode, operands[0]); + operands[1] = gen_lowpart (QImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) ;; Logical inclusive and exclusive OR instructions @@ -8402,9 +8421,11 @@ (const_int 8) (const_int 8)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode); +}) ;; Since OR can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is set. @@ -8423,9 +8444,11 @@ (any_or:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (QImode, operands[0]); - operands[1] = gen_lowpart (QImode, operands[1]); - operands[2] = gen_lowpart (QImode, operands[2]);") +{ + operands[0] = gen_lowpart (QImode, operands[0]); + operands[1] = gen_lowpart (QImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) (define_expand "xorqi_cc_ext_1" [(parallel [ @@ -14651,7 +14674,7 @@ else if (optimize_insn_for_size_p ()) FAIL; else - ix86_expand_rint (operand0, operand1); + ix86_expand_rint (operands[0], operands[1]); } else { @@ -14851,7 +14874,7 @@ && <SWI248x:MODE>mode != HImode && ((<SWI248x:MODE>mode != DImode) || TARGET_64BIT) && !flag_trapping_math && !flag_rounding_math) - ix86_expand_lround (operand0, operand1); + ix86_expand_lround (operands[0], operands[1]); else ix86_emit_i387_round (operands[0], operands[1]); DONE; @@ -14927,9 +14950,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, true); + ix86_expand_floorceil (operands[0], operands[1], true); else - ix86_expand_floorceildf_32 (operand0, operand1, true); + ix86_expand_floorceildf_32 (operands[0], operands[1], true); } else { @@ -15111,7 +15134,7 @@ { if (TARGET_64BIT && optimize_insn_for_size_p ()) FAIL; - ix86_expand_lfloorceil (operand0, operand1, true); + ix86_expand_lfloorceil (operands[0], operands[1], true); DONE; }) @@ -15185,9 +15208,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, false); + ix86_expand_floorceil (operands[0], operands[1], false); else - ix86_expand_floorceildf_32 (operand0, operand1, false); + ix86_expand_floorceildf_32 (operands[0], operands[1], false); } else { @@ -15367,7 +15390,7 @@ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !flag_trapping_math" { - ix86_expand_lfloorceil (operand0, operand1, false); + ix86_expand_lfloorceil (operands[0], operands[1], false); DONE; }) @@ -15441,9 +15464,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_trunc (operand0, operand1); + ix86_expand_trunc (operands[0], operands[1]); else - ix86_expand_truncdf_32 (operand0, operand1); + ix86_expand_truncdf_32 (operands[0], operands[1]); } else { @@ -16631,14 +16654,18 @@ ;; The % modifier is not operational anymore in peephole2's, so we have to ;; swap the operands manually in the case of addition and multiplication. - "if (COMMUTATIVE_ARITH_P (operands[2])) - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), - GET_MODE (operands[2]), - operands[0], operands[1]); - else - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), - GET_MODE (operands[2]), - operands[1], operands[0]);") +{ + rtx op0, op1; + + if (COMMUTATIVE_ARITH_P (operands[2])) + op0 = operands[0], op1 = operands[1]; + else + op0 = operands[1], op1 = operands[0]; + + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), + GET_MODE (operands[2]), + op0, op1); +}) ;; Conditional addition patterns (define_expand "add<mode>cc" @@ -16837,11 +16864,13 @@ [(parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 1) (match_dup 2)])) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - if (GET_CODE (operands[3]) != ASHIFT) - operands[2] = gen_lowpart (SImode, operands[2]); - PUT_MODE (operands[3], SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + if (GET_CODE (operands[3]) != ASHIFT) + operands[2] = gen_lowpart (SImode, operands[2]); + PUT_MODE (operands[3], SImode); +}) ; Promote the QImode tests, as i386 has encoding of the AND ; instruction with 32-bit sign-extended immediate and thus the @@ -16911,8 +16940,10 @@ [(parallel [(set (match_dup 0) (neg:SI (match_dup 1))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); +}) (define_split [(set (match_operand 0 "register_operand" "") @@ -16924,8 +16955,10 @@ || optimize_insn_for_size_p ())))" [(set (match_dup 0) (not:SI (match_dup 1)))] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); +}) (define_split [(set (match_operand 0 "register_operand" "") @@ -16940,9 +16973,11 @@ || optimize_insn_for_size_p ())))" [(set (match_dup 0) (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[2] = gen_lowpart (SImode, operands[2]); - operands[3] = gen_lowpart (SImode, operands[3]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[2] = gen_lowpart (SImode, operands[2]); + operands[3] = gen_lowpart (SImode, operands[3]); +}) ;; RTL Peephole optimizations, run before sched2. These primarily look to ;; transform a complex memory operation into two memory to register operations. @@ -17228,12 +17263,14 @@ [(parallel [(set (match_dup 4) (match_dup 5)) (set (match_dup 1) (match_op_dup 3 [(match_dup 1) (match_dup 2)]))])] - "operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, - copy_rtx (operands[1]), - copy_rtx (operands[2])); - operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), - operands[5], const0_rtx);") +{ + operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, + copy_rtx (operands[1]), + copy_rtx (operands[2])); + operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), + operands[5], const0_rtx); +}) (define_peephole2 [(parallel [(set (match_operand:SWI 0 "register_operand" "") @@ -17253,12 +17290,14 @@ [(parallel [(set (match_dup 3) (match_dup 4)) (set (match_dup 1) (match_op_dup 2 [(match_dup 1) (match_dup 0)]))])] - "operands[3] = SET_DEST (PATTERN (peep2_next_insn (2))); - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode, - copy_rtx (operands[1]), - copy_rtx (operands[0])); - operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]), - operands[4], const0_rtx);") +{ + operands[3] = SET_DEST (PATTERN (peep2_next_insn (2))); + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode, + copy_rtx (operands[1]), + copy_rtx (operands[0])); + operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]), + operands[4], const0_rtx); +}) (define_peephole2 [(set (match_operand:SWI12 0 "register_operand" "") @@ -17281,15 +17320,17 @@ ? CCGOCmode : CCNOmode)" [(parallel [(set (match_dup 4) (match_dup 5)) (set (match_dup 1) (match_dup 6))])] - "operands[2] = gen_lowpart (<MODE>mode, operands[2]); - operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, - copy_rtx (operands[1]), operands[2]); - operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), - operands[5], const0_rtx); - operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, - copy_rtx (operands[1]), - copy_rtx (operands[2]));") +{ + operands[2] = gen_lowpart (<MODE>mode, operands[2]); + operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, + copy_rtx (operands[1]), operands[2]); + operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), + operands[5], const0_rtx); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode, + copy_rtx (operands[1]), + copy_rtx (operands[2])); +}) ;; Attempt to always use XOR for zeroing registers. (define_peephole2 @@ -18075,8 +18116,8 @@ (match_operand:SI 3 "const_int_operand" "i")] UNSPECV_LWPVAL_INTRINSIC)] "TARGET_LWP" - "/* Avoid unused variable warning. */ - (void) operand0;") + ;; Avoid unused variable warning. + "(void) operands[0];") (define_insn "*lwp_lwpval<mode>3_1" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 102814e2b90..986a573dbea 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -76,6 +76,10 @@ #include <fmaintrin.h> #endif +#ifdef __F16C__ +#include <f16cintrin.h> +#endif + #ifdef __RDRND__ extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -161,63 +165,4 @@ _rdrand64_step (unsigned long long *__P) #endif /* __RDRND__ */ #endif /* __x86_64__ */ -#ifdef __F16C__ -extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_cvtsh_ss (unsigned short __S) -{ - __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 }; - __v4sf __A = __builtin_ia32_vcvtph2ps (__H); - return __builtin_ia32_vec_ext_v4sf (__A, 0); -} - -extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm_cvtph_ps (__m128i __A) -{ - return (__m128) __builtin_ia32_vcvtph2ps ((__v8hi) __A); -} - -extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm256_cvtph_ps (__m128i __A) -{ - return (__m256) __builtin_ia32_vcvtph2ps256 ((__v8hi) __A); -} - -#ifdef __OPTIMIZE__ -extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_cvtss_sh (float __F, const int __I) -{ - __v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 }; - __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I); - return (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0); -} - -extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm_cvtps_ph (__m128 __A, const int __I) -{ - return (__m128i) __builtin_ia32_vcvtps2ph ((__v4sf) __A, __I); -} - -extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm256_cvtps_ph (__m256 __A, const int __I) -{ - return (__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf) __A, __I); -} -#else -#define _cvtss_sh(__F, __I) \ - (__extension__ \ - ({ \ - __v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 }; \ - __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I); \ - (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0); \ - })) - -#define _mm_cvtps_ph(A, I) \ - ((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) A, (int) (I))) - -#define _mm256_cvtps_ph(A, I) \ - ((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) A, (int) (I))) -#endif - -#endif /* __F16C__ */ - #endif /* _IMMINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/libgcc-glibc.ver b/gcc/config/i386/libgcc-glibc.ver deleted file mode 100644 index e79d3267f6f..00000000000 --- a/gcc/config/i386/libgcc-glibc.ver +++ /dev/null @@ -1,186 +0,0 @@ -# Copyright (C) 2008, 2010 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. - -# In order to work around the very problems that force us to now generally -# create a libgcc.so, glibc reexported a number of routines from libgcc.a. -# By now choosing the same version tags for these specific routines, we -# maintain enough binary compatibility to allow future versions of glibc -# to defer implementation of these routines to libgcc.so via DT_AUXILIARY. - -%ifndef __x86_64__ -%exclude { - __divdi3 - __moddi3 - __udivdi3 - __umoddi3 - __register_frame - __register_frame_table - __deregister_frame - __register_frame_info - __deregister_frame_info - __frame_state_for - __register_frame_info_table -} - -%inherit GCC_3.0 GLIBC_2.0 -GLIBC_2.0 { - # Sampling of DImode arithmetic used by (at least) i386 and m68k. - __divdi3 - __moddi3 - __udivdi3 - __umoddi3 - - # Exception handling support functions used by most everyone. - __register_frame - __register_frame_table - __deregister_frame - __register_frame_info - __deregister_frame_info - __frame_state_for - __register_frame_info_table -} -%endif - -# 128 bit long double support was introduced with GCC 4.3.0 to 64bit -# and with GCC 4.4.0 to 32bit. These lines make the symbols to get -# a @@GCC_4.3.0 or @@GCC_4.4.0 attached. - -%exclude { - __addtf3 - __divtc3 - __divtf3 - __eqtf2 - __extenddftf2 - __extendsftf2 - __extendxftf2 - __fixtfdi - __fixtfsi - __fixtfti - __fixunstfdi - __fixunstfsi - __fixunstfti - __floatditf - __floatsitf - __floattitf - __floatunditf - __floatunsitf - __floatuntitf - __getf2 - __gttf2 - __letf2 - __lttf2 - __multc3 - __multf3 - __negtf2 - __netf2 - __powitf2 - __subtf3 - __trunctfdf2 - __trunctfsf2 - __trunctfxf2 - __unordtf2 -} - -%ifdef __x86_64__ -# Those symbols had improper versions when they were added to gcc 4.3.0. -# We corrected the default version to GCC_4.3.0. But we keep the old -# version for backward binary compatibility. -GCC_3.0 { - __gttf2 - __lttf2 - __netf2 -} - -GCC_4.0.0 { - __divtc3 - __multc3 - __powitf2 -} - -GCC_4.3.0 { - __addtf3 - __divtc3 - __divtf3 - __eqtf2 - __extenddftf2 - __extendsftf2 - __extendxftf2 - __fixtfdi - __fixtfsi - __fixtfti - __fixunstfdi - __fixunstfsi - __fixunstfti - __floatditf - __floatsitf - __floattitf - __floatunditf - __floatunsitf - __floatuntitf - __getf2 - __gttf2 - __letf2 - __lttf2 - __multc3 - __multf3 - __negtf2 - __netf2 - __powitf2 - __subtf3 - __trunctfdf2 - __trunctfsf2 - __trunctfxf2 - __unordtf2 -} -%else -GCC_4.4.0 { - __addtf3 - __copysigntf3 - __divtc3 - __divtf3 - __eqtf2 - __extenddftf2 - __extendsftf2 - __fabstf2 - __fixtfdi - __fixtfsi - __fixunstfdi - __fixunstfsi - __floatditf - __floatsitf - __floatunditf - __floatunsitf - __getf2 - __gttf2 - __letf2 - __lttf2 - __multc3 - __multf3 - __negtf2 - __netf2 - __powitf2 - __subtf3 - __trunctfdf2 - __trunctfsf2 - __trunctfxf2 - __unordtf2 -} -GCC_4.5.0 { - __extendxftf2 -} -%endif diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index d9f10c834af..00dcca60bb0 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -230,4 +230,4 @@ do { \ #define LIBGCC_SONAME "libgcc_s" LIBGCC_EH_EXTN "-1.dll" /* We should find a way to not have to update this manually. */ -#define LIBGCJ_SONAME "libgcj" /*LIBGCC_EH_EXTN*/ "-12.dll" +#define LIBGCJ_SONAME "libgcj" /*LIBGCC_EH_EXTN*/ "-13.dll" diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 48e110ad164..3745b497c19 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1162,7 +1162,7 @@ ;; Return true if OP is a binary operator that can be promoted to wider mode. (define_predicate "promotable_binary_operator" - (ior (match_code "plus,and,ior,xor,ashift") + (ior (match_code "plus,minus,and,ior,xor,ashift") (and (match_code "mult") (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL")))) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 33c2e94b369..688b5be9648 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -316,14 +316,6 @@ ;; Mix-n-match (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF]) -(define_mode_iterator AVXMODE48P_DI - [V2DI V2DF V4DI V4DF V4SF V4SI]) -(define_mode_attr AVXMODE48P_DI - [(V2DI "V2DI") (V2DF "V2DI") - (V4DI "V4DI") (V4DF "V4DI") - (V4SI "V2DI") (V4SF "V2DI") - (V8SI "V4DI") (V8SF "V4DI")]) - (define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF]) ;; Mapping of immediate bits for blend instructions @@ -2242,30 +2234,12 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "floatuns<sseintvecmodelower><mode>2" - [(set (match_dup 5) - (float:VF1 - (match_operand:<sseintvecmode> 1 "nonimmediate_operand" ""))) - (set (match_dup 6) - (lt:VF1 (match_dup 5) (match_dup 3))) - (set (match_dup 7) - (and:VF1 (match_dup 6) (match_dup 4))) - (set (match_operand:VF1 0 "register_operand" "") - (plus:VF1 (match_dup 5) (match_dup 7)))] - "TARGET_SSE2" + [(match_operand:VF1 0 "register_operand" "") + (match_operand:<sseintvecmode> 1 "register_operand" "")] + "TARGET_SSE2 && (<MODE>mode == V4SFmode || TARGET_AVX2)" { - REAL_VALUE_TYPE TWO32r; - rtx x; - int i; - - real_ldexp (&TWO32r, &dconst1, 32); - x = const_double_from_real_value (TWO32r, SFmode); - - operands[3] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); - operands[4] = force_reg (<MODE>mode, - ix86_build_const_vector (<MODE>mode, 1, x)); - - for (i = 5; i < 8; i++) - operands[i] = gen_reg_rtx (<MODE>mode); + ix86_expand_vector_convert_uns_vsivsf (operands[0], operands[1]); + DONE; }) (define_insn "avx_cvtps2dq256" @@ -2325,10 +2299,13 @@ (define_expand "fixuns_trunc<mode><sseintvecmodelower>2" [(match_operand:<sseintvecmode> 0 "register_operand" "") (match_operand:VF1 1 "register_operand" "")] - "TARGET_AVX" + "TARGET_SSE2" { - rtx tmp = ix86_expand_adjust_ufix_to_sfix_si (operands[1]); - emit_insn (gen_fix_trunc<mode><sseintvecmodelower>2 (operands[0], tmp)); + rtx tmp[3]; + tmp[0] = ix86_expand_adjust_ufix_to_sfix_si (operands[1], &tmp[2]); + tmp[1] = gen_reg_rtx (<sseintvecmode>mode); + emit_insn (gen_fix_trunc<mode><sseintvecmodelower>2 (tmp[1], tmp[0])); + emit_insn (gen_xor<sseintvecmodelower>3 (operands[0], tmp[1], tmp[2])); DONE; }) @@ -3115,12 +3092,29 @@ [(match_operand:<ssepackfltmode> 0 "register_operand" "") (match_operand:VF2 1 "register_operand" "") (match_operand:VF2 2 "register_operand" "")] - "TARGET_AVX" + "TARGET_SSE2" { - rtx tmp[2]; - tmp[0] = ix86_expand_adjust_ufix_to_sfix_si (operands[1]); - tmp[1] = ix86_expand_adjust_ufix_to_sfix_si (operands[2]); - emit_insn (gen_vec_pack_sfix_trunc_<mode> (operands[0], tmp[0], tmp[1])); + rtx tmp[7]; + tmp[0] = ix86_expand_adjust_ufix_to_sfix_si (operands[1], &tmp[2]); + tmp[1] = ix86_expand_adjust_ufix_to_sfix_si (operands[2], &tmp[3]); + tmp[4] = gen_reg_rtx (<ssepackfltmode>mode); + emit_insn (gen_vec_pack_sfix_trunc_<mode> (tmp[4], tmp[0], tmp[1])); + if (<ssepackfltmode>mode == V4SImode || TARGET_AVX2) + { + tmp[5] = gen_reg_rtx (<ssepackfltmode>mode); + ix86_expand_vec_extract_even_odd (tmp[5], tmp[2], tmp[3], 0); + } + else + { + tmp[5] = gen_reg_rtx (V8SFmode); + ix86_expand_vec_extract_even_odd (tmp[5], gen_lowpart (V8SFmode, tmp[2]), + gen_lowpart (V8SFmode, tmp[3]), 0); + tmp[5] = gen_lowpart (V8SImode, tmp[5]); + } + tmp[6] = expand_simple_binop (<ssepackfltmode>mode, XOR, tmp[4], tmp[5], + operands[0], 0, OPTAB_DIRECT); + if (tmp[6] != operands[0]) + emit_move_insn (operands[0], tmp[6]); DONE; }) @@ -12516,11 +12510,21 @@ ;; For gather* insn patterns (define_mode_iterator VEC_GATHER_MODE [V2DI V2DF V4DI V4DF V4SI V4SF V8SI V8SF]) -(define_mode_attr VEC_GATHER_MODE +(define_mode_attr VEC_GATHER_IDXSI [(V2DI "V4SI") (V2DF "V4SI") (V4DI "V4SI") (V4DF "V4SI") (V4SI "V4SI") (V4SF "V4SI") (V8SI "V8SI") (V8SF "V8SI")]) +(define_mode_attr VEC_GATHER_IDXDI + [(V2DI "V2DI") (V2DF "V2DI") + (V4DI "V4DI") (V4DF "V4DI") + (V4SI "V2DI") (V4SF "V2DI") + (V8SI "V4DI") (V8SF "V4DI")]) +(define_mode_attr VEC_GATHER_SRCDI + [(V2DI "V2DI") (V2DF "V2DF") + (V4DI "V4DI") (V4DF "V4DF") + (V4SI "V4SI") (V4SF "V4SF") + (V8SI "V4SI") (V8SF "V4SF")]) (define_expand "avx2_gathersi<mode>" [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") @@ -12529,7 +12533,8 @@ (mem:<ssescalarmode> (match_par_dup 7 [(match_operand 2 "vsib_address_operand" "") - (match_operand:<VEC_GATHER_MODE> 3 "register_operand" "") + (match_operand:<VEC_GATHER_IDXSI> + 3 "register_operand" "") (match_operand:SI 5 "const1248_operand " "")])) (mem:BLK (scratch)) (match_operand:VEC_GATHER_MODE 4 "register_operand" "")] @@ -12549,7 +12554,7 @@ (match_operator:<ssescalarmode> 7 "vsib_mem_operator" [(unspec:P [(match_operand:P 3 "vsib_address_operand" "p") - (match_operand:<VEC_GATHER_MODE> 4 "register_operand" "x") + (match_operand:<VEC_GATHER_IDXSI> 4 "register_operand" "x") (match_operand:SI 6 "const1248_operand" "n")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) @@ -12562,17 +12567,39 @@ (set_attr "prefix" "vex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "*avx2_gathersi<mode>_2" + [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") + (unspec:VEC_GATHER_MODE + [(pc) + (match_operator:<ssescalarmode> 6 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 2 "vsib_address_operand" "p") + (match_operand:<VEC_GATHER_IDXSI> 3 "register_operand" "x") + (match_operand:SI 5 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (mem:BLK (scratch)) + (match_operand:VEC_GATHER_MODE 4 "register_operand" "1")] + UNSPEC_GATHER)) + (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] + "TARGET_AVX2" + "v<sseintprefix>gatherd<ssemodesuffix>\t{%1, %6, %0|%0, %6, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "vex") + (set_attr "mode" "<sseinsnmode>")]) + (define_expand "avx2_gatherdi<mode>" [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") (unspec:VEC_GATHER_MODE - [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") + [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand" "") (mem:<ssescalarmode> (match_par_dup 7 [(match_operand 2 "vsib_address_operand" "") - (match_operand:<AVXMODE48P_DI> 3 "register_operand" "") + (match_operand:<VEC_GATHER_IDXDI> + 3 "register_operand" "") (match_operand:SI 5 "const1248_operand " "")])) (mem:BLK (scratch)) - (match_operand:VEC_GATHER_MODE 4 "register_operand" "")] + (match_operand:<VEC_GATHER_SRCDI> + 4 "register_operand" "")] UNSPEC_GATHER)) (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])] "TARGET_AVX2" @@ -12583,63 +12610,45 @@ }) (define_insn "*avx2_gatherdi<mode>" - [(set (match_operand:AVXMODE48P_DI 0 "register_operand" "=&x") - (unspec:AVXMODE48P_DI - [(match_operand:AVXMODE48P_DI 2 "register_operand" "0") + [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") + (unspec:VEC_GATHER_MODE + [(match_operand:<VEC_GATHER_SRCDI> 2 "register_operand" "0") (match_operator:<ssescalarmode> 7 "vsib_mem_operator" [(unspec:P [(match_operand:P 3 "vsib_address_operand" "p") - (match_operand:<AVXMODE48P_DI> 4 "register_operand" "x") + (match_operand:<VEC_GATHER_IDXDI> 4 "register_operand" "x") (match_operand:SI 6 "const1248_operand" "n")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) - (match_operand:AVXMODE48P_DI 5 "register_operand" "1")] + (match_operand:<VEC_GATHER_SRCDI> 5 "register_operand" "1")] UNSPEC_GATHER)) - (clobber (match_scratch:AVXMODE48P_DI 1 "=&x"))] + (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "v<sseintprefix>gatherq<ssemodesuffix>\t{%1, %7, %0|%0, %7, %1}" + "v<sseintprefix>gatherq<ssemodesuffix>\t{%5, %7, %2|%2, %7, %5}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "<sseinsnmode>")]) -;; Special handling for VEX.256 with float arguments -;; since there're still xmms as operands -(define_expand "avx2_gatherdi<mode>256" - [(parallel [(set (match_operand:VI4F_128 0 "register_operand" "") - (unspec:VI4F_128 - [(match_operand:VI4F_128 1 "register_operand" "") - (mem:<ssescalarmode> - (match_par_dup 7 - [(match_operand 2 "vsib_address_operand" "") - (match_operand:V4DI 3 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")])) - (mem:BLK (scratch)) - (match_operand:VI4F_128 4 "register_operand" "")] - UNSPEC_GATHER)) - (clobber (match_scratch:VI4F_128 6 ""))])] - "TARGET_AVX2" -{ - operands[7] - = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[2], operands[3], - operands[5]), UNSPEC_VSIBADDR); -}) - -(define_insn "*avx2_gatherdi<mode>256" - [(set (match_operand:VI4F_128 0 "register_operand" "=x") - (unspec:VI4F_128 - [(match_operand:VI4F_128 2 "register_operand" "0") - (match_operator:<ssescalarmode> 7 "vsib_mem_operator" +(define_insn "*avx2_gatherdi<mode>_2" + [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") + (unspec:VEC_GATHER_MODE + [(pc) + (match_operator:<ssescalarmode> 6 "vsib_mem_operator" [(unspec:P - [(match_operand:P 3 "vsib_address_operand" "p") - (match_operand:V4DI 4 "register_operand" "x") - (match_operand:SI 6 "const1248_operand" "n")] + [(match_operand:P 2 "vsib_address_operand" "p") + (match_operand:<VEC_GATHER_IDXDI> 3 "register_operand" "x") + (match_operand:SI 5 "const1248_operand" "n")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) - (match_operand:VI4F_128 5 "register_operand" "1")] - UNSPEC_GATHER)) - (clobber (match_scratch:VI4F_128 1 "=&x"))] + (match_operand:<VEC_GATHER_SRCDI> 4 "register_operand" "1")] + UNSPEC_GATHER)) + (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "v<sseintprefix>gatherq<ssemodesuffix>\t{%1, %7, %0|%0, %7, %1}" +{ + if (<MODE>mode != <VEC_GATHER_SRCDI>mode) + return "v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %x0|%x0, %6, %4}"; + return "v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %0|%0, %6, %4}"; +} [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "<sseinsnmode>")]) diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 20378d090bf..0ff17123f27 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -18,31 +18,27 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -(define_mode_iterator CASMODE - [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B") - (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) -(define_mode_iterator DCASMODE - [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic") - (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) -(define_mode_attr doublemodesuffix [(DI "8") (TI "16")]) -(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")]) - -(define_expand "memory_barrier" - [(set (match_dup 0) - (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] +(define_expand "mem_thread_fence" + [(match_operand:SI 0 "const_int_operand" "")] ;; model "" { - operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); - MEM_VOLATILE_P (operands[0]) = 1; + /* Unless this is a SEQ_CST fence, the i386 memory model is strong + enough not to require barriers of any kind. */ + if (INTVAL (operands[0]) != MEMMODEL_SEQ_CST) + DONE; - if (!(TARGET_64BIT || TARGET_SSE2)) + if (TARGET_64BIT || TARGET_SSE2) + emit_insn (gen_sse2_mfence ()); + else { - emit_insn (gen_memory_barrier_nosse (operands[0])); - DONE; + rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (mem) = 1; + emit_insn (gen_mfence_nosse (mem)); } + DONE; }) -(define_insn "memory_barrier_nosse" +(define_insn "mfence_nosse" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE)) (clobber (reg:CC FLAGS_REG))] @@ -50,127 +46,315 @@ "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}" [(set_attr "memory" "unknown")]) -;; ??? It would be possible to use cmpxchg8b on pentium for DImode -;; changes. It's complicated because the insn uses ecx:ebx as the -;; new value; note that the registers are reversed from the order -;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode -;; data in 64-bit mode. - -(define_expand "sync_compare_and_swap<mode>" - [(parallel - [(set (match_operand:CASMODE 0 "register_operand" "") - (match_operand:CASMODE 1 "memory_operand" "")) - (set (match_dup 1) - (unspec_volatile:CASMODE - [(match_dup 1) - (match_operand:CASMODE 2 "register_operand" "") - (match_operand:CASMODE 3 "register_operand" "")] - UNSPECV_CMPXCHG)) - (set (reg:CCZ FLAGS_REG) - (compare:CCZ - (unspec_volatile:CASMODE - [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG) - (match_dup 2)))])] - "TARGET_CMPXCHG" +;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations, +;; Only beginning at Pentium family processors do we get any guarantee of +;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a +;; guarantee for 64-bit accesses that do not cross a cacheline boundary. +;; +;; Note that the TARGET_CMPXCHG8B test below is a stand-in for "Pentium". +;; +;; Importantly, *no* processor makes atomicity guarantees for larger +;; accesses. In particular, there's no way to perform an atomic TImode +;; move, despite the apparent applicability of MOVDQA et al. + +(define_mode_iterator ATOMIC + [QI HI SI + (DI "TARGET_64BIT || (TARGET_CMPXCHG8B && (TARGET_80387 || TARGET_SSE))") + ]) + +(define_expand "atomic_load<mode>" + [(set (match_operand:ATOMIC 0 "register_operand" "") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + UNSPEC_MOVA))] + "" +{ + /* For DImode on 32-bit, we can use the FPU to perform the load. */ + if (<MODE>mode == DImode && !TARGET_64BIT) + emit_insn (gen_atomic_loaddi_fpu + (operands[0], operands[1], + assign_386_stack_local (DImode, + (virtuals_instantiated + ? SLOT_TEMP : SLOT_VIRTUAL)))); + else + emit_move_insn (operands[0], operands[1]); + DONE; +}) + +(define_insn_and_split "atomic_loaddi_fpu" + [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m,?r") + (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m,m")] + UNSPEC_MOVA)) + (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) + (clobber (match_scratch:DF 3 "=X,xf,xf"))] + "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dst = operands[0], src = operands[1]; + rtx mem = operands[2], tmp = operands[3]; + + if (SSE_REG_P (dst)) + emit_move_insn (dst, src); + else + { + if (MEM_P (dst)) + mem = dst; + + if (FP_REG_P (tmp)) + emit_insn (gen_movdi_via_fpu (mem, src, tmp)); + else + { + adjust_reg_mode (tmp, DImode); + emit_move_insn (tmp, src); + emit_move_insn (mem, tmp); + } + + if (mem != dst) + emit_move_insn (dst, mem); + } + DONE; +}) + +(define_expand "atomic_store<mode>" + [(set (match_operand:ATOMIC 0 "memory_operand" "") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + UNSPEC_MOVA))] + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + if (<MODE>mode == DImode && !TARGET_64BIT) + { + /* For DImode on 32-bit, we can use the FPU to perform the store. */ + /* Note that while we could perform a cmpxchg8b loop, that turns + out to be significantly larger than this plus a barrier. */ + emit_insn (gen_atomic_storedi_fpu + (operands[0], operands[1], + assign_386_stack_local (DImode, + (virtuals_instantiated + ? SLOT_TEMP : SLOT_VIRTUAL)))); + } + else + { + /* For seq-cst stores, when we lack MFENCE, use XCHG. */ + if (model == MEMMODEL_SEQ_CST && !(TARGET_64BIT || TARGET_SSE2)) + { + emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode), + operands[0], operands[1], + operands[2])); + DONE; + } + + /* Otherwise use a normal store. */ + emit_move_insn (operands[0], operands[1]); + } + /* ... followed by an MFENCE, if required. */ + if (model == MEMMODEL_SEQ_CST) + emit_insn (gen_mem_thread_fence (operands[2])); + DONE; +}) + +(define_insn_and_split "atomic_storedi_fpu" + [(set (match_operand:DI 0 "memory_operand" "=m,m,m") + (unspec:DI [(match_operand:DI 1 "register_operand" "x,m,?r")] + UNSPEC_MOVA)) + (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) + (clobber (match_scratch:DF 3 "=X,xf,xf"))] + "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" + "#" + "&& reload_completed" + [(const_int 0)] { - if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode) + rtx dst = operands[0], src = operands[1]; + rtx mem = operands[2], tmp = operands[3]; + + if (!SSE_REG_P (src)) { - enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode; - rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0); - rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode, - GET_MODE_SIZE (hmode)); - low = force_reg (hmode, low); - high = force_reg (hmode, high); - if (<MODE>mode == DImode) + if (REG_P (src)) + { + emit_move_insn (mem, src); + src = mem; + } + + if (FP_REG_P (tmp)) { - if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode)) - operands[1] = replace_equiv_address (operands[1], - force_reg (Pmode, - XEXP (operands[1], - 0))); - emit_insn (gen_sync_double_compare_and_swapdi - (operands[0], operands[1], operands[2], low, high)); + emit_insn (gen_movdi_via_fpu (dst, src, tmp)); + DONE; } - else if (<MODE>mode == TImode) - emit_insn (gen_sync_double_compare_and_swapti - (operands[0], operands[1], operands[2], low, high)); else - gcc_unreachable (); - DONE; + { + adjust_reg_mode (tmp, DImode); + emit_move_insn (tmp, mem); + src = tmp; + } } + emit_move_insn (dst, src); + DONE; +}) + +;; ??? You'd think that we'd be able to perform this via FLOAT + FIX_TRUNC +;; operations. But the fix_trunc patterns want way more setup than we want +;; to provide. Note that the scratch is DFmode instead of XFmode in order +;; to make it easy to allocate a scratch in either SSE or FP_REGs above. +(define_insn "movdi_via_fpu" + [(set (match_operand:DI 0 "memory_operand" "=m") + (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_MOVA)) + (clobber (match_operand:DF 2 "register_operand" "=f"))] + "TARGET_80387" + "fild\t%1\;fistp\t%0" + [(set_attr "type" "multi") + ;; Worst case based on full sib+offset32 addressing modes + (set_attr "length" "14")]) + +(define_expand "atomic_compare_and_swap<mode>" + [(match_operand:QI 0 "register_operand" "") ;; bool success output + (match_operand:SWI124 1 "register_operand" "") ;; oldval output + (match_operand:SWI124 2 "memory_operand" "") ;; memory + (match_operand:SWI124 3 "register_operand" "") ;; expected input + (match_operand:SWI124 4 "register_operand" "") ;; newval input + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; success model + (match_operand:SI 7 "const_int_operand" "")] ;; failure model + "TARGET_CMPXCHG" +{ + emit_insn (gen_atomic_compare_and_swap_single<mode> + (operands[1], operands[2], operands[3], operands[4])); + ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), + const0_rtx); + DONE; }) -(define_insn "*sync_compare_and_swap<mode>" +(define_mode_iterator CASMODE + [(DI "TARGET_64BIT || TARGET_CMPXCHG8B") + (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) +(define_mode_iterator DCASMODE + [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic") + (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) +(define_mode_attr doublemodesuffix [(DI "8") (TI "16")]) +(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")]) + +(define_expand "atomic_compare_and_swap<mode>" + [(match_operand:QI 0 "register_operand" "") ;; bool success output + (match_operand:CASMODE 1 "register_operand" "") ;; oldval output + (match_operand:CASMODE 2 "memory_operand" "") ;; memory + (match_operand:CASMODE 3 "register_operand" "") ;; expected input + (match_operand:CASMODE 4 "register_operand" "") ;; newval input + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; success model + (match_operand:SI 7 "const_int_operand" "")] ;; failure model + "TARGET_CMPXCHG" +{ + if (<MODE>mode == DImode && TARGET_64BIT) + { + emit_insn (gen_atomic_compare_and_swap_singledi + (operands[1], operands[2], operands[3], operands[4])); + } + else + { + enum machine_mode hmode = <DCASHMODE>mode; + rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n, mem; + + lo_o = operands[1]; + mem = operands[2]; + lo_e = operands[3]; + lo_n = operands[4]; + hi_o = gen_highpart (hmode, lo_o); + hi_e = gen_highpart (hmode, lo_e); + hi_n = gen_highpart (hmode, lo_n); + lo_o = gen_lowpart (hmode, lo_o); + lo_e = gen_lowpart (hmode, lo_e); + lo_n = gen_lowpart (hmode, lo_n); + + if (<MODE>mode == DImode + && !TARGET_64BIT + && flag_pic + && !cmpxchg8b_pic_memory_operand (mem, DImode)) + mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0))); + + emit_insn (gen_atomic_compare_and_swap_double<mode> + (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n)); + } + ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), + const0_rtx); + DONE; +}) + +(define_insn "atomic_compare_and_swap_single<mode>" [(set (match_operand:SWI 0 "register_operand" "=a") - (match_operand:SWI 1 "memory_operand" "+m")) - (set (match_dup 1) (unspec_volatile:SWI - [(match_dup 1) - (match_operand:SWI 2 "register_operand" "a") + [(match_operand:SWI 1 "memory_operand" "+m") + (match_operand:SWI 2 "register_operand" "0") (match_operand:SWI 3 "register_operand" "<r>")] - UNSPECV_CMPXCHG)) + UNSPECV_CMPXCHG_1)) + (set (match_dup 1) + (unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG_2)) (set (reg:CCZ FLAGS_REG) - (compare:CCZ - (unspec_volatile:SWI - [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG) - (match_dup 2)))] + (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_3))] "TARGET_CMPXCHG" "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}") -(define_insn "sync_double_compare_and_swap<mode>" - [(set (match_operand:DCASMODE 0 "register_operand" "=A") - (match_operand:DCASMODE 1 "memory_operand" "+m")) - (set (match_dup 1) - (unspec_volatile:DCASMODE - [(match_dup 1) - (match_operand:DCASMODE 2 "register_operand" "A") - (match_operand:<DCASHMODE> 3 "register_operand" "b") - (match_operand:<DCASHMODE> 4 "register_operand" "c")] - UNSPECV_CMPXCHG)) +;; For double-word compare and swap, we are obliged to play tricks with +;; the input newval (op5:op6) because the Intel register numbering does +;; not match the gcc register numbering, so the pair must be CX:BX. +;; That said, in order to take advantage of possible lower-subreg opts, +;; treat all of the integral operands in the same way. +(define_insn "atomic_compare_and_swap_double<mode>" + [(set (match_operand:<DCASHMODE> 0 "register_operand" "=a") + (unspec_volatile:<DCASHMODE> + [(match_operand:DCASMODE 2 "memory_operand" "+m") + (match_operand:<DCASHMODE> 3 "register_operand" "0") + (match_operand:<DCASHMODE> 4 "register_operand" "1") + (match_operand:<DCASHMODE> 5 "register_operand" "b") + (match_operand:<DCASHMODE> 6 "register_operand" "c")] + UNSPECV_CMPXCHG_1)) + (set (match_operand:<DCASHMODE> 1 "register_operand" "=d") + (unspec_volatile:<DCASHMODE> [(const_int 0)] UNSPECV_CMPXCHG_2)) + (set (match_dup 2) + (unspec_volatile:DCASMODE [(const_int 0)] UNSPECV_CMPXCHG_3)) (set (reg:CCZ FLAGS_REG) - (compare:CCZ - (unspec_volatile:DCASMODE - [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)] - UNSPECV_CMPXCHG) - (match_dup 2)))] + (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))] "" - "lock{%;} cmpxchg<doublemodesuffix>b\t%1") - -;; Theoretically we'd like to use constraint "r" (any reg) for operand -;; 3, but that includes ecx. If operand 3 and 4 are the same (like when -;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like -;; operand 4. This breaks, as the xchg will move the PIC register contents -;; to %ecx then --> boom. Operands 3 and 4 really need to be different -;; registers, which in this case means operand 3 must not be ecx. -;; Instead of playing tricks with fake early clobbers or the like we -;; just enumerate all regs possible here, which (as this is !TARGET_64BIT) + "lock{%;} cmpxchg<doublemodesuffix>b\t%2") + +;; Theoretically we'd like to use constraint "r" (any reg) for op5, +;; but that includes ecx. If op5 and op6 are the same (like when +;; the input is -1LL) GCC might chose to allocate op5 to ecx, like +;; op6. This breaks, as the xchg will move the PIC register contents +;; to %ecx then --> boom. Operands 5 and 6 really need to be different +;; registers, which in this case means op5 must not be ecx. Instead +;; of playing tricks with fake early clobbers or the like we just +;; enumerate all regs possible here, which (as this is !TARGET_64BIT) ;; are just esi and edi. -(define_insn "*sync_double_compare_and_swapdi_pic" - [(set (match_operand:DI 0 "register_operand" "=A") - (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m")) - (set (match_dup 1) - (unspec_volatile:DI - [(match_dup 1) - (match_operand:DI 2 "register_operand" "A") - (match_operand:SI 3 "register_operand" "SD") - (match_operand:SI 4 "register_operand" "c")] - UNSPECV_CMPXCHG)) +(define_insn "*atomic_compare_and_swap_doubledi_pic" + [(set (match_operand:SI 0 "register_operand" "=a") + (unspec_volatile:SI + [(match_operand:DI 2 "cmpxchg8b_pic_memory_operand" "+m") + (match_operand:SI 3 "register_operand" "0") + (match_operand:SI 4 "register_operand" "1") + (match_operand:SI 5 "register_operand" "SD") + (match_operand:SI 6 "register_operand" "c")] + UNSPECV_CMPXCHG_1)) + (set (match_operand:SI 1 "register_operand" "=d") + (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_2)) + (set (match_dup 2) + (unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG_3)) (set (reg:CCZ FLAGS_REG) - (compare:CCZ - (unspec_volatile:DI - [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)] - UNSPECV_CMPXCHG) - (match_dup 2)))] + (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))] "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic" - "xchg{l}\t%%ebx, %3\;lock{%;} cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3") + "xchg{l}\t%%ebx, %5\;lock{%;} cmpxchg8b\t%2\;xchg{l}\t%%ebx, %5") ;; For operand 2 nonmemory_operand predicate is used instead of ;; register_operand to allow combiner to better optimize atomic ;; additions of constants. -(define_insn "sync_old_add<mode>" +(define_insn "atomic_fetch_add<mode>" [(set (match_operand:SWI 0 "register_operand" "=<r>") (unspec_volatile:SWI - [(match_operand:SWI 1 "memory_operand" "+m")] UNSPECV_XCHG)) + [(match_operand:SWI 1 "memory_operand" "+m") + (match_operand:SI 3 "const_int_operand" "")] ;; model + UNSPECV_XCHG)) (set (match_dup 1) (plus:SWI (match_dup 1) (match_operand:SWI 2 "nonmemory_operand" "0"))) @@ -186,7 +370,9 @@ (match_operand:SWI 2 "const_int_operand" "")) (parallel [(set (match_dup 0) (unspec_volatile:SWI - [(match_operand:SWI 1 "memory_operand" "")] UNSPECV_XCHG)) + [(match_operand:SWI 1 "memory_operand" "") + (match_operand:SI 4 "const_int_operand" "")] + UNSPECV_XCHG)) (set (match_dup 1) (plus:SWI (match_dup 1) (match_dup 0))) @@ -199,17 +385,19 @@ == -(unsigned HOST_WIDE_INT) INTVAL (operands[3]) && !reg_overlap_mentioned_p (operands[0], operands[1])" [(parallel [(set (reg:CCZ FLAGS_REG) - (compare:CCZ (unspec_volatile:SWI [(match_dup 1)] - UNSPECV_XCHG) - (match_dup 3))) + (compare:CCZ + (unspec_volatile:SWI [(match_dup 1) (match_dup 4)] + UNSPECV_XCHG) + (match_dup 3))) (set (match_dup 1) (plus:SWI (match_dup 1) (match_dup 2)))])]) -(define_insn "*sync_old_add_cmp<mode>" +(define_insn "*atomic_fetch_add_cmp<mode>" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (unspec_volatile:SWI - [(match_operand:SWI 0 "memory_operand" "+m")] + [(match_operand:SWI 0 "memory_operand" "+m") + (match_operand:SI 3 "const_int_operand" "")] UNSPECV_XCHG) (match_operand:SWI 2 "const_int_operand" "i"))) (set (match_dup 0) @@ -233,20 +421,24 @@ }) ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space. -(define_insn "sync_lock_test_and_set<mode>" - [(set (match_operand:SWI 0 "register_operand" "=<r>") +;; In addition, it is always a full barrier, so we can ignore the memory model. +(define_insn "atomic_exchange<mode>" + [(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output (unspec_volatile:SWI - [(match_operand:SWI 1 "memory_operand" "+m")] UNSPECV_XCHG)) + [(match_operand:SWI 1 "memory_operand" "+m") ;; memory + (match_operand:SI 3 "const_int_operand" "")] ;; model + UNSPECV_XCHG)) (set (match_dup 1) - (match_operand:SWI 2 "register_operand" "0"))] + (match_operand:SWI 2 "register_operand" "0"))] ;; input "" "xchg{<imodesuffix>}\t{%1, %0|%0, %1}") -(define_insn "sync_add<mode>" +(define_insn "atomic_add<mode>" [(set (match_operand:SWI 0 "memory_operand" "+m") (unspec_volatile:SWI [(plus:SWI (match_dup 0) - (match_operand:SWI 1 "nonmemory_operand" "<r><i>"))] + (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) + (match_operand:SI 2 "const_int_operand" "")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" @@ -265,11 +457,12 @@ return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; }) -(define_insn "sync_sub<mode>" +(define_insn "atomic_sub<mode>" [(set (match_operand:SWI 0 "memory_operand" "+m") (unspec_volatile:SWI [(minus:SWI (match_dup 0) - (match_operand:SWI 1 "nonmemory_operand" "<r><i>"))] + (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) + (match_operand:SI 2 "const_int_operand" "")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" @@ -282,14 +475,18 @@ return "lock{%;} inc{<imodesuffix>}\t%0"; } + if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) + return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; + return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; }) -(define_insn "sync_<code><mode>" +(define_insn "atomic_<code><mode>" [(set (match_operand:SWI 0 "memory_operand" "+m") (unspec_volatile:SWI [(any_logic:SWI (match_dup 0) - (match_operand:SWI 1 "nonmemory_operand" "<r><i>"))] + (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) + (match_operand:SI 2 "const_int_operand" "")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" diff --git a/gcc/config/i386/t-crtstuff b/gcc/config/i386/t-crtstuff deleted file mode 100644 index c14dd9411ae..00000000000 --- a/gcc/config/i386/t-crtstuff +++ /dev/null @@ -1,7 +0,0 @@ -# The pushl in CTOR initialization interferes with frame pointer elimination. -# crtend*.o cannot be compiled without -fno-asynchronous-unwind-tables, -# because then __FRAME_END__ might not be the last thing in .eh_frame -# section. -fno-asynchronous-unwind-tables is off by default for i386 -# and is on by default for x86-64. We turn it off for both i386 and -# x86-64. -CRTSTUFF_T_CFLAGS += -fno-omit-frame-pointer -fno-asynchronous-unwind-tables diff --git a/gcc/config/i386/t-cygming b/gcc/config/i386/t-cygming index af2c9e41c4d..18b57c4152a 100644 --- a/gcc/config/i386/t-cygming +++ b/gcc/config/i386/t-cygming @@ -1,4 +1,5 @@ -# Copyright (C) 2003, 2005, 2008, 2009, 2010 Free Software Foundation, Inc. +# Copyright (C) 2003, 2005, 2008, 2009, 2010, 2011 +# Free Software Foundation, Inc. # # This file is part of GCC. # @@ -16,18 +17,10 @@ # along with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. -LIB1ASMSRC = i386/cygwin.asm -LIB1ASMFUNCS = _chkstk _chkstk_ms - # cygwin and mingw always have a limits.h, but, depending upon how we are # doing the build, it may not be installed yet. LIMITS_H_TEST = true -# If we are building next to winsup, this will let us find the real -# limits.h when building libgcc2. Otherwise, winsup must be installed -# first. -LIBGCC2_INCLUDES = -I$(srcdir)/../winsup/w32api/include - winnt.o: $(srcdir)/config/i386/winnt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h output.h $(TREE_H) flags.h \ $(TM_P_H) $(HASHTAB_H) $(GGC_H) $(LTO_STREAMER_H) @@ -54,63 +47,3 @@ msformat-c.o: $(srcdir)/config/i386/msformat-c.c $(CONFIG_H) $(SYSTEM_H) coretyp $(srcdir)/config/i386/msformat-c.c STMP_FIXINC=stmp-fixinc - -# Build a shared libgcc library for PECOFF with a DEF file -# with the GNU linker. -# -# mkmap-flat.awk is used with the pe_dll option to produce a DEF instead -# of an ELF map file. -# -# Warning: If SHLIB_SOVERSION or SHLIB_SONAME are updated, LIBGCC_SONAME -# in mingw32.h and SHLIB_MKMAP_OPTS below must be updated also. - -SHLIB_EXT = .dll -SHLIB_IMPLIB = @shlib_base_name@.a -SHLIB_SOVERSION = 1 -SHLIB_SONAME = @shlib_base_name@_$(EH_MODEL)-$(SHLIB_SOVERSION)$(SHLIB_EXT) -SHLIB_MAP = @shlib_map_file@ -SHLIB_OBJS = @shlib_objs@ -SHLIB_DIR = @multilib_dir@/shlib -SHLIB_SLIBDIR_QUAL = @shlib_slibdir_qual@ -# SHLIB_DLLDIR is defined by including one of either t-dlldir or t-dlldir-x -# (native/cross build respectively) in the tmake_file list in gcc/config.gcc. -ifndef SHLIB_DLLDIR -$(error SHLIB_DLLDIR must be defined) -endif -ifndef SHLIB_PTHREAD_CFLAG -SHLIB_PTHREAD_CFLAG = -endif -ifndef SHLIB_PTHREAD_LDFLAG -SHLIB_PTHREAD_LDFLAG = -endif - -SHLIB_LINK = $(LN_S) -f $(SHLIB_MAP) $(SHLIB_MAP).def && \ - if [ ! -d $(SHLIB_DIR) ]; then \ - mkdir $(SHLIB_DIR); \ - else true; fi && \ - $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(SHLIB_PTHREAD_CFLAG) \ - -shared -nodefaultlibs \ - $(SHLIB_MAP).def \ - -Wl,--out-implib,$(SHLIB_DIR)/$(SHLIB_IMPLIB).tmp \ - -o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ \ - $(SHLIB_OBJS) ${SHLIB_PTHREAD_LDFLAG} $(SHLIB_LC) && \ - if [ -f $(SHLIB_DIR)/$(SHLIB_SONAME) ]; then \ - mv -f $(SHLIB_DIR)/$(SHLIB_SONAME) \ - $(SHLIB_DIR)/$(SHLIB_SONAME).backup; \ - else true; fi && \ - mv $(SHLIB_DIR)/$(SHLIB_SONAME).tmp $(SHLIB_DIR)/$(SHLIB_SONAME) && \ - mv $(SHLIB_DIR)/$(SHLIB_IMPLIB).tmp $(SHLIB_DIR)/$(SHLIB_IMPLIB) -# $(slibdir) double quoted to protect it from expansion while building -# libgcc.mk. We want this delayed until actual install time. -SHLIB_INSTALL = \ - $$(mkinstalldirs) $$(DESTDIR)$$(SHLIB_DLLDIR) \ - $$(DESTDIR)$$(slibdir)$(SHLIB_SLIBDIR_QUAL); \ - $(INSTALL) $(SHLIB_DIR)/$(SHLIB_SONAME) \ - $$(DESTDIR)$$(SHLIB_DLLDIR)/$(SHLIB_SONAME); \ - $(INSTALL_DATA) $(SHLIB_DIR)/$(SHLIB_IMPLIB) \ - $$(DESTDIR)$$(slibdir)$(SHLIB_SLIBDIR_QUAL)/$(SHLIB_IMPLIB) -SHLIB_MKMAP = $(srcdir)/mkmap-flat.awk -# We'd like to use SHLIB_SONAME here too, but shlib_base_name -# does not get substituted before mkmap-flat.awk is run. -SHLIB_MKMAP_OPTS = -v pe_dll=libgcc_s_$(EH_MODEL)-$(SHLIB_SOVERSION)$(SHLIB_EXT) -SHLIB_MAPFILES = $$(libgcc_objdir)/libgcc-std.ver diff --git a/gcc/config/i386/t-cygwin b/gcc/config/i386/t-cygwin deleted file mode 100644 index f5eda91c0ef..00000000000 --- a/gcc/config/i386/t-cygwin +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2008, 2009, 2010 -# Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. - -# If we are building next to winsup, this will let us find the real -# limits.h when building libgcc2. Otherwise, winsup must be installed -# first. -LIBGCC2_INCLUDES += -I$(srcdir)/../winsup/include \ - -I$(srcdir)/../winsup/cygwin/include - -# Cygwin-specific parts of LIB_SPEC -SHLIB_LC = -lcygwin -ladvapi32 -lshell32 -luser32 -lkernel32 - -# We have already included one of the t-{dw2,sjlj}-eh fragments for EH_MODEL -SHLIB_EH_EXTENSION = $(subst -dw2,,-$(EH_MODEL)) - -# Cygwin uses different conventions than MinGW; override generic SHLIB_ def'ns here. -SHLIB_IMPLIB = @shlib_base_name@$(SHLIB_EXT).a -SHLIB_SONAME = cyggcc_s$(SHLIB_EH_EXTENSION)-$(SHLIB_SOVERSION)$(SHLIB_EXT) -# This must match the definitions of SHLIB_SONAME/SHLIB_SOVERSION and LIBGCC_SONAME. -# We'd like to use SHLIB_SONAME here too, and we can, since -# we don't rely on shlib_base_name substitution for it. -SHLIB_MKMAP_OPTS = -v pe_dll=$(SHLIB_SONAME) - diff --git a/gcc/config/i386/t-darwin b/gcc/config/i386/t-darwin index 22323e4abee..bf44504d4fd 100644 --- a/gcc/config/i386/t-darwin +++ b/gcc/config/i386/t-darwin @@ -1,5 +1,2 @@ MULTILIB_OPTIONS = m64 MULTILIB_DIRNAMES = x86_64 -LIB2_SIDITI_CONV_FUNCS=yes -LIB2FUNCS_EXTRA = $(srcdir)/config/darwin-64.c -LIB2FUNCS_EXCLUDE = _fixtfdi _fixunstfdi _floatditf _floatunditf diff --git a/gcc/config/i386/t-darwin64 b/gcc/config/i386/t-darwin64 index 81b4565ac72..6a6b22f1ee5 100644 --- a/gcc/config/i386/t-darwin64 +++ b/gcc/config/i386/t-darwin64 @@ -1,8 +1,2 @@ -LIB2_SIDITI_CONV_FUNCS=yes -LIB2FUNCS_EXTRA = $(srcdir)/config/darwin-64.c - MULTILIB_OPTIONS = m32 MULTILIB_DIRNAMES = i386 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/i386/t-dlldir b/gcc/config/i386/t-dlldir deleted file mode 100644 index a3e03317a04..00000000000 --- a/gcc/config/i386/t-dlldir +++ /dev/null @@ -1,6 +0,0 @@ - -# In a native build, target DLLs go in bindir, where they can be executed. -# Note double quoting to prevent variables from being evaluated until install -# time; we don't want to expand them during libgcc.mvars generation. - -SHLIB_DLLDIR = $$(bindir) diff --git a/gcc/config/i386/t-dlldir-x b/gcc/config/i386/t-dlldir-x deleted file mode 100644 index 07dd845f0a6..00000000000 --- a/gcc/config/i386/t-dlldir-x +++ /dev/null @@ -1,9 +0,0 @@ - -# In a cross build, bindir contains host not target binaries, so target DLLs -# instead go in toolexeclibdir, alongside other target binaries and static libs. -# Note double quoting to prevent variables from being evaluated until install -# time; we don't want to expand them during libgcc.mvars generation, and in -# any case, $toolexeclibdir is not defined in the gcc/ subdirectory, only in -# target lib directories. - -SHLIB_DLLDIR = $$(toolexeclibdir) diff --git a/gcc/config/i386/t-dw2-eh b/gcc/config/i386/t-dw2-eh deleted file mode 100644 index ffcc39aea33..00000000000 --- a/gcc/config/i386/t-dw2-eh +++ /dev/null @@ -1,3 +0,0 @@ - -# We are using Dwarf-2 EH. -EH_MODEL = dw2 diff --git a/gcc/config/i386/t-gthr-win32 b/gcc/config/i386/t-gthr-win32 deleted file mode 100644 index f67fa1e25a8..00000000000 --- a/gcc/config/i386/t-gthr-win32 +++ /dev/null @@ -1,2 +0,0 @@ -# We hide calls to w32api needed for w32 thread support here: -LIB2FUNCS_EXTRA = $(srcdir)/config/i386/gthr-win32.c diff --git a/gcc/config/i386/t-i386elf b/gcc/config/i386/t-i386elf deleted file mode 100644 index 9560d905521..00000000000 --- a/gcc/config/i386/t-i386elf +++ /dev/null @@ -1,4 +0,0 @@ -# For svr4 we build crtbegin.o and crtend.o which serve to add begin and -# end labels to the .ctors and .dtors section when we link using gcc. - -EXTRA_PARTS=crtbegin.o crtend.o diff --git a/gcc/config/i386/t-interix b/gcc/config/i386/t-interix index e7b016f1e7a..09c9127f6af 100644 --- a/gcc/config/i386/t-interix +++ b/gcc/config/i386/t-interix @@ -1,6 +1,3 @@ -LIB1ASMSRC = i386/cygwin.asm -LIB1ASMFUNCS = _chkstk _chkstk_ms - winnt.o: $(srcdir)/config/i386/winnt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h output.h $(TREE_H) flags.h \ $(TM_P_H) $(HASHTAB_H) $(GGC_H) diff --git a/gcc/config/i386/t-linux b/gcc/config/i386/t-linux deleted file mode 100644 index 500d932fec8..00000000000 --- a/gcc/config/i386/t-linux +++ /dev/null @@ -1,5 +0,0 @@ -# On 64bit we do not need any exports for glibc for 64-bit libgcc_s. -# Need to support TImode for x86. Override the settings from -# t-slibgcc-elf-ver and t-linux -SHLIB_MAPFILES = $$(libgcc_objdir)/libgcc-std.ver \ - $(srcdir)/config/i386/libgcc-glibc.ver diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64 index ea8f5e9d7ae..b5d39855a70 100644 --- a/gcc/config/i386/t-linux64 +++ b/gcc/config/i386/t-linux64 @@ -37,10 +37,3 @@ MULTILIB_DIRNAMES = $(patsubst m%, %, $(subst /, ,$(MULTILIB_OPTIONS))) MULTILIB_OSDIRNAMES = m64=../lib64 MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) MULTILIB_OSDIRNAMES+= mx32=../libx32 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o \ - crtbeginT.o crtprec32.o crtprec64.o crtprec80.o \ - crtfastmath.o diff --git a/gcc/config/i386/t-mingw-pthread b/gcc/config/i386/t-mingw-pthread deleted file mode 100644 index 622ef82be6e..00000000000 --- a/gcc/config/i386/t-mingw-pthread +++ /dev/null @@ -1,2 +0,0 @@ -SHLIB_PTHREAD_CFLAG = -pthread -SHLIB_PTHREAD_LDFLAG = -Wl,-lpthread diff --git a/gcc/config/i386/t-mingw-w32 b/gcc/config/i386/t-mingw-w32 index 83cee71f1c1..4fc8582cf5e 100644 --- a/gcc/config/i386/t-mingw-w32 +++ b/gcc/config/i386/t-mingw-w32 @@ -1,9 +1,3 @@ MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 MULTILIB_OSDIRNAMES = ../lib64 ../lib - -# MinGW-specific parts of LIB_SPEC -SHLIB_LC = -lmingwthrd -lmingw32 -lmingwex -lmoldname -lmsvcrt -ladvapi32 -lshell32 -luser32 -lkernel32 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/i386/t-mingw-w64 b/gcc/config/i386/t-mingw-w64 index 041a02f1018..c809ebd7d1d 100644 --- a/gcc/config/i386/t-mingw-w64 +++ b/gcc/config/i386/t-mingw-w64 @@ -1,9 +1,3 @@ MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 MULTILIB_OSDIRNAMES = ../lib ../lib32 - -# MinGW-specific parts of LIB_SPEC -SHLIB_LC = -lmingwthrd -lmingw32 -lmingwex -lmoldname -lmsvcrt -ladvapi32 -lshell32 -luser32 -lkernel32 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/i386/t-mingw32 b/gcc/config/i386/t-mingw32 deleted file mode 100644 index bfdef6723ce..00000000000 --- a/gcc/config/i386/t-mingw32 +++ /dev/null @@ -1,2 +0,0 @@ -# MinGW-specific parts of LIB_SPEC -SHLIB_LC = -lmingwthrd -lmingw32 -lmingwex -lmoldname -lmsvcrt -ladvapi32 -lshell32 -luser32 -lkernel32 diff --git a/gcc/config/i386/t-nto b/gcc/config/i386/t-nto deleted file mode 100644 index b80ff802927..00000000000 --- a/gcc/config/i386/t-nto +++ /dev/null @@ -1,4 +0,0 @@ -CRTSTUFF_T_CFLAGS = -fno-omit-frame-pointer -fPIC -TARGET_LIBGCC2_CFLAGS = -fPIC -fexceptions - -EXTRA_PARTS = crtbegin.o diff --git a/gcc/config/i386/t-openbsd b/gcc/config/i386/t-openbsd index 18304634000..4f8ff657a93 100644 --- a/gcc/config/i386/t-openbsd +++ b/gcc/config/i386/t-openbsd @@ -2,5 +2,3 @@ # We cope by building variants of libgcc. MULTILIB_OPTIONS = fpic MULTILIB_MATCHES=fpic=fPIC -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/i386/t-sjlj-eh b/gcc/config/i386/t-sjlj-eh deleted file mode 100644 index c9085f43216..00000000000 --- a/gcc/config/i386/t-sjlj-eh +++ /dev/null @@ -1,3 +0,0 @@ - -# We are using SjLj EH. -EH_MODEL = sjlj |