diff options
Diffstat (limited to 'gcc/config/arm')
27 files changed, 290 insertions, 3562 deletions
diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 35d2d96c9fd..a51121193ce 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -25,7 +25,6 @@ extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); extern int aarch_crypto_can_dual_issue (rtx_insn *, rtx_insn *); -extern int aarch_forward_to_shift_is_not_shifted_reg (rtx_insn *, rtx_insn *); extern bool aarch_rev16_p (rtx); extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); extern bool aarch_rev16_shright_mask_imm_p (rtx, machine_mode); diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index 6a04711335d..979f86e5bed 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -272,12 +272,7 @@ arm_no_early_alu_shift_dep (rtx producer, rtx consumer) return 0; if ((early_op = arm_find_shift_sub_rtx (op))) - { - if (REG_P (early_op)) - early_op = op; - - return !reg_overlap_mentioned_p (value, early_op); - } + return !reg_overlap_mentioned_p (value, early_op); return 0; } @@ -508,38 +503,6 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_insn *consumer) return (REGNO (dest) == REGNO (accumulator)); } -/* Return nonzero if the CONSUMER instruction is some sort of - arithmetic or logic + shift operation, and the register we are - writing in PRODUCER is not used in a register shift by register - operation. */ - -int -aarch_forward_to_shift_is_not_shifted_reg (rtx_insn *producer, - rtx_insn *consumer) -{ - rtx value, op; - rtx early_op; - - if (!arm_get_set_operands (producer, consumer, &value, &op)) - return 0; - - if ((early_op = arm_find_shift_sub_rtx (op))) - { - if (REG_P (early_op)) - early_op = op; - - /* Any other canonicalisation of a shift is a shift-by-constant - so we don't care. */ - if (GET_CODE (early_op) == ASHIFT) - return (!REG_P (XEXP (early_op, 0)) - || !REG_P (XEXP (early_op, 1))); - else - return 1; - } - - return 0; -} - /* Return non-zero if the consumer (a multiply-accumulate instruction) has an accumulator dependency on the result of the producer (a multiplication instruction) and no other dependency on that result. */ diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 8d14e58d916..7504ed581c6 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -27,6 +27,7 @@ #include "gimple-expr.h" #include "memmodel.h" #include "tm_p.h" +#include "profile-count.h" #include "optabs.h" #include "emit-rtl.h" #include "recog.h" @@ -807,7 +808,7 @@ arm_mangle_builtin_type (const_tree type) } static tree -arm_simd_builtin_std_type (enum machine_mode mode, +arm_simd_builtin_std_type (machine_mode mode, enum arm_type_qualifiers q) { #define QUAL_TYPE(M) \ @@ -845,7 +846,7 @@ arm_simd_builtin_std_type (enum machine_mode mode, } static tree -arm_lookup_simd_builtin_type (enum machine_mode mode, +arm_lookup_simd_builtin_type (machine_mode mode, enum arm_type_qualifiers q) { int i; @@ -867,8 +868,7 @@ arm_lookup_simd_builtin_type (enum machine_mode mode, } static tree -arm_simd_builtin_type (enum machine_mode mode, - bool unsigned_p, bool poly_p) +arm_simd_builtin_type (machine_mode mode, bool unsigned_p, bool poly_p) { if (poly_p) return arm_lookup_simd_builtin_type (mode, qualifier_poly); @@ -942,7 +942,7 @@ arm_init_simd_builtin_types (void) for (i = 0; i < nelts; i++) { tree eltype = arm_simd_types[i].eltype; - enum machine_mode mode = arm_simd_types[i].mode; + machine_mode mode = arm_simd_types[i].mode; if (arm_simd_types[i].itype == NULL) arm_simd_types[i].itype = @@ -2232,7 +2232,7 @@ arm_expand_builtin_args (rtx target, machine_mode map_mode, int fcode, gcc_assert (argc > 0); if (CONST_INT_P (op[argc])) { - enum machine_mode vmode = mode[argc - 1]; + machine_mode vmode = mode[argc - 1]; neon_lane_bounds (op[argc], 0, GET_MODE_NUNITS (vmode), exp); } /* If the lane index isn't a constant then the next @@ -3098,7 +3098,7 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in) NULL_TREE is returned if no such builtin is available. */ #undef ARM_CHECK_BUILTIN_MODE #define ARM_CHECK_BUILTIN_MODE(C) \ - (TARGET_FPU_ARMV8 \ + (TARGET_VFP5 \ && flag_unsafe_math_optimizations \ && ARM_CHECK_BUILTIN_MODE_1 (C)) diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index a3daa3220a2..9178937b6d9 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -96,7 +96,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) || TARGET_ARM_ARCH_ISA_THUMB >=2)); def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN", - TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8); + TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_VFP5); def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD); diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h deleted file mode 100644 index 8406fa05423..00000000000 --- a/gcc/config/arm/arm-cpu-cdata.h +++ /dev/null @@ -1,2584 +0,0 @@ -/* -*- buffer-read-only: t -*- - Generated automatically by parsecpu.awk from arm-cpus.in. - Do not edit. - - Copyright (C) 2011-2017 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public - License along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -static const cpu_arch_extension cpu_opttab_arm9e[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm946es[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm966es[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm968es[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm10e[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1020e[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1022e[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm926ejs[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_genericv7a[] = { - { - "vfpv3-d16", false, false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-fp16", false, false, - { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv4-d16", false, false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "simd", false, false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "neon-vfpv4", false, false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "neon", false, true, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv3", false, true, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa5[] = { - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa7[] = { - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa8[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa9[] = { - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa12[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa15[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa17[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr5[] = { - { - "nofp.dp", true, false, - { ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr7[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr8[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm7[] = { - { - "nofp.dp", true, false, - { ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm4[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa32[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa35[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa53[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa57[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa72[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_exynosm1[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_xgene1[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm33[] = { - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -const cpu_option all_cores[] = -{ - { - { - "arm2", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm250", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm3", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm6", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm60", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm600", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm610", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm620", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7d", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7di", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm70", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm700", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm700i", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm710", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm720", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm710c", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7100", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7500", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7500fe", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7m", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm7dm", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm7dmi", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm8", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "arm810", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm110", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm1100", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm1110", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "fa526", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "fa626", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "arm7tdmi", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm7tdmi-s", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm710t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm720t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm740t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm9", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm9tdmi", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm920", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm920t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm922t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm940t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "ep9312", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm10tdmi", - NULL, - { - ISA_ARMv5t, - isa_nobit - } - }, - TARGET_ARCH_armv5t - }, - { - { - "arm1020t", - NULL, - { - ISA_ARMv5t, - isa_nobit - } - }, - TARGET_ARCH_armv5t - }, - { - { - "arm9e", - cpu_opttab_arm9e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm946e-s", - cpu_opttab_arm946es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm966e-s", - cpu_opttab_arm966es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm968e-s", - cpu_opttab_arm968es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm10e", - cpu_opttab_arm10e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm1020e", - cpu_opttab_arm1020e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm1022e", - cpu_opttab_arm1022e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "xscale", - NULL, - { - ISA_ARMv5te, - isa_bit_xscale, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "iwmmxt", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - } - }, - TARGET_ARCH_iwmmxt - }, - { - { - "iwmmxt2", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - } - }, - TARGET_ARCH_iwmmxt2 - }, - { - { - "fa606te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fa626te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fmp626", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fa726te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm926ej-s", - cpu_opttab_arm926ejs, - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5tej - }, - { - { - "arm1026ej-s", - cpu_opttab_arm1026ejs, - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5tej - }, - { - { - "arm1136j-s", - NULL, - { - ISA_ARMv6j, - isa_nobit - } - }, - TARGET_ARCH_armv6j - }, - { - { - "arm1136jf-s", - NULL, - { - ISA_ARMv6j, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6j - }, - { - { - "arm1176jz-s", - NULL, - { - ISA_ARMv6kz, - isa_nobit - } - }, - TARGET_ARCH_armv6kz - }, - { - { - "arm1176jzf-s", - NULL, - { - ISA_ARMv6kz, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6kz - }, - { - { - "mpcorenovfp", - NULL, - { - ISA_ARMv6k, - isa_nobit - } - }, - TARGET_ARCH_armv6k - }, - { - { - "mpcore", - NULL, - { - ISA_ARMv6k, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6k - }, - { - { - "arm1156t2-s", - NULL, - { - ISA_ARMv6t2, - isa_nobit - } - }, - TARGET_ARCH_armv6t2 - }, - { - { - "arm1156t2f-s", - NULL, - { - ISA_ARMv6t2, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6t2 - }, - { - { - "cortex-m1", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0plus", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m1.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0plus.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "generic-armv7-a", - cpu_opttab_genericv7a, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a5", - cpu_opttab_cortexa5, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a7", - cpu_opttab_cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a8", - cpu_opttab_cortexa8, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a9", - cpu_opttab_cortexa9, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a12", - cpu_opttab_cortexa12, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a15", - cpu_opttab_cortexa15, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a17", - cpu_opttab_cortexa17, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-r4", - NULL, - { - ISA_ARMv7r, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r4f", - NULL, - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r5", - cpu_opttab_cortexr5, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r7", - cpu_opttab_cortexr7, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r8", - cpu_opttab_cortexr8, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-m7", - cpu_opttab_cortexm7, - { - ISA_ARMv7em, - ISA_FPv5,ISA_FP_DBL, - isa_quirk_no_volatile_ce, - isa_nobit - } - }, - TARGET_ARCH_armv7e_m - }, - { - { - "cortex-m4", - cpu_opttab_cortexm4, - { - ISA_ARMv7em, - ISA_VFPv4, - isa_nobit - } - }, - TARGET_ARCH_armv7e_m - }, - { - { - "cortex-m3", - NULL, - { - ISA_ARMv7m, - isa_quirk_cm3_ldrd, - isa_nobit - } - }, - TARGET_ARCH_armv7_m - }, - { - { - "marvell-pj4", - NULL, - { - ISA_ARMv7a, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a15.cortex-a7", - cpu_opttab_cortexa15cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a17.cortex-a7", - cpu_opttab_cortexa17cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a32", - cpu_opttab_cortexa32, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a35", - cpu_opttab_cortexa35, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a53", - cpu_opttab_cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a57", - cpu_opttab_cortexa57, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a72", - cpu_opttab_cortexa72, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73", - cpu_opttab_cortexa73, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "exynos-m1", - cpu_opttab_exynosm1, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "xgene1", - cpu_opttab_xgene1, - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a57.cortex-a53", - cpu_opttab_cortexa57cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a72.cortex-a53", - cpu_opttab_cortexa72cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73.cortex-a35", - cpu_opttab_cortexa73cortexa35, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73.cortex-a53", - cpu_opttab_cortexa73cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-m23", - NULL, - { - ISA_ARMv8m_base, - isa_nobit - } - }, - TARGET_ARCH_armv8_m_base - }, - { - { - "cortex-m33", - cpu_opttab_cortexm33, - { - ISA_ARMv8m_main, - isa_bit_ARMv7em, - ISA_FPv5, - isa_nobit - } - }, - TARGET_ARCH_armv8_m_main - }, - {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none} -}; -static const struct cpu_arch_extension arch_opttab_armv5e[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv5te[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv5tej[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6j[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6k[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6z[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6kz[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6zk[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6t2[] = { - { - "fp", false, false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv2", false, true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7[] = { - { - "fp", false, false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv3-d16", false, true, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7_a[] = { - { - "fp", false, false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-fp16", false, false, - { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv4-d16", false, false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "simd", false, false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "neon-vfpv4", false, false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv3-d16", false, true, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "neon", false, true, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv3", false, true, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7ve[] = { - { - "vfpv3-d16", false, false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-fp16", false, false, - { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "fp", false, false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "neon", false, false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "simd", false, false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nosimd", true, false, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv4-d16", false, true, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "neon-vfpv3", false, true, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv4", false, true, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7_r[] = { - { - "fp.sp", false, false, - { ISA_VFPv3, isa_nobit } - }, - { - "fp", false, false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "idiv", false, false, - { isa_bit_adiv, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "noidiv", true, false, - { isa_bit_adiv, isa_nobit } - }, - { - "vfpv3xd", false, true, - { ISA_VFPv3, isa_nobit } - }, - { - "vfpv3-d16", false, true, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { - { - "fp", false, false, - { ISA_VFPv4, isa_nobit } - }, - { - "fpv5", false, false, - { ISA_FPv5, isa_nobit } - }, - { - "fp.dp", false, false, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_a[] = { - { - "crc", false, false, - { isa_bit_crc32, isa_nobit } - }, - { - "simd", false, false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nocrypto", true, false, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { - { - "simd", false, false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nocrypto", true, false, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "vfpv4-sp-d16", false, true, - { ISA_VFPv4, isa_nobit } - }, - { - "fpv5-d16", false, true, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { - { - "simd", false, false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "fp16", false, false, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nocrypto", true, false, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { - { - "dsp", false, false, - { isa_bit_ARMv7em, isa_nobit } - }, - { - "fp", false, false, - { ISA_FPv5, isa_nobit } - }, - { - "fp.dp", false, false, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, false, - { ISA_ALL_FP, isa_nobit } - }, - { - "nodsp", true, false, - { isa_bit_ARMv7em, isa_nobit } - }, - { NULL, false, false, {isa_nobit}} -}; - -const arch_option all_architectures[] = -{ - { - "armv2", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - "2", BASE_ARCH_2, - TARGET_CPU_arm2, - }, - { - "armv2a", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - "2", BASE_ARCH_2, - TARGET_CPU_arm2, - }, - { - "armv3", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - "3", BASE_ARCH_3, - TARGET_CPU_arm6, - }, - { - "armv3m", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - "3M", BASE_ARCH_3M, - TARGET_CPU_arm7m, - }, - { - "armv4", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - "4", BASE_ARCH_4, - TARGET_CPU_arm7tdmi, - }, - { - "armv4t", - NULL, - { - ISA_ARMv4t, - isa_nobit - }, - "4T", BASE_ARCH_4T, - TARGET_CPU_arm7tdmi, - }, - { - "armv5", - NULL, - { - ISA_ARMv5, - isa_nobit - }, - "5", BASE_ARCH_5, - TARGET_CPU_arm10tdmi, - }, - { - "armv5t", - NULL, - { - ISA_ARMv5t, - isa_nobit - }, - "5T", BASE_ARCH_5T, - TARGET_CPU_arm10tdmi, - }, - { - "armv5e", - arch_opttab_armv5e, - { - ISA_ARMv5e, - isa_nobit - }, - "5E", BASE_ARCH_5E, - TARGET_CPU_arm1026ejs, - }, - { - "armv5te", - arch_opttab_armv5te, - { - ISA_ARMv5te, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_arm1026ejs, - }, - { - "armv5tej", - arch_opttab_armv5tej, - { - ISA_ARMv5tej, - isa_nobit - }, - "5TEJ", BASE_ARCH_5TEJ, - TARGET_CPU_arm1026ejs, - }, - { - "armv6", - arch_opttab_armv6, - { - ISA_ARMv6, - isa_nobit - }, - "6", BASE_ARCH_6, - TARGET_CPU_arm1136js, - }, - { - "armv6j", - arch_opttab_armv6j, - { - ISA_ARMv6j, - isa_nobit - }, - "6J", BASE_ARCH_6J, - TARGET_CPU_arm1136js, - }, - { - "armv6k", - arch_opttab_armv6k, - { - ISA_ARMv6k, - isa_nobit - }, - "6K", BASE_ARCH_6K, - TARGET_CPU_mpcore, - }, - { - "armv6z", - arch_opttab_armv6z, - { - ISA_ARMv6z, - isa_nobit - }, - "6Z", BASE_ARCH_6Z, - TARGET_CPU_arm1176jzs, - }, - { - "armv6kz", - arch_opttab_armv6kz, - { - ISA_ARMv6kz, - isa_nobit - }, - "6KZ", BASE_ARCH_6KZ, - TARGET_CPU_arm1176jzs, - }, - { - "armv6zk", - arch_opttab_armv6zk, - { - ISA_ARMv6kz, - isa_nobit - }, - "6KZ", BASE_ARCH_6KZ, - TARGET_CPU_arm1176jzs, - }, - { - "armv6t2", - arch_opttab_armv6t2, - { - ISA_ARMv6t2, - isa_nobit - }, - "6T2", BASE_ARCH_6T2, - TARGET_CPU_arm1156t2s, - }, - { - "armv6-m", - NULL, - { - ISA_ARMv6m, - isa_nobit - }, - "6M", BASE_ARCH_6M, - TARGET_CPU_cortexm1, - }, - { - "armv6s-m", - NULL, - { - ISA_ARMv6m, - isa_nobit - }, - "6M", BASE_ARCH_6M, - TARGET_CPU_cortexm1, - }, - { - "armv7", - arch_opttab_armv7, - { - ISA_ARMv7, - isa_nobit - }, - "7", BASE_ARCH_7, - TARGET_CPU_cortexa8, - }, - { - "armv7-a", - arch_opttab_armv7_a, - { - ISA_ARMv7a, - isa_nobit - }, - "7A", BASE_ARCH_7A, - TARGET_CPU_cortexa8, - }, - { - "armv7ve", - arch_opttab_armv7ve, - { - ISA_ARMv7ve, - isa_nobit - }, - "7A", BASE_ARCH_7A, - TARGET_CPU_cortexa8, - }, - { - "armv7-r", - arch_opttab_armv7_r, - { - ISA_ARMv7r, - isa_nobit - }, - "7R", BASE_ARCH_7R, - TARGET_CPU_cortexr4, - }, - { - "armv7-m", - NULL, - { - ISA_ARMv7m, - isa_nobit - }, - "7M", BASE_ARCH_7M, - TARGET_CPU_cortexm3, - }, - { - "armv7e-m", - arch_opttab_armv7e_m, - { - ISA_ARMv7em, - isa_nobit - }, - "7EM", BASE_ARCH_7EM, - TARGET_CPU_cortexm4, - }, - { - "armv8-a", - arch_opttab_armv8_a, - { - ISA_ARMv8a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8.1-a", - arch_opttab_armv8_1_a, - { - ISA_ARMv8_1a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8.2-a", - arch_opttab_armv8_2_a, - { - ISA_ARMv8_2a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8-m.base", - NULL, - { - ISA_ARMv8m_base, - isa_nobit - }, - "8M_BASE", BASE_ARCH_8M_BASE, - TARGET_CPU_cortexm23, - }, - { - "armv8-m.main", - arch_opttab_armv8_m_main, - { - ISA_ARMv8m_main, - isa_nobit - }, - "8M_MAIN", BASE_ARCH_8M_MAIN, - TARGET_CPU_cortexm7, - }, - { - "iwmmxt", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_iwmmxt, - }, - { - "iwmmxt2", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_iwmmxt2, - }, - {{NULL, NULL, {isa_nobit}}, - NULL, BASE_ARCH_0, TARGET_CPU_arm_none} -}; - -const arm_fpu_desc all_fpus[] = -{ - { - "vfp", - { - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv2", - { - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv3", - { - ISA_VFPv3,ISA_FP_D32, - isa_nobit - } - }, - { - "vfpv3-fp16", - { - ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv3-d16", - { - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv3-d16-fp16", - { - ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv3xd", - { - ISA_VFPv3, - isa_nobit - } - }, - { - "vfpv3xd-fp16", - { - ISA_VFPv3,isa_bit_fp16conv, - isa_nobit - } - }, - { - "neon", - { - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - { - "neon-vfpv3", - { - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - { - "neon-fp16", - { - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv4", - { - ISA_VFPv4,ISA_FP_D32, - isa_nobit - } - }, - { - "neon-vfpv4", - { - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - { - "vfpv4-d16", - { - ISA_VFPv4,ISA_FP_DBL, - isa_nobit - } - }, - { - "fpv4-sp-d16", - { - ISA_VFPv4, - isa_nobit - } - }, - { - "fpv5-sp-d16", - { - ISA_FPv5, - isa_nobit - } - }, - { - "fpv5-d16", - { - ISA_FPv5,ISA_FP_DBL, - isa_nobit - } - }, - { - "fp-armv8", - { - ISA_FP_ARMv8,ISA_FP_D32, - isa_nobit - } - }, - { - "neon-fp-armv8", - { - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - { - "crypto-neon-fp-armv8", - { - ISA_FP_ARMv8,ISA_CRYPTO, - isa_nobit - } - }, - { - "vfp3", - { - ISA_VFPv3,ISA_FP_D32, - isa_nobit - } - }, -}; diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h deleted file mode 100644 index d42021d15c7..00000000000 --- a/gcc/config/arm/arm-cpu-data.h +++ /dev/null @@ -1,566 +0,0 @@ -/* -*- buffer-read-only: t -*- - Generated automatically by parsecpu.awk from arm-cpus.in. - Do not edit. - - Copyright (C) 2011-2017 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public - License along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -static const cpu_tune all_tunes[] = -{ - { /* arm2. */ - TARGET_CPU_arm2, - (TF_CO_PROC | TF_NO_MODE32), - &arm_slowmul_tune - }, - { /* arm250. */ - TARGET_CPU_arm250, - (TF_CO_PROC | TF_NO_MODE32), - &arm_slowmul_tune - }, - { /* arm3. */ - TARGET_CPU_arm3, - (TF_CO_PROC | TF_NO_MODE32), - &arm_slowmul_tune - }, - { /* arm6. */ - TARGET_CPU_arm6, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm60. */ - TARGET_CPU_arm60, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm600. */ - TARGET_CPU_arm600, - (TF_CO_PROC | TF_WBUF), - &arm_slowmul_tune - }, - { /* arm610. */ - TARGET_CPU_arm610, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm620. */ - TARGET_CPU_arm620, - (TF_CO_PROC | TF_WBUF), - &arm_slowmul_tune - }, - { /* arm7. */ - TARGET_CPU_arm7, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm7d. */ - TARGET_CPU_arm7d, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm7di. */ - TARGET_CPU_arm7di, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm70. */ - TARGET_CPU_arm70, - (TF_CO_PROC), - &arm_slowmul_tune - }, - { /* arm700. */ - TARGET_CPU_arm700, - (TF_CO_PROC | TF_WBUF), - &arm_slowmul_tune - }, - { /* arm700i. */ - TARGET_CPU_arm700i, - (TF_CO_PROC | TF_WBUF), - &arm_slowmul_tune - }, - { /* arm710. */ - TARGET_CPU_arm710, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm720. */ - TARGET_CPU_arm720, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm710c. */ - TARGET_CPU_arm710c, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm7100. */ - TARGET_CPU_arm7100, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm7500. */ - TARGET_CPU_arm7500, - (TF_WBUF), - &arm_slowmul_tune - }, - { /* arm7500fe. */ - TARGET_CPU_arm7500fe, - (TF_CO_PROC | TF_WBUF), - &arm_slowmul_tune - }, - { /* arm7m. */ - TARGET_CPU_arm7m, - (TF_CO_PROC), - &arm_fastmul_tune - }, - { /* arm7dm. */ - TARGET_CPU_arm7dm, - (TF_CO_PROC), - &arm_fastmul_tune - }, - { /* arm7dmi. */ - TARGET_CPU_arm7dmi, - (TF_CO_PROC), - &arm_fastmul_tune - }, - { /* arm8. */ - TARGET_CPU_arm8, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm810. */ - TARGET_CPU_arm810, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* strongarm. */ - TARGET_CPU_strongarm, - (TF_LDSCHED | TF_STRONG), - &arm_strongarm_tune - }, - { /* strongarm110. */ - TARGET_CPU_strongarm110, - (TF_LDSCHED | TF_STRONG), - &arm_strongarm_tune - }, - { /* strongarm1100. */ - TARGET_CPU_strongarm1100, - (TF_LDSCHED | TF_STRONG), - &arm_strongarm_tune - }, - { /* strongarm1110. */ - TARGET_CPU_strongarm1110, - (TF_LDSCHED | TF_STRONG), - &arm_strongarm_tune - }, - { /* fa526. */ - TARGET_CPU_fa526, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* fa626. */ - TARGET_CPU_fa626, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm7tdmi. */ - TARGET_CPU_arm7tdmi, - (TF_CO_PROC), - &arm_fastmul_tune - }, - { /* arm7tdmi-s. */ - TARGET_CPU_arm7tdmis, - (TF_CO_PROC), - &arm_fastmul_tune - }, - { /* arm710t. */ - TARGET_CPU_arm710t, - (TF_WBUF), - &arm_fastmul_tune - }, - { /* arm720t. */ - TARGET_CPU_arm720t, - (TF_WBUF), - &arm_fastmul_tune - }, - { /* arm740t. */ - TARGET_CPU_arm740t, - (TF_WBUF), - &arm_fastmul_tune - }, - { /* arm9. */ - TARGET_CPU_arm9, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm9tdmi. */ - TARGET_CPU_arm9tdmi, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm920. */ - TARGET_CPU_arm920, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm920t. */ - TARGET_CPU_arm920t, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm922t. */ - TARGET_CPU_arm922t, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm940t. */ - TARGET_CPU_arm940t, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* ep9312. */ - TARGET_CPU_ep9312, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm10tdmi. */ - TARGET_CPU_arm10tdmi, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm1020t. */ - TARGET_CPU_arm1020t, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm9e. */ - TARGET_CPU_arm9e, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm946e-s. */ - TARGET_CPU_arm946es, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm966e-s. */ - TARGET_CPU_arm966es, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm968e-s. */ - TARGET_CPU_arm968es, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm10e. */ - TARGET_CPU_arm10e, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm1020e. */ - TARGET_CPU_arm1020e, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* arm1022e. */ - TARGET_CPU_arm1022e, - (TF_LDSCHED), - &arm_fastmul_tune - }, - { /* xscale. */ - TARGET_CPU_xscale, - (TF_LDSCHED | TF_XSCALE), - &arm_xscale_tune - }, - { /* iwmmxt. */ - TARGET_CPU_iwmmxt, - (TF_LDSCHED | TF_XSCALE), - &arm_xscale_tune - }, - { /* iwmmxt2. */ - TARGET_CPU_iwmmxt2, - (TF_LDSCHED | TF_XSCALE), - &arm_xscale_tune - }, - { /* fa606te. */ - TARGET_CPU_fa606te, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* fa626te. */ - TARGET_CPU_fa626te, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* fmp626. */ - TARGET_CPU_fmp626, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* fa726te. */ - TARGET_CPU_fa726te, - (TF_LDSCHED), - &arm_fa726te_tune - }, - { /* arm926ej-s. */ - TARGET_CPU_arm926ejs, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1026ej-s. */ - TARGET_CPU_arm1026ejs, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1136j-s. */ - TARGET_CPU_arm1136js, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1136jf-s. */ - TARGET_CPU_arm1136jfs, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1176jz-s. */ - TARGET_CPU_arm1176jzs, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1176jzf-s. */ - TARGET_CPU_arm1176jzfs, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* mpcorenovfp. */ - TARGET_CPU_mpcorenovfp, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* mpcore. */ - TARGET_CPU_mpcore, - (TF_LDSCHED), - &arm_9e_tune - }, - { /* arm1156t2-s. */ - TARGET_CPU_arm1156t2s, - (TF_LDSCHED), - &arm_v6t2_tune - }, - { /* arm1156t2f-s. */ - TARGET_CPU_arm1156t2fs, - (TF_LDSCHED), - &arm_v6t2_tune - }, - { /* cortex-m1. */ - TARGET_CPU_cortexm1, - (TF_LDSCHED), - &arm_v6m_tune - }, - { /* cortex-m0. */ - TARGET_CPU_cortexm0, - (TF_LDSCHED), - &arm_v6m_tune - }, - { /* cortex-m0plus. */ - TARGET_CPU_cortexm0plus, - (TF_LDSCHED), - &arm_v6m_tune - }, - { /* cortex-m1.small-multiply. */ - TARGET_CPU_cortexm1, - (TF_LDSCHED | TF_SMALLMUL), - &arm_v6m_tune - }, - { /* cortex-m0.small-multiply. */ - TARGET_CPU_cortexm0, - (TF_LDSCHED | TF_SMALLMUL), - &arm_v6m_tune - }, - { /* cortex-m0plus.small-multiply. */ - TARGET_CPU_cortexm0plus, - (TF_LDSCHED | TF_SMALLMUL), - &arm_v6m_tune - }, - { /* generic-armv7-a. */ - TARGET_CPU_genericv7a, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-a5. */ - TARGET_CPU_cortexa5, - (TF_LDSCHED), - &arm_cortex_a5_tune - }, - { /* cortex-a7. */ - TARGET_CPU_cortexa7, - (TF_LDSCHED), - &arm_cortex_a7_tune - }, - { /* cortex-a8. */ - TARGET_CPU_cortexa8, - (TF_LDSCHED), - &arm_cortex_a8_tune - }, - { /* cortex-a9. */ - TARGET_CPU_cortexa9, - (TF_LDSCHED), - &arm_cortex_a9_tune - }, - { /* cortex-a12. */ - TARGET_CPU_cortexa17, - (TF_LDSCHED), - &arm_cortex_a12_tune - }, - { /* cortex-a15. */ - TARGET_CPU_cortexa15, - (TF_LDSCHED), - &arm_cortex_a15_tune - }, - { /* cortex-a17. */ - TARGET_CPU_cortexa17, - (TF_LDSCHED), - &arm_cortex_a12_tune - }, - { /* cortex-r4. */ - TARGET_CPU_cortexr4, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-r4f. */ - TARGET_CPU_cortexr4f, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-r5. */ - TARGET_CPU_cortexr5, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-r7. */ - TARGET_CPU_cortexr7, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-r8. */ - TARGET_CPU_cortexr7, - (TF_LDSCHED), - &arm_cortex_tune - }, - { /* cortex-m7. */ - TARGET_CPU_cortexm7, - (TF_LDSCHED), - &arm_cortex_m7_tune - }, - { /* cortex-m4. */ - TARGET_CPU_cortexm4, - (TF_LDSCHED), - &arm_v7m_tune - }, - { /* cortex-m3. */ - TARGET_CPU_cortexm3, - (TF_LDSCHED), - &arm_v7m_tune - }, - { /* marvell-pj4. */ - TARGET_CPU_marvell_pj4, - (TF_LDSCHED), - &arm_marvell_pj4_tune - }, - { /* cortex-a15.cortex-a7. */ - TARGET_CPU_cortexa7, - (TF_LDSCHED), - &arm_cortex_a15_tune - }, - { /* cortex-a17.cortex-a7. */ - TARGET_CPU_cortexa7, - (TF_LDSCHED), - &arm_cortex_a12_tune - }, - { /* cortex-a32. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a35_tune - }, - { /* cortex-a35. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a35_tune - }, - { /* cortex-a53. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a53_tune - }, - { /* cortex-a57. */ - TARGET_CPU_cortexa57, - (TF_LDSCHED), - &arm_cortex_a57_tune - }, - { /* cortex-a72. */ - TARGET_CPU_cortexa57, - (TF_LDSCHED), - &arm_cortex_a57_tune - }, - { /* cortex-a73. */ - TARGET_CPU_cortexa57, - (TF_LDSCHED), - &arm_cortex_a73_tune - }, - { /* exynos-m1. */ - TARGET_CPU_exynosm1, - (TF_LDSCHED), - &arm_exynosm1_tune - }, - { /* xgene1. */ - TARGET_CPU_xgene1, - (TF_LDSCHED), - &arm_xgene1_tune - }, - { /* cortex-a57.cortex-a53. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a57_tune - }, - { /* cortex-a72.cortex-a53. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a57_tune - }, - { /* cortex-a73.cortex-a35. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a73_tune - }, - { /* cortex-a73.cortex-a53. */ - TARGET_CPU_cortexa53, - (TF_LDSCHED), - &arm_cortex_a73_tune - }, - { /* cortex-m23. */ - TARGET_CPU_cortexm23, - (TF_LDSCHED), - &arm_v6m_tune - }, - { /* cortex-m33. */ - TARGET_CPU_cortexm33, - (TF_LDSCHED), - &arm_v7m_tune - }, - {TARGET_CPU_arm_none, 0, NULL} -}; diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h deleted file mode 100644 index e27634c6dd9..00000000000 --- a/gcc/config/arm/arm-cpu.h +++ /dev/null @@ -1,198 +0,0 @@ -/* -*- buffer-read-only: t -*- - Generated automatically by parsecpu.awk from arm-cpus.in. - Do not edit. - - Copyright (C) 2011-2017 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public - License along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -enum processor_type -{ - TARGET_CPU_arm2, - TARGET_CPU_arm250, - TARGET_CPU_arm3, - TARGET_CPU_arm6, - TARGET_CPU_arm60, - TARGET_CPU_arm600, - TARGET_CPU_arm610, - TARGET_CPU_arm620, - TARGET_CPU_arm7, - TARGET_CPU_arm7d, - TARGET_CPU_arm7di, - TARGET_CPU_arm70, - TARGET_CPU_arm700, - TARGET_CPU_arm700i, - TARGET_CPU_arm710, - TARGET_CPU_arm720, - TARGET_CPU_arm710c, - TARGET_CPU_arm7100, - TARGET_CPU_arm7500, - TARGET_CPU_arm7500fe, - TARGET_CPU_arm7m, - TARGET_CPU_arm7dm, - TARGET_CPU_arm7dmi, - TARGET_CPU_arm8, - TARGET_CPU_arm810, - TARGET_CPU_strongarm, - TARGET_CPU_strongarm110, - TARGET_CPU_strongarm1100, - TARGET_CPU_strongarm1110, - TARGET_CPU_fa526, - TARGET_CPU_fa626, - TARGET_CPU_arm7tdmi, - TARGET_CPU_arm7tdmis, - TARGET_CPU_arm710t, - TARGET_CPU_arm720t, - TARGET_CPU_arm740t, - TARGET_CPU_arm9, - TARGET_CPU_arm9tdmi, - TARGET_CPU_arm920, - TARGET_CPU_arm920t, - TARGET_CPU_arm922t, - TARGET_CPU_arm940t, - TARGET_CPU_ep9312, - TARGET_CPU_arm10tdmi, - TARGET_CPU_arm1020t, - TARGET_CPU_arm9e, - TARGET_CPU_arm946es, - TARGET_CPU_arm966es, - TARGET_CPU_arm968es, - TARGET_CPU_arm10e, - TARGET_CPU_arm1020e, - TARGET_CPU_arm1022e, - TARGET_CPU_xscale, - TARGET_CPU_iwmmxt, - TARGET_CPU_iwmmxt2, - TARGET_CPU_fa606te, - TARGET_CPU_fa626te, - TARGET_CPU_fmp626, - TARGET_CPU_fa726te, - TARGET_CPU_arm926ejs, - TARGET_CPU_arm1026ejs, - TARGET_CPU_arm1136js, - TARGET_CPU_arm1136jfs, - TARGET_CPU_arm1176jzs, - TARGET_CPU_arm1176jzfs, - TARGET_CPU_mpcorenovfp, - TARGET_CPU_mpcore, - TARGET_CPU_arm1156t2s, - TARGET_CPU_arm1156t2fs, - TARGET_CPU_cortexm1, - TARGET_CPU_cortexm0, - TARGET_CPU_cortexm0plus, - TARGET_CPU_cortexm1smallmultiply, - TARGET_CPU_cortexm0smallmultiply, - TARGET_CPU_cortexm0plussmallmultiply, - TARGET_CPU_genericv7a, - TARGET_CPU_cortexa5, - TARGET_CPU_cortexa7, - TARGET_CPU_cortexa8, - TARGET_CPU_cortexa9, - TARGET_CPU_cortexa12, - TARGET_CPU_cortexa15, - TARGET_CPU_cortexa17, - TARGET_CPU_cortexr4, - TARGET_CPU_cortexr4f, - TARGET_CPU_cortexr5, - TARGET_CPU_cortexr7, - TARGET_CPU_cortexr8, - TARGET_CPU_cortexm7, - TARGET_CPU_cortexm4, - TARGET_CPU_cortexm3, - TARGET_CPU_marvell_pj4, - TARGET_CPU_cortexa15cortexa7, - TARGET_CPU_cortexa17cortexa7, - TARGET_CPU_cortexa32, - TARGET_CPU_cortexa35, - TARGET_CPU_cortexa53, - TARGET_CPU_cortexa57, - TARGET_CPU_cortexa72, - TARGET_CPU_cortexa73, - TARGET_CPU_exynosm1, - TARGET_CPU_xgene1, - TARGET_CPU_cortexa57cortexa53, - TARGET_CPU_cortexa72cortexa53, - TARGET_CPU_cortexa73cortexa35, - TARGET_CPU_cortexa73cortexa53, - TARGET_CPU_cortexm23, - TARGET_CPU_cortexm33, - TARGET_CPU_arm_none -}; - -enum arch_type -{ - TARGET_ARCH_armv2, - TARGET_ARCH_armv2a, - TARGET_ARCH_armv3, - TARGET_ARCH_armv3m, - TARGET_ARCH_armv4, - TARGET_ARCH_armv4t, - TARGET_ARCH_armv5, - TARGET_ARCH_armv5t, - TARGET_ARCH_armv5e, - TARGET_ARCH_armv5te, - TARGET_ARCH_armv5tej, - TARGET_ARCH_armv6, - TARGET_ARCH_armv6j, - TARGET_ARCH_armv6k, - TARGET_ARCH_armv6z, - TARGET_ARCH_armv6kz, - TARGET_ARCH_armv6zk, - TARGET_ARCH_armv6t2, - TARGET_ARCH_armv6_m, - TARGET_ARCH_armv6s_m, - TARGET_ARCH_armv7, - TARGET_ARCH_armv7_a, - TARGET_ARCH_armv7ve, - TARGET_ARCH_armv7_r, - TARGET_ARCH_armv7_m, - TARGET_ARCH_armv7e_m, - TARGET_ARCH_armv8_a, - TARGET_ARCH_armv8_1_a, - TARGET_ARCH_armv8_2_a, - TARGET_ARCH_armv8_m_base, - TARGET_ARCH_armv8_m_main, - TARGET_ARCH_iwmmxt, - TARGET_ARCH_iwmmxt2, - TARGET_ARCH_arm_none -}; - -enum fpu_type -{ - TARGET_FPU_vfp, - TARGET_FPU_vfpv2, - TARGET_FPU_vfpv3, - TARGET_FPU_vfpv3_fp16, - TARGET_FPU_vfpv3_d16, - TARGET_FPU_vfpv3_d16_fp16, - TARGET_FPU_vfpv3xd, - TARGET_FPU_vfpv3xd_fp16, - TARGET_FPU_neon, - TARGET_FPU_neon_vfpv3, - TARGET_FPU_neon_fp16, - TARGET_FPU_vfpv4, - TARGET_FPU_neon_vfpv4, - TARGET_FPU_vfpv4_d16, - TARGET_FPU_fpv4_sp_d16, - TARGET_FPU_fpv5_sp_d16, - TARGET_FPU_fpv5_d16, - TARGET_FPU_fp_armv8, - TARGET_FPU_neon_fp_armv8, - TARGET_FPU_crypto_neon_fp_armv8, - TARGET_FPU_vfp3, - TARGET_FPU_auto -}; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 43f4ebcc5f7..d009a9e18ac 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -46,6 +46,7 @@ # tune for <cpu> # [tune flags <list>] # base <name> +# [profile <A|R|M>] # isa <isa-flags-list> # end arch <name> # @@ -211,12 +212,14 @@ end arch armv6t2 begin arch armv6-m tune for cortex-m1 base 6M + profile M isa ARMv6m end arch armv6-m begin arch armv6s-m tune for cortex-m1 base 6M + profile M isa ARMv6m end arch armv6s-m @@ -235,6 +238,7 @@ begin arch armv7-a tune for cortex-a8 tune flags CO_PROC base 7A + profile A isa ARMv7a # fp => VFPv3-d16, simd => neon-vfpv3 option fp add VFPv3 FP_DBL @@ -257,6 +261,7 @@ begin arch armv7ve tune for cortex-a8 tune flags CO_PROC base 7A + profile A isa ARMv7ve # fp => VFPv4-d16, simd => neon-vfpv4 option vfpv3-d16 add VFPv3 FP_DBL @@ -279,6 +284,7 @@ begin arch armv7-r tune for cortex-r4 tune flags CO_PROC base 7R + profile R isa ARMv7r # ARMv7-r uses VFPv3-d16 option fp.sp add VFPv3 @@ -294,6 +300,7 @@ begin arch armv7-m tune for cortex-m3 tune flags CO_PROC base 7M + profile M isa ARMv7m # In theory FP is permitted in v7-m, but in practice no implementations exist. # leave it out for now. @@ -303,6 +310,7 @@ begin arch armv7e-m tune for cortex-m4 tune flags CO_PROC base 7EM + profile M isa ARMv7em # fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 option fp add VFPv4 @@ -317,6 +325,7 @@ begin arch armv8-a tune for cortex-a53 tune flags CO_PROC base 8A + profile A isa ARMv8a option crc add bit_crc32 option simd add FP_ARMv8 NEON @@ -329,6 +338,7 @@ begin arch armv8.1-a tune for cortex-a53 tune flags CO_PROC base 8A + profile A isa ARMv8_1a option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 CRYPTO @@ -340,6 +350,7 @@ begin arch armv8.2-a tune for cortex-a53 tune flags CO_PROC base 8A + profile A isa ARMv8_2a option simd add FP_ARMv8 NEON option fp16 add bit_fp16 FP_ARMv8 NEON @@ -351,6 +362,7 @@ end arch armv8.2-a begin arch armv8-m.base tune for cortex-m23 base 8M_BASE + profile M isa ARMv8m_base end arch armv8-m.base @@ -358,6 +370,7 @@ begin arch armv8-m.main tune for cortex-m7 tune flags CO_PROC base 8M_MAIN + profile M isa ARMv8m_main option dsp add bit_ARMv7em # fp => FPv5-sp-d16; fp.dp => FPv5-d16 @@ -367,6 +380,22 @@ begin arch armv8-m.main option nodsp remove bit_ARMv7em end arch armv8-m.main +begin arch armv8-r + tune for cortex-r52 + tune flags CO_PROC + base 8R + profile R + isa ARMv8r + option crc add bit_crc32 +# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision +# note: no fp option for fp-armv8 (d16) + double precision at the moment + option fp.sp add FPv5 + option simd add FP_ARMv8 NEON + option crypto add FP_ARMv8 CRYPTO + option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP +end arch armv8-r + begin arch iwmmxt tune for iwmmxt tune flags LDSCHED STRONG XSCALE @@ -1193,7 +1222,6 @@ begin cpu xgene1 costs xgene1 end cpu xgene1 - # V8 A-profile big.LITTLE implementations begin cpu cortex-a57.cortex-a53 cname cortexa57cortexa53 @@ -1236,6 +1264,40 @@ begin cpu cortex-a73.cortex-a53 end cpu cortex-a73.cortex-a53 +# ARMv8.2 A-profile Architecture Processors +begin cpu cortex-a55 + cname cortexa55 + tune for cortex-a53 + tune flags LDSCHED + architecture armv8.2-a+fp16 + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + costs cortex_a53 +end cpu cortex-a55 + +begin cpu cortex-a75 + cname cortexa75 + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.2-a+fp16 + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + costs cortex_a73 +end cpu cortex-a75 + + +# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations +begin cpu cortex-a75.cortex-a55 + cname cortexa75cortexa55 + tune for cortex-a53 + tune flags LDSCHED + architecture armv8.2-a+fp16 + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + costs cortex_a73 +end cpu cortex-a75.cortex-a55 + # V8 M-profile implementations. begin cpu cortex-m23 cname cortexm23 @@ -1253,6 +1315,16 @@ begin cpu cortex-m33 costs v7m end cpu cortex-m33 +# V8 R-profile implementations. +begin cpu cortex-r52 + cname cortexr52 + tune flags LDSCHED + architecture armv8-r+crc+simd + fpu neon-fp-armv8 + option nofp.dp remove FP_DBL ALL_SIMD + costs cortex +end cpu cortex-r52 + # FPU entries # format: # begin fpu <name> @@ -1328,7 +1400,7 @@ begin fpu fpv5-d16 end fpu fpv5-d16 begin fpu fp-armv8 - isa FP_ARMv8 FP_D32 + isa FP_ARMv8 end fpu fp-armv8 begin fpu neon-fp-armv8 diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 4b5a0f658e6..dbd29eaa52f 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -40,7 +40,8 @@ enum isa_feature isa_bit_ARMv6, /* Architecture rel 6. */ isa_bit_ARMv6k, /* Architecture rel 6k. */ isa_bit_thumb2, /* Thumb-2. */ - isa_bit_notm, /* Instructions that are not present in 'M' profile. */ + isa_bit_notm, /* Instructions not present in 'M' profile. */ + isa_bit_be8, /* Architecture uses be8 mode in big-endian. */ isa_bit_tdiv, /* Thumb division instructions. */ isa_bit_ARMv7em, /* Architecture rel 7e-m. */ isa_bit_ARMv7, /* Architecture rel 7. */ @@ -59,7 +60,6 @@ enum isa_feature isa_bit_VFPv4, /* Vector floating point v4. */ isa_bit_FPv5, /* Floating point v5. */ isa_bit_lpae, /* ARMv7-A LPAE. */ - isa_bit_FP_ARMv8, /* ARMv8 floating-point extension. */ isa_bit_neon, /* Advanced SIMD instructions. */ isa_bit_fp16conv, /* Conversions to/from fp16 (VFPv3 extension). */ isa_bit_fp_dbl, /* Double precision operations supported. */ @@ -101,7 +101,7 @@ enum isa_feature #define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e #define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb #define ISA_ARMv5tej ISA_ARMv5te -#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6 +#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8 #define ISA_ARMv6j ISA_ARMv6 #define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k #define ISA_ARMv6z ISA_ARMv6 @@ -126,6 +126,7 @@ enum isa_feature #define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +#define ISA_ARMv8r ISA_ARMv8a /* List of all cryptographic extensions to stripout if crypto is disabled. Currently, that's trivial, but we define it anyway for @@ -141,7 +142,7 @@ enum isa_feature default. isa_bit_fp16 is deliberately missing from this list. */ #define ISA_ALL_FPU_INTERNAL \ isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5, \ - isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD + isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD /* Similarly, but including fp16 and other extensions that aren't part of -mfpu support. */ @@ -152,10 +153,10 @@ enum isa_feature #define ISA_VFPv3 ISA_VFPv2, isa_bit_VFPv3 #define ISA_VFPv4 ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv #define ISA_FPv5 ISA_VFPv4, isa_bit_FPv5 -#define ISA_FP_ARMv8 ISA_FPv5, isa_bit_FP_ARMv8 #define ISA_FP_DBL isa_bit_fp_dbl #define ISA_FP_D32 ISA_FP_DBL, isa_bit_fp_d32 +#define ISA_FP_ARMv8 ISA_FPv5, ISA_FP_D32 #define ISA_NEON ISA_FP_D32, isa_bit_neon #define ISA_CRYPTO ISA_NEON, isa_bit_crypto diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 25210e2375a..25fb10c32d1 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -47,7 +47,7 @@ extern unsigned int arm_dbx_register_number (unsigned int); extern void arm_output_fn_unwind (FILE *, bool); extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget - ATTRIBUTE_UNUSED, enum machine_mode mode + ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED); extern tree arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED); @@ -464,6 +464,8 @@ struct arm_build_target const char *arch_pp_name; /* The base architecture value. */ enum base_architecture base_arch; + /* The profile letter for the architecture, upper case by convention. */ + char profile; /* Bitmap encapsulating the isa_bits for the target environment. */ sbitmap isa; /* Flags used for tuning. Long term, these move into tune_params. */ @@ -507,6 +509,8 @@ struct arch_option const char *arch; /* Base architecture, from which this specific architecture is derived. */ enum base_architecture base_arch; + /* The profile letter for the architecture, upper case by convention. */ + const char profile; /* Default tune target (in the absence of any more specific data). */ enum processor_type tune_id; }; diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 0f50c64f4b1..4e508b1555a 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -343,11 +343,23 @@ EnumValue Enum(processor_type) String(cortex-a73.cortex-a53) Value( TARGET_CPU_cortexa73cortexa53) EnumValue +Enum(processor_type) String(cortex-a55) Value( TARGET_CPU_cortexa55) + +EnumValue +Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75) + +EnumValue +Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55) + +EnumValue Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) +EnumValue +Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): @@ -446,10 +458,13 @@ EnumValue Enum(arm_arch) String(armv8-m.main) Value(30) EnumValue -Enum(arm_arch) String(iwmmxt) Value(31) +Enum(arm_arch) String(armv8-r) Value(31) + +EnumValue +Enum(arm_arch) String(iwmmxt) Value(32) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(32) +Enum(arm_arch) String(iwmmxt2) Value(33) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 6252d42d4d8..1b3f7a94cc7 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -56,5 +56,7 @@ cortexa53,cortexa57,cortexa72, cortexa73,exynosm1,xgene1, cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, - cortexa73cortexa53,cortexm23,cortexm33" + cortexa73cortexa53,cortexa55,cortexa75, + cortexa75cortexa55,cortexm23,cortexm33, + cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index f3b2715185b..25677d19e20 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -110,6 +110,7 @@ static void arm_print_operand_address (FILE *, machine_mode, rtx); static bool arm_print_operand_punct_valid_p (unsigned char code); static const char *fp_const_from_val (REAL_VALUE_TYPE *); static arm_cc get_arm_condition_code (rtx); +static bool arm_fixed_condition_code_regs (unsigned int *, unsigned int *); static const char *output_multi_immediate (rtx *, const char *, const char *, int, HOST_WIDE_INT); static const char *shift_op (rtx, HOST_WIDE_INT *); @@ -775,6 +776,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2 +#undef TARGET_FIXED_CONDITION_CODE_REGS +#define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs + /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; @@ -3273,6 +3277,7 @@ arm_configure_build_target (struct arm_build_target *target, /* Finish initializing the target structure. */ target->arch_pp_name = arm_selected_arch->arch; target->base_arch = arm_selected_arch->base_arch; + target->profile = arm_selected_arch->profile; target->tune_flags = tune_data->tune_flags; target->tune = tune_data->tune; @@ -3484,6 +3489,8 @@ arm_option_override (void) } else { + warning (0, "option %<-mstructure-size-boundary%> is deprecated"); + if (arm_structure_size_boundary != 8 && arm_structure_size_boundary != 32 && !(ARM_DOUBLEWORD_ALIGN && arm_structure_size_boundary == 64)) @@ -10750,7 +10757,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, { if (speed_p) *cost += extra_cost->fp[mode == DFmode].widen; - if (!TARGET_FPU_ARMV8 + if (!TARGET_VFP5 && GET_MODE (XEXP (x, 0)) == HFmode) { /* Pre v8, widening HF->DF is a two-step process, first @@ -10844,7 +10851,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, return true; } else if (GET_MODE_CLASS (mode) == MODE_FLOAT - && TARGET_FPU_ARMV8) + && TARGET_VFP5) { if (speed_p) *cost += extra_cost->fp[mode == DFmode].roundint; @@ -13614,10 +13621,7 @@ gen_ldm_seq (rtx *operands, int nops, bool sort_regs) emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); offset = 0; if (!TARGET_THUMB1) - { - base_reg = regs[0]; - base_reg_rtx = newbase; - } + base_reg_rtx = newbase; } for (i = 0; i < nops; i++) @@ -14141,7 +14145,6 @@ arm_gen_movmemqi (rtx *operands) { HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; HOST_WIDE_INT srcoffset, dstoffset; - int i; rtx src, dst, srcbase, dstbase; rtx part_bytes_reg = NULL; rtx mem; @@ -14171,7 +14174,7 @@ arm_gen_movmemqi (rtx *operands) if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); - for (i = 0; in_words_to_go >= 2; i+=4) + while (in_words_to_go >= 2) { if (in_words_to_go > 4) emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, @@ -21725,8 +21728,8 @@ arm_expand_prologue (void) will prevent the scheduler from moving stores to the frame before the stack adjustment. */ if (frame_pointer_needed) - insn = emit_insn (gen_stack_tie (stack_pointer_rtx, - hard_frame_pointer_rtx)); + emit_insn (gen_stack_tie (stack_pointer_rtx, + hard_frame_pointer_rtx)); } @@ -22931,6 +22934,20 @@ get_arm_condition_code (rtx comparison) return code; } +/* Implement TARGET_FIXED_CONDITION_CODE_REGS. We only have condition + code registers when not targetting Thumb1. The VFP condition register + only exists when generating hard-float code. */ +static bool +arm_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) +{ + if (!TARGET_32BIT) + return false; + + *p1 = CC_REGNUM; + *p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM; + return true; +} + /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed instructions. */ void @@ -23811,7 +23828,6 @@ thumb_pop (FILE *f, unsigned long mask) { int regno; int lo_mask = mask & 0xFF; - int pushed_words = 0; gcc_assert (mask); @@ -23834,8 +23850,6 @@ thumb_pop (FILE *f, unsigned long mask) if ((lo_mask & ~1) != 0) fprintf (f, ", "); - - pushed_words++; } } @@ -24105,9 +24119,6 @@ thumb_exit (FILE *f, int reg_containing_return_addr) move_to = number_of_first_bit_set (regs_to_pop); asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); - - regs_to_pop &= ~(1 << move_to); - --pops_needed; } @@ -28259,10 +28270,8 @@ arm_emit_store_exclusive (machine_mode mode, rtx bval, rtx rval, static void emit_unlikely_jump (rtx insn) { - int very_unlikely = REG_BR_PROB_BASE / 100 - 1; - rtx_insn *jump = emit_jump_insn (insn); - add_int_reg_note (jump, REG_BR_PROB, very_unlikely); + add_reg_br_prob_note (jump, profile_probability::very_unlikely ()); } /* Expand a compare and swap pattern. */ @@ -31215,12 +31224,15 @@ namespace selftest { inconsistencies in the option extensions at present (extensions that duplicate others but aren't marked as aliases). Furthermore, for correct canonicalization later options must never be a subset - of an earlier option. */ + of an earlier option. Any extension should also only specify other + feature bits and never an architecture bit. The architecture is inferred + from the declaration of the extension. */ static void arm_test_cpu_arch_data (void) { const arch_option *arch; const cpu_option *cpu; + auto_sbitmap target_isa (isa_num_bits); auto_sbitmap isa1 (isa_num_bits); auto_sbitmap isa2 (isa_num_bits); @@ -31231,6 +31243,8 @@ arm_test_cpu_arch_data (void) if (arch->common.extensions == NULL) continue; + arm_initialize_isa (target_isa, arch->common.isa_bits); + for (ext1 = arch->common.extensions; ext1->name != NULL; ++ext1) { if (ext1->alias) @@ -31243,7 +31257,13 @@ arm_test_cpu_arch_data (void) continue; arm_initialize_isa (isa2, ext2->isa_bits); + /* If the option is a subset of the parent option, it doesn't + add anything and so isn't useful. */ ASSERT_TRUE (!bitmap_subset_p (isa2, isa1)); + + /* If the extension specifies any architectural bits then + disallow it. Extensions should only specify feature bits. */ + ASSERT_TRUE (!bitmap_intersect_p (isa2, target_isa)); } } } @@ -31255,6 +31275,8 @@ arm_test_cpu_arch_data (void) if (cpu->common.extensions == NULL) continue; + arm_initialize_isa (target_isa, arch->common.isa_bits); + for (ext1 = cpu->common.extensions; ext1->name != NULL; ++ext1) { if (ext1->alias) @@ -31267,7 +31289,13 @@ arm_test_cpu_arch_data (void) continue; arm_initialize_isa (isa2, ext2->isa_bits); + /* If the option is a subset of the parent option, it doesn't + add anything and so isn't useful. */ ASSERT_TRUE (!bitmap_subset_p (isa2, isa1)); + + /* If the extension specifies any architectural bits then + disallow it. Extensions should only specify feature bits. */ + ASSERT_TRUE (!bitmap_intersect_p (isa2, target_isa)); } } } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 43d44778bdc..4f53583cf02 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -196,10 +196,6 @@ extern tree arm_fp16_type_node; /* FPU supports fused-multiply-add operations. */ #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4)) -/* FPU is ARMv8 compatible. */ -#define TARGET_FPU_ARMV8 \ - (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8)) - /* FPU supports Crypto extensions. */ #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) @@ -216,7 +212,7 @@ extern tree arm_fp16_type_node; /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */ #define TARGET_VFP_FP16INST \ - (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst) + (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) @@ -384,7 +380,8 @@ enum base_architecture BASE_ARCH_7EM = 7, BASE_ARCH_8A = 8, BASE_ARCH_8M_BASE = 8, - BASE_ARCH_8M_MAIN = 8 + BASE_ARCH_8M_MAIN = 8, + BASE_ARCH_8R = 8 }; /* The major revision number of the ARM Architecture implemented by the target. */ @@ -2189,13 +2186,7 @@ extern int making_const_table; /* Expands to an upper-case char of the target's architectural profile. */ #define TARGET_ARM_ARCH_PROFILE \ - (!arm_arch_notm \ - ? 'M' \ - : (arm_arch7 \ - ? (strlen (arm_arch_name) >=3 \ - ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ - : 0) \ - : 0)) + (arm_active_target.profile) /* Bit-field indicating what size LDREX/STREX loads/stores are available. Bit 0 for bytes, up to bit 3 for double-words. */ @@ -2263,11 +2254,16 @@ const char *arm_canon_arch_option (int argc, const char **argv); #define CANON_ARCH_SPEC_FUNCTION \ { "canon_arch", arm_canon_arch_option }, +const char *arm_be8_option (int argc, const char **argv); +#define BE8_SPEC_FUNCTION \ + { "be8_linkopt", arm_be8_option }, + # define EXTRA_SPEC_FUNCTIONS \ MCPU_MTUNE_NATIVE_FUNCTIONS \ ASM_CPU_SPEC_FUNCTIONS \ CANON_ARCH_SPEC_FUNCTION \ - TARGET_MODE_SPEC_FUNCTIONS + TARGET_MODE_SPEC_FUNCTIONS \ + BE8_SPEC_FUNCTION /* Automatically add -mthumb for Thumb-only targets if mode isn't specified via the configuration option --with-mode or via the command line. The diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index e6e1ac54a85..049a78edefe 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -7879,7 +7879,7 @@ "<F_constraint>") (match_operand:SDF 4 "s_register_operand" "<F_constraint>")))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" + "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "* { enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]); diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index dad52576872..6060516dd40 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -95,7 +95,7 @@ Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) Generate code in 32 bit ARM state. mbig-endian -Target Report RejectNegative Mask(BIG_END) +Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END) Assume target CPU is configured as big endian. mcallee-super-interworking @@ -160,7 +160,7 @@ mhard-float Target RejectNegative Alias(mfloat-abi=, hard) Undocumented mlittle-endian -Target Report RejectNegative InverseMask(BIG_END) +Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END) Assume target CPU is configured as little endian. mlong-calls @@ -192,7 +192,7 @@ Target RejectNegative Alias(mfloat-abi=, soft) Undocumented mstructure-size-boundary= Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) -Specify the minimum bit alignment of structures. +Specify the minimum bit alignment of structures. (Deprecated). mthumb Target Report RejectNegative Negative(marm) Mask(THUMB) Save @@ -286,3 +286,11 @@ Assume unified syntax for inline assembly code. mpure-code Target Report Var(target_pure_code) Init(0) Do not allow constant data to be placed in code sections. + +mbe8 +Target Report RejectNegative Negative(mbe32) Mask(BE8) +When linking for big-endian targets, generate a BE8 format image. + +mbe32 +Target Report RejectNegative Negative(mbe8) InverseMask(BE8) +When linking for big-endian targets, generate a legacy BE32 format image. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 65f36e2c91e..0d436e83d0f 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -28,7 +28,7 @@ #define _GCC_ARM_NEON_H 1 #ifndef __ARM_FP -#error "NEON intrinsics not available with the soft-float ABI. Please use -mfloat-abi=softp or -mfloat-abi=hard" +#error "NEON intrinsics not available with the soft-float ABI. Please use -mfloat-abi=softfp or -mfloat-abi=hard" #else #pragma GCC push_options diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index d38863a3cd3..2f41c4ffbdb 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -26,7 +26,7 @@ /* Use the AAPCS ABI by default. */ #define ARM_DEFAULT_ABI ARM_ABI_AAPCS -/* Assume that AAPCS ABIs should adhere to the full BPABI. */ +/* Assume that AAPCS ABIs should adhere to the full BPABI. */ #define TARGET_BPABI (TARGET_AAPCS_BASED) /* BPABI targets use EABI frame unwinding tables. */ @@ -55,84 +55,11 @@ #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -#if TARGET_BIG_ENDIAN_DEFAULT -#define BE8_LINK_SPEC \ - " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5 \ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ - |mcpu=cortex-a12|mcpu=cortex-a17 \ - |mcpu=cortex-a15.cortex-a7 \ - |mcpu=cortex-a17.cortex-a7 \ - |mcpu=marvell-pj4 \ - |mcpu=cortex-a32 \ - |mcpu=cortex-a35 \ - |mcpu=cortex-a53 \ - |mcpu=cortex-a57 \ - |mcpu=cortex-a57.cortex-a53 \ - |mcpu=cortex-a72 \ - |mcpu=cortex-a72.cortex-a53 \ - |mcpu=cortex-a73 \ - |mcpu=cortex-a73.cortex-a35 \ - |mcpu=cortex-a73.cortex-a53 \ - |mcpu=exynos-m1 \ - |mcpu=xgene1 \ - |mcpu=cortex-m1.small-multiply \ - |mcpu=cortex-m0.small-multiply \ - |mcpu=cortex-m0plus.small-multiply \ - |mcpu=generic-armv7-a \ - |march=armv7ve \ - |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ - |march=armv6-m|mcpu=cortex-m0 \ - |march=armv8-a \ - |march=armv8-a+crc \ - |march=armv8.1-a \ - |march=armv8.1-a+crc \ - |march=armv8.2-a \ - |march=armv8.2-a+fp16 \ - |march=armv8-m.base|mcpu=cortex-m23 \ - |march=armv8-m.main \ - |march=armv8-m.main+dsp|mcpu=cortex-m33 \ - :%{!r:--be8}}}" -#else -#define BE8_LINK_SPEC \ - " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ - |mcpu=cortex-a12|mcpu=cortex-a17 \ - |mcpu=cortex-a15.cortex-a7 \ - |mcpu=cortex-a17.cortex-a7 \ - |mcpu=cortex-a35 \ - |mcpu=cortex-a53 \ - |mcpu=cortex-a57 \ - |mcpu=cortex-a57.cortex-a53 \ - |mcpu=cortex-a72 \ - |mcpu=cortex-a72.cortex-a53 \ - |mcpu=cortex-a73 \ - |mcpu=cortex-a73.cortex-a35 \ - |mcpu=cortex-a73.cortex-a53 \ - |mcpu=exynos-m1 \ - |mcpu=xgene1 \ - |mcpu=cortex-m1.small-multiply \ - |mcpu=cortex-m0.small-multiply \ - |mcpu=cortex-m0plus.small-multiply \ - |mcpu=marvell-pj4 \ - |mcpu=generic-armv7-a \ - |march=armv7ve \ - |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ - |march=armv6-m|mcpu=cortex-m0 \ - |march=armv8-a \ - |march=armv8-a+crc \ - |march=armv8.1-a \ - |march=armv8.1-a+crc \ - |march=armv8.2-a \ - |march=armv8.2-a+fp16 \ - |march=armv8-m.base|mcpu=cortex-m23 \ - |march=armv8-m.main \ - |march=armv8-m.main+dsp|mcpu=cortex-m33 \ - :%{!r:--be8}}}" -#endif +#define BE8_LINK_SPEC \ + "%{!r:%{!mbe32:%:be8_linkopt(%{mlittle-endian:little}" \ + " %{mbig-endian:big}" \ + " %{mbe8:be8}" \ + " %{march=*:arch %*})}}" /* Tell the assembler to build BPABI binaries. */ #undef SUBTARGET_EXTRA_ASM_SPEC diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 3c613375756..6734e37be49 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -211,7 +211,7 @@ (define_bypass 1 "cortex_a53_alu*" "cortex_a53_alu_shift*" - "aarch_forward_to_shift_is_not_shifted_reg") + "arm_no_early_alu_shift_dep") (define_bypass 2 "cortex_a53_alu*" "cortex_a53_alu_*,cortex_a53_shift*") diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index b034f13fda6..5c29b94caab 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -52,8 +52,13 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd07", "armv8-a+crc", "cortex-a57"}, {"0xd08", "armv8-a+crc", "cortex-a72"}, {"0xd09", "armv8-a+crc", "cortex-a73"}, + {"0xd05", "armv8.2-a+fp16", "cortex-a55"}, + {"0xd0a", "armv8.2-a+fp16", "cortex-a75"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, + {"0xc17", "armv7-r", "cortex-r7"}, + {"0xc18", "armv7-r", "cortex-r8"}, + {"0xd13", "armv8-r+crc", "cortex-r52"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"}, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 0ce3fe415e6..235c46da1a1 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -678,7 +678,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" - "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -688,7 +688,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" - "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -720,7 +720,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" - "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -731,7 +731,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" - "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -751,8 +751,8 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")] NEON_VRINT))] - "TARGET_NEON && TARGET_FPU_ARMV8" - "vrint<nvrint_variant>%?.f32\\t%<V_reg>0, %<V_reg>1" + "TARGET_NEON && TARGET_VFP5" + "vrint<nvrint_variant>.f32\\t%<V_reg>0, %<V_reg>1" [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")] ) @@ -761,7 +761,7 @@ (FIXUORS:<V_cmp_result> (unspec:VCVTF [(match_operand:VCVTF 1 "register_operand" "w")] NEON_VCVT)))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "vcvt<nvrint_variant>.<su>32.f32\\t%<V_reg>0, %<V_reg>1" [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>") (set_attr "predicable" "no")] @@ -2901,7 +2901,7 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") (match_operand:VCVTF 2 "s_register_operand" "w")] VMAXMINFNM))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_minmax_s<q>")] ) @@ -2912,7 +2912,7 @@ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") (match_operand:VCVTF 2 "s_register_operand" "w")] VMAXMINFNM))] - "TARGET_NEON && TARGET_FPU_ARMV8" + "TARGET_NEON && TARGET_VFP5" "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_minmax_s<q>")] ) diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index b6e50932ddc..070d193b338 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -223,10 +223,39 @@ function gen_comm_data () { if (arch_opt_remove[feats[1],feats[m]] == "true") { fatal("cannot remove features from architecture specs") } - print " " arch_opt_isa[feats[1],feats[m]] "," + # The isa_features array that is being initialized here has a length + # of max isa_bit_num, which is the last entry in the enum. + # Logically this means that the number of features is implicitly + # never more than the number of feature bits we have. This is only + # true if we don't emit duplicates here. So keep track of which + # options we have already emitted so we don't emit them twice. + nopts = split (arch_opt_isa[feats[1],feats[m]], opts, ",") + for (i = 1; i <= nopts; i++) { + if (! (opts[i] in seen)) { + print " " opts[i] "," + seen[opts[i]] + } + } } - if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," - if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," + if (cpus[n] in cpu_fpu) { + nopts = split (fpu_isa[cpu_fpu[cpus[n]]], opts, ",") + for (i = 1; i <= nopts; i++) { + if (! (opts[i] in seen)) { + print " " opts[i] "," + seen[opts[i]] + } + } + } + if (cpus[n] in cpu_isa) { + nopts = split (cpu_isa[cpus[n]], opts, ",") + for (i = 1; i <= nopts; i++) { + if (! (opts[i] in seen)) { + print " " opts[i] "," + seen[opts[i]] + } + } + } + delete seen print " isa_nobit" print " }" print " }," @@ -299,13 +328,19 @@ function gen_comm_data () { # arch, base_arch print " \"" arch_base[archs[n]] "\", BASE_ARCH_" \ arch_base[archs[n]] "," + # profile letter code, or zero if none. + if (archs[n] in arch_prof) { + print " '" arch_prof[archs[n]] "'," + } else { + print " 0," + } # tune_id print " TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] "," print " }," } print " {{NULL, NULL, {isa_nobit}}," - print " NULL, BASE_ARCH_0, TARGET_CPU_arm_none}" + print " NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none}" print "};\n" print "const arm_fpu_desc all_fpus[] =" @@ -477,6 +512,12 @@ BEGIN { parse_ok = 1 } +/^[ ]*profile / { + if (arch_name == "") fatal("\"profile\" statement outside of arch block") + arch_prof[arch_name] = $2 + parse_ok = 1 +} + /^end arch / { if (arch_name != $3) fatal("mimatched end arch") if (! arch_name in arch_tune_for) { diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index afb5d6339a8..3e25cd16b29 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -350,9 +350,9 @@ (define_special_predicate "arm_cond_move_operator" (if_then_else (match_test "arm_restrict_it") - (and (match_test "TARGET_FPU_ARMV8") - (match_operand 0 "arm_vsel_comparison_operator")) - (match_operand 0 "expandable_comparison_operator"))) + (and (match_test "TARGET_VFP5") + (match_operand 0 "arm_vsel_comparison_operator")) + (match_operand 0 "expandable_comparison_operator"))) (define_special_predicate "noov_comparison_operator" (match_code "lt,ge,eq,ne")) diff --git a/gcc/config/arm/rtems.h b/gcc/config/arm/rtems.h index b34bbe8a063..77eb32c1d20 100644 --- a/gcc/config/arm/rtems.h +++ b/gcc/config/arm/rtems.h @@ -1,20 +1,25 @@ /* Definitions for RTEMS based ARM systems using EABI. Copyright (C) 2011-2017 Free Software Foundation, Inc. - + This file is part of GCC. - + GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ #define HAS_INIT_SECTION diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index b6a3cb40c5d..16177e0bbbc 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -18,7 +18,8 @@ # along with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. -TM_H += $(srcdir)/config/arm/arm-cpu.h +TM_H += arm-cpu.h +GTM_H += arm-cpu.h # All md files - except for arm.md. # This list should be kept in alphabetical order and updated whenever an md @@ -75,26 +76,32 @@ $(srcdir)/config/arm/arm-tune.md: $(srcdir)/config/arm/parsecpu.awk \ $(srcdir)/config/arm/arm-tables.opt: $(srcdir)/config/arm/parsecpu.awk \ $(srcdir)/config/arm/arm-cpus.in $(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=opt \ - $(srcdir)/config/arm/arm-cpus.in > \ - $(srcdir)/config/arm/arm-tables.opt + $(srcdir)/config/arm/arm-cpus.in > arm-tables.new + mv arm-tables.new $(srcdir)/config/arm/arm-tables.opt -$(srcdir)/config/arm/arm-cpu.h: $(srcdir)/config/arm/parsecpu.awk \ +arm-cpu.h: s-arm-cpu ; @true +s-arm-cpu: $(srcdir)/config/arm/parsecpu.awk \ $(srcdir)/config/arm/arm-cpus.in $(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=headers \ - $(srcdir)/config/arm/arm-cpus.in > arm-cpu.new - mv arm-cpu.new $(srcdir)/config/arm/arm-cpu.h + $(srcdir)/config/arm/arm-cpus.in > tmp-arm-cpu.h + $(SHELL) $(srcdir)/../move-if-change tmp-arm-cpu.h arm-cpu.h + $(STAMP) s-arm-cpu -$(srcdir)/config/arm/arm-cpu-data.h: $(srcdir)/config/arm/parsecpu.awk \ +arm-cpu-data.h: s-arm-data ; @true +s-arm-data: $(srcdir)/config/arm/parsecpu.awk \ $(srcdir)/config/arm/arm-cpus.in $(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=data \ - $(srcdir)/config/arm/arm-cpus.in > arm-cpu-data.new - mv arm-cpu-data.new $(srcdir)/config/arm/arm-cpu-data.h + $(srcdir)/config/arm/arm-cpus.in > tmp-arm-cpu-data.h + $(SHELL) $(srcdir)/../move-if-change tmp-arm-cpu-data.h arm-cpu-data.h + $(STAMP) s-arm-data -$(srcdir)/config/arm/arm-cpu-cdata.h: $(srcdir)/config/arm/parsecpu.awk \ +arm-cpu-cdata.h: s-arm-cdata ; @true +s-arm-cdata: $(srcdir)/config/arm/parsecpu.awk \ $(srcdir)/config/arm/arm-cpus.in $(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=common-data \ - $(srcdir)/config/arm/arm-cpus.in > arm-cpu-cdata.new - mv arm-cpu-cdata.new $(srcdir)/config/arm/arm-cpu-cdata.h + $(srcdir)/config/arm/arm-cpus.in > tmp-arm-cpu-cdata.h + $(SHELL) $(srcdir)/../move-if-change tmp-arm-cpu-cdata.h arm-cpu-cdata.h + $(STAMP) s-arm-cdata aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \ coretypes.h $(TM_H) $(TM_P_H) $(RTL_H) $(TREE_H) output.h $(C_COMMON_H) @@ -109,7 +116,7 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \ $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \ intl.h libfuncs.h $(PARAMS_H) $(OPTS_H) sched-int.h \ - $(srcdir)/config/arm/arm-cpu-data.h \ + arm-cpu-data.h \ $(srcdir)/config/arm/arm-protos.h \ $(srcdir)/config/arm/arm_neon_builtins.def \ $(srcdir)/config/arm/arm_vfp_builtins.def @@ -130,4 +137,4 @@ arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/arm/arm-c.c -arm-common.o: $(srcdir)/config/arm/arm-cpu-cdata.h +arm-common.o: arm-cpu-cdata.h diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d8f77e2ffe4..23c1d67c9e3 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1997,7 +1997,7 @@ (FIXUORS:SI (unspec:SDF [(match_operand:SDF 1 "register_operand" "<F_constraint>")] VCVT)))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" + "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" [(set_attr "predicable" "no") (set_attr "conds" "unconditional") diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 9af37c7f4f5..f20324f144d 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -117,3 +117,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* This platform supports the probing method of stack checking (RTP mode). 8K is reserved in the stack to propagate exceptions in case of overflow. */ #define STACK_CHECK_PROTECT 8192 + +/* Unless overridded by the target options, the default is little-endian. */ +#define TARGET_ENDIAN_DEFAULT 0 |