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-rw-r--r--gcc/config/arm/arm.c1
-rw-r--r--gcc/config/arm/iterators.md8
-rw-r--r--gcc/config/arm/neon.md26
-rw-r--r--gcc/config/arm/t-vxworks10
-rw-r--r--gcc/config/arm/vxworks.h81
5 files changed, 89 insertions, 37 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 25677d19e20..fa3e2fa6c76 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -32,6 +32,7 @@
#include "df.h"
#include "tm_p.h"
#include "stringpool.h"
+#include "attribs.h"
#include "optabs.h"
#include "regs.h"
#include "emit-rtl.h"
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 48992879a8e..7acbaf1bb40 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -444,6 +444,14 @@
(V2SF "SF") (V4SF "SF")
(DI "DI") (V2DI "DI")])
+;; As above but in lower case.
+(define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi")
+ (V4HI "hi") (V8HI "hi")
+ (V4HF "hf") (V8HF "hf")
+ (V2SI "si") (V4SI "si")
+ (V2SF "sf") (V4SF "sf")
+ (DI "di") (V2DI "di")])
+
;; Element modes for vector extraction, padded up to register size.
(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 235c46da1a1..45b3bd18052 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -412,7 +412,7 @@
DONE;
})
-(define_insn "vec_extract<mode>"
+(define_insn "vec_extract<mode><V_elem_l>"
[(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=Um,r")
(vec_select:<V_elem>
(match_operand:VD_LANE 1 "s_register_operand" "w,w")
@@ -434,7 +434,7 @@
[(set_attr "type" "neon_store1_one_lane<q>,neon_to_gp<q>")]
)
-(define_insn "vec_extract<mode>"
+(define_insn "vec_extract<mode><V_elem_l>"
[(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=Um,r")
(vec_select:<V_elem>
(match_operand:VQ2 1 "s_register_operand" "w,w")
@@ -460,7 +460,7 @@
[(set_attr "type" "neon_store1_one_lane<q>,neon_to_gp<q>")]
)
-(define_insn "vec_extractv2di"
+(define_insn "vec_extractv2didi"
[(set (match_operand:DI 0 "nonimmediate_operand" "=Um,r")
(vec_select:DI
(match_operand:V2DI 1 "s_register_operand" "w,w")
@@ -479,7 +479,7 @@
[(set_attr "type" "neon_store1_one_lane_q,neon_to_gp_q")]
)
-(define_expand "vec_init<mode>"
+(define_expand "vec_init<mode><V_elem_l>"
[(match_operand:VDQ 0 "s_register_operand" "")
(match_operand 1 "" "")]
"TARGET_NEON"
@@ -1581,7 +1581,7 @@
neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpadd_internal<mode>);
/* The same result is actually computed into every element. */
- emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], vec, const0_rtx));
DONE;
})
@@ -1607,7 +1607,7 @@
rtx vec = gen_reg_rtx (V2DImode);
emit_insn (gen_arm_reduc_plus_internal_v2di (vec, operands[1]));
- emit_insn (gen_vec_extractv2di (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extractv2didi (operands[0], vec, const0_rtx));
DONE;
})
@@ -1631,7 +1631,7 @@
neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpsmin<mode>);
/* The result is computed into every element of the vector. */
- emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], vec, const0_rtx));
DONE;
})
@@ -1658,7 +1658,7 @@
neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpsmax<mode>);
/* The result is computed into every element of the vector. */
- emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], vec, const0_rtx));
DONE;
})
@@ -1685,7 +1685,7 @@
neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpumin<mode>);
/* The result is computed into every element of the vector. */
- emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], vec, const0_rtx));
DONE;
})
@@ -1711,7 +1711,7 @@
neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpumax<mode>);
/* The result is computed into every element of the vector. */
- emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], vec, const0_rtx));
DONE;
})
@@ -3272,7 +3272,8 @@
}
if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
- emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], operands[1],
+ operands[2]));
else
emit_insn (gen_neon_vget_lane<mode>_sext_internal (operands[0],
operands[1],
@@ -3301,7 +3302,8 @@
}
if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
- emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
+ emit_insn (gen_vec_extract<mode><V_elem_l> (operands[0], operands[1],
+ operands[2]));
else
emit_insn (gen_neon_vget_lane<mode>_zext_internal (operands[0],
operands[1],
diff --git a/gcc/config/arm/t-vxworks b/gcc/config/arm/t-vxworks
index 093d7fae88b..0a3840ba8fe 100644
--- a/gcc/config/arm/t-vxworks
+++ b/gcc/config/arm/t-vxworks
@@ -16,9 +16,7 @@
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
-MULTILIB_OPTIONS = \
- mrtp fPIC \
- t4/t4be/t4t/t4tbe/t5/t5be/t5t/t5tbe/tstrongarm/txscale/txscalebe
-MULTILIB_MATCHES = fPIC=fpic
-# Don't build -fPIC multilibs for kernel or Thumb code.
-MULTILIB_EXCEPTIONS = fPIC* mrtp/fPIC/*t[45]t*
+MULTILIB_OPTIONS = mrtp fPIC
+
+# -fPIC alone is not supported, only together with -mrtp
+MULTILIB_EXCEPTIONS = fPIC
diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h
index f20324f144d..59f6282a0ea 100644
--- a/gcc/config/arm/vxworks.h
+++ b/gcc/config/arm/vxworks.h
@@ -26,7 +26,15 @@ a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
+/* TARGET_OS_CPP_BUILTINS, down to BPABI if defined. */
+#if defined (TARGET_BPABI_CPP_BUILTINS)
+#define MAYBE_TARGET_BPABI_CPP_BUILTINS TARGET_BPABI_CPP_BUILTINS
+#else
+#define MAYBE_TARGET_BPABI_CPP_BUILTINS()
+#endif
+
+#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do { \
if (TARGET_BIG_END) \
@@ -36,8 +44,29 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
\
if (arm_arch_xscale) \
builtin_define ("CPU=XSCALE"); \
+ else if (arm_arch7) \
+ { \
+ if (!arm_arch_notm) \
+ builtin_define ("CPU=ARMARCH7M"); \
+ else if (TARGET_THUMB) \
+ builtin_define ("CPU=ARMARCH7_T2"); \
+ else \
+ builtin_define ("CPU=ARMARCH7"); \
+ } \
+ else if (arm_arch6) \
+ { \
+ if (TARGET_THUMB) \
+ builtin_define ("CPU=ARMARCH6_T"); \
+ else \
+ builtin_define ("CPU=ARMARCH6"); \
+ } \
else if (arm_arch5) \
- builtin_define ("CPU=ARMARCH5"); \
+ { \
+ if (TARGET_THUMB) \
+ builtin_define ("CPU=ARMARCH5_T"); \
+ else \
+ builtin_define ("CPU=ARMARCH5"); \
+ } \
else if (arm_arch4) \
{ \
if (TARGET_THUMB) \
@@ -46,6 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
builtin_define ("CPU=ARMARCH4"); \
} \
VXWORKS_OS_CPP_BUILTINS (); \
+ MAYBE_TARGET_BPABI_CPP_BUILTINS (); \
} while (0)
#undef SUBTARGET_OVERRIDE_OPTIONS
@@ -55,27 +85,32 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC "-D__ELF__" VXWORKS_ADDITIONAL_CPP_SPEC
+/* .text.hot and .text.unlikely sections are badly handled by the
+ VxWorks kernel mode loader for ARM style exceptions. */
+
+#if ARM_UNWIND_INFO
+#define EXTRA_CC1_SPEC "%{!mrtp:-fno-reorder-functions}"
+#else
+#define EXTRA_CC1_SPEC
+#endif
+
#undef CC1_SPEC
-#define CC1_SPEC \
-"%{tstrongarm:-mlittle-endian -mcpu=strongarm ; \
- t4: -mlittle-endian -march=armv4 ; \
- t4be: -mbig-endian -march=armv4 ; \
- t4t: -mthumb -mthumb-interwork -mlittle-endian -march=armv4t ; \
- t4tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv4t ; \
- t5: -mlittle-endian -march=armv5 ; \
- t5be: -mbig-endian -march=armv5 ; \
- t5t: -mthumb -mthumb-interwork -mlittle-endian -march=armv5 ; \
- t5tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv5 ; \
- txscale: -mlittle-endian -mcpu=xscale ; \
- txscalebe: -mbig-endian -mcpu=xscale ; \
- : -march=armv4}"
-
-/* Pass -EB for big-endian targets. */
-#define VXWORKS_ENDIAN_SPEC \
- "%{mbig-endian|t4be|t4tbe|t5be|t5tbe|txscalebe:-EB}"
+#define CC1_SPEC "" EXTRA_CC1_SPEC
+
+/* Translate an explicit -mbig-endian as an explicit -EB to assembler
+ and linker, and pass abi options matching the target expectations
+ or command-line requests. */
+#define VXWORKS_ENDIAN_SPEC "%{mbig-endian:-EB}"
+
+#if defined (TARGET_BPABI_CPP_BUILTINS)
+#define MAYBE_ASM_ABI_SPEC \
+ "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC
+#else
+#define MAYBE_ASM_ABI_SPEC
+#endif
#undef SUBTARGET_EXTRA_ASM_SPEC
-#define SUBTARGET_EXTRA_ASM_SPEC VXWORKS_ENDIAN_SPEC
+#define SUBTARGET_EXTRA_ASM_SPEC MAYBE_ASM_ABI_SPEC " " VXWORKS_ENDIAN_SPEC
#undef LINK_SPEC
#define LINK_SPEC VXWORKS_LINK_SPEC " " VXWORKS_ENDIAN_SPEC
@@ -89,6 +124,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC VXWORKS_ENDFILE_SPEC
+/* For exceptions, pre VX7 uses DWARF2 info, VX7 uses ARM unwinding. */
+#undef DWARF2_UNWIND_INFO
+#define DWARF2_UNWIND_INFO (!TARGET_VXWORKS7)
+
+#undef ARM_TARGET2_DWARF_FORMAT
+#define ARM_TARGET2_DWARF_FORMAT \
+ (TARGET_VXWORKS_RTP ? DW_EH_PE_pcrel : DW_EH_PE_absptr)
+
/* There is no default multilib. */
#undef MULTILIB_DEFAULTS
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