diff options
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64-cores.def | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-option-extensions.def | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 37 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 40 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 43 | ||||
| -rw-r--r-- | gcc/config/aarch64/falkor.md | 681 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 5 |
8 files changed, 789 insertions, 34 deletions
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index b8d0ba6b69e..10893324d3f 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -65,8 +65,8 @@ AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1) /* Qualcomm ('Q') cores. */ -AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) -AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) +AARCH64_CORE("falkor", falkor, falkor, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) +AARCH64_CORE("qdf24xx", qdf24xx, falkor, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) /* Samsung ('S') cores. */ AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index c4f059ab7c5..a989a2ec23e 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -65,6 +65,6 @@ AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, "lrcpc") /* Enabling "rdma" also enables "fp", "simd". Disabling "rdma" just disables "rdma". */ -AARCH64_OPT_EXTENSION("rdma", AARCH64_FL_RDMA, AARCH64_FL_FP | AARCH64_FL_SIMD, 0, "rdma") +AARCH64_OPT_EXTENSION("rdma", AARCH64_FL_RDMA, AARCH64_FL_FP | AARCH64_FL_SIMD, 0, "asimdrdm") #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 011fcec0795..f74b68775cf 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -351,6 +351,35 @@ } ) +(define_expand "xorsign<mode>3" + [(match_operand:VHSDF 0 "register_operand") + (match_operand:VHSDF 1 "register_operand") + (match_operand:VHSDF 2 "register_operand")] + "TARGET_SIMD" +{ + + machine_mode imode = <V_cmp_result>mode; + rtx v_bitmask = gen_reg_rtx (imode); + rtx op1x = gen_reg_rtx (imode); + rtx op2x = gen_reg_rtx (imode); + + rtx arg1 = lowpart_subreg (imode, operands[1], <MODE>mode); + rtx arg2 = lowpart_subreg (imode, operands[2], <MODE>mode); + + int bits = GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1; + + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (<V_cmp_result>mode, + HOST_WIDE_INT_M1U << bits)); + + emit_insn (gen_and<v_cmp_result>3 (op2x, v_bitmask, arg2)); + emit_insn (gen_xor<v_cmp_result>3 (op1x, arg1, op2x)); + emit_move_insn (operands[0], + lowpart_subreg (<MODE>mode, op1x, imode)); + DONE; +} +) + (define_expand "copysign<mode>3" [(match_operand:VHSDF 0 "register_operand") (match_operand:VHSDF 1 "register_operand") @@ -5617,9 +5646,9 @@ DONE; }) -;; Standard pattern name vec_init<mode>. +;; Standard pattern name vec_init<mode><Vel>. -(define_expand "vec_init<mode>" +(define_expand "vec_init<mode><Vel>" [(match_operand:VALL_F16 0 "register_operand" "") (match_operand 1 "" "")] "TARGET_SIMD" @@ -5674,9 +5703,9 @@ "urecpe\\t%0.<Vtype>, %1.<Vtype>" [(set_attr "type" "neon_fp_recpe_<Vetype><q>")]) -;; Standard pattern name vec_extract<mode>. +;; Standard pattern name vec_extract<mode><Vel>. -(define_expand "vec_extract<mode>" +(define_expand "vec_extract<mode><Vel>" [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "") (match_operand:VALL_F16 1 "register_operand" "") (match_operand:SI 2 "immediate_operand" "")] diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 055ebafb830..28c4e0e6476 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -33,6 +33,7 @@ #include "df.h" #include "tm_p.h" #include "stringpool.h" +#include "attribs.h" #include "optabs.h" #include "regs.h" #include "emit-rtl.h" @@ -3069,7 +3070,7 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno, reg = gen_rtx_REG (mode, regno); mem = gen_rtx_PRE_MODIFY (Pmode, base_rtx, plus_constant (Pmode, base_rtx, -adjustment)); - mem = gen_rtx_MEM (mode, mem); + mem = gen_frame_mem (mode, mem); insn = emit_move_insn (mem, reg); RTX_FRAME_RELATED_P (insn) = 1; @@ -3157,7 +3158,7 @@ aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, { rtx mem = plus_constant (Pmode, stack_pointer_rtx, adjustment); mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem); - emit_move_insn (reg1, gen_rtx_MEM (mode, mem)); + emit_move_insn (reg1, gen_frame_mem (mode, mem)); } else { @@ -3233,8 +3234,6 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, unsigned start, unsigned limit, bool skip_wb) { rtx_insn *insn; - rtx (*gen_mem_ref) (machine_mode, rtx) = (frame_pointer_needed - ? gen_frame_mem : gen_rtx_MEM); unsigned regno; unsigned regno2; @@ -3255,8 +3254,8 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, reg = gen_rtx_REG (mode, regno); offset = start_offset + cfun->machine->frame.reg_offset[regno]; - mem = gen_mem_ref (mode, plus_constant (Pmode, stack_pointer_rtx, - offset)); + mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, + offset)); regno2 = aarch64_next_callee_save (regno + 1, limit); @@ -3270,8 +3269,8 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, rtx mem2; offset = start_offset + cfun->machine->frame.reg_offset[regno2]; - mem2 = gen_mem_ref (mode, plus_constant (Pmode, stack_pointer_rtx, - offset)); + mem2 = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, + offset)); insn = emit_insn (aarch64_gen_store_pair (mode, mem, reg, mem2, reg2)); @@ -3300,8 +3299,6 @@ aarch64_restore_callee_saves (machine_mode mode, unsigned limit, bool skip_wb, rtx *cfi_ops) { rtx base_rtx = stack_pointer_rtx; - rtx (*gen_mem_ref) (machine_mode, rtx) = (frame_pointer_needed - ? gen_frame_mem : gen_rtx_MEM); unsigned regno; unsigned regno2; HOST_WIDE_INT offset; @@ -3322,7 +3319,7 @@ aarch64_restore_callee_saves (machine_mode mode, reg = gen_rtx_REG (mode, regno); offset = start_offset + cfun->machine->frame.reg_offset[regno]; - mem = gen_mem_ref (mode, plus_constant (Pmode, base_rtx, offset)); + mem = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset)); regno2 = aarch64_next_callee_save (regno + 1, limit); @@ -3335,7 +3332,7 @@ aarch64_restore_callee_saves (machine_mode mode, rtx mem2; offset = start_offset + cfun->machine->frame.reg_offset[regno2]; - mem2 = gen_mem_ref (mode, plus_constant (Pmode, base_rtx, offset)); + mem2 = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset)); emit_insn (aarch64_gen_load_pair (mode, reg, mem, reg2, mem2)); *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops); @@ -4733,9 +4730,14 @@ aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *intval) CONST_DOUBLE_REAL_VALUE (value), REAL_MODE_FORMAT (mode)); - ival = zext_hwi (res[0], 32); - if (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (DFmode)) - ival |= (zext_hwi (res[1], 32) << 32); + if (mode == DFmode) + { + int order = BYTES_BIG_ENDIAN ? 1 : 0; + ival = zext_hwi (res[order], 32); + ival |= (zext_hwi (res[1 - order], 32) << 32); + } + else + ival = zext_hwi (res[0], 32); *intval = ival; return true; @@ -4787,10 +4789,6 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode) if (!TARGET_SIMD) return false; - /* We make a general exception for 0. */ - if (aarch64_float_const_zero_rtx_p (x)) - return true; - machine_mode vmode, imode; unsigned HOST_WIDE_INT ival; @@ -4800,6 +4798,10 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode) if (!aarch64_reinterpret_float_as_int (x, &ival)) return false; + /* We make a general exception for 0. */ + if (aarch64_float_const_zero_rtx_p (x)) + return true; + imode = int_mode_for_mode (mode); } else if (GET_CODE (x) == CONST_INT diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index fc799479c81..64b60a903ed 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -231,6 +231,7 @@ (include "../arm/cortex-a53.md") (include "../arm/cortex-a57.md") (include "../arm/exynos-m1.md") +(include "falkor.md") (include "thunderx.md") (include "../arm/xgene1.md") (include "thunderx2t99.md") @@ -1076,7 +1077,7 @@ [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w ,w,m,r,m ,r") (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) - || aarch64_reg_or_fp_float (operands[1], HFmode))" + || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ movi\\t%0.4h, #0 fmov\\t%h0, %w1 @@ -1099,7 +1100,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w ,w,m,r,m ,r,r") (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r,M"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) - || aarch64_reg_or_fp_float (operands[1], SFmode))" + || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ movi\\t%0.2s, #0 fmov\\t%s0, %w1 @@ -1123,7 +1124,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=w, w ,?r,w,w ,w ,w,m,r,m ,r,r") (match_operand:DF 1 "general_operand" "Y , ?rY, w,w,Ufc,Uvi,m,w,m,rY,r,N"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) - || aarch64_reg_or_fp_float (operands[1], DFmode))" + || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ movi\\t%d0, #0 fmov\\t%d0, %x1 @@ -5178,6 +5179,42 @@ } ) +;; For xorsign (x, y), we want to generate: +;; +;; LDR d2, #1<<63 +;; AND v3.8B, v1.8B, v2.8B +;; EOR v0.8B, v0.8B, v3.8B +;; + +(define_expand "xorsign<mode>3" + [(match_operand:GPF 0 "register_operand") + (match_operand:GPF 1 "register_operand") + (match_operand:GPF 2 "register_operand")] + "TARGET_FLOAT && TARGET_SIMD" +{ + + machine_mode imode = <V_cmp_result>mode; + rtx mask = gen_reg_rtx (imode); + rtx op1x = gen_reg_rtx (imode); + rtx op2x = gen_reg_rtx (imode); + + int bits = GET_MODE_BITSIZE (<MODE>mode) - 1; + emit_move_insn (mask, GEN_INT (trunc_int_for_mode (HOST_WIDE_INT_M1U << bits, + imode))); + + emit_insn (gen_and<v_cmp_result>3 (op2x, mask, + lowpart_subreg (imode, operands[2], + <MODE>mode))); + emit_insn (gen_xor<v_cmp_result>3 (op1x, + lowpart_subreg (imode, operands[1], + <MODE>mode), + op2x)); + emit_move_insn (operands[0], + lowpart_subreg (<MODE>mode, op1x, imode)); + DONE; +} +) + ;; ------------------------------------------------------------------- ;; Reload support ;; ------------------------------------------------------------------- diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md new file mode 100644 index 00000000000..b422ab30c44 --- /dev/null +++ b/gcc/config/aarch64/falkor.md @@ -0,0 +1,681 @@ +;; Falkor pipeline description +;; Copyright (C) 2017 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "falkor") + +;; Complex int instructions (e.g. multiply and divide) execute in the X +;; pipeline. Simple int instructions execute in the X, Y, and Z pipelines. + +(define_cpu_unit "falkor_x" "falkor") +(define_cpu_unit "falkor_y" "falkor") +(define_cpu_unit "falkor_z" "falkor") + +;; Branches execute in the B pipeline or in one of the int pipelines depending +;; on how complex it is. Simple int insns (like movz) can also execute here. + +(define_cpu_unit "falkor_b" "falkor") + +;; Vector and FP insns execute in the VX and VY pipelines. + +(define_automaton "falkor_vfp") + +(define_cpu_unit "falkor_vx" "falkor_vfp") +(define_cpu_unit "falkor_vy" "falkor_vfp") + +;; Loads execute in the LD pipeline. +;; Stores execute in the ST, SD, and VSD pipelines, for address, data, and +;; vector data. + +(define_automaton "falkor_mem") + +(define_cpu_unit "falkor_ld" "falkor_mem") +(define_cpu_unit "falkor_st" "falkor_mem") +(define_cpu_unit "falkor_sd" "falkor_mem") +(define_cpu_unit "falkor_vsd" "falkor_mem") + +;; The GTOV and VTOG pipelines are for general to vector reg moves, and vice +;; versa. + +(define_cpu_unit "falkor_gtov" "falkor") +(define_cpu_unit "falkor_vtog" "falkor") + +;; Common reservation combinations. + +(define_reservation "falkor_vxvy" "falkor_vx|falkor_vy") +(define_reservation "falkor_zb" "falkor_z|falkor_b") +(define_reservation "falkor_xyz" "falkor_x|falkor_y|falkor_z") +(define_reservation "falkor_xyzb" "falkor_x|falkor_y|falkor_z|falkor_b") + +;; SIMD Floating-Point Instructions + +(define_insn_reservation "falkor_afp_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_neg_s,neon_fp_neg_d,neon_fp_abs_s,neon_fp_abs_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_1_vxvy_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_neg_s_q,neon_fp_neg_d_q,neon_fp_abs_s_q,neon_fp_abs_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_2_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_minmax_s,neon_fp_minmax_d,neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d,neon_fp_compare_s,neon_fp_compare_d,neon_fp_round_s,neon_fp_round_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_2_vxvy_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_minmax_d_q,neon_fp_compare_s_q,neon_fp_compare_d_q,neon_fp_round_s_q,neon_fp_round_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_3_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q,neon_fp_abd_s,neon_fp_abd_d,neon_fp_addsub_s,neon_fp_addsub_d,neon_fp_reduc_add_s,neon_fp_reduc_add_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_3_vxvy_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_abd_s_q,neon_fp_abd_d_q,neon_fp_addsub_s_q,neon_fp_addsub_d_q,neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_4_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_to_int_s,neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d,neon_fp_cvt_widen_h,neon_fp_cvt_widen_s")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_4_vxvy_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,neon_int_to_fp_s_q,neon_int_to_fp_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_5_vxvy_mul" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mul_s,neon_fp_mul_s_scalar")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_5_vxvy_mla" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mla_s,neon_fp_mla_s_scalar")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_5_vxvy_vxvy_mul" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_5_vxvy_vxvy_mla" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_6_vxvy_mul" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mul_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_6_vxvy_mla" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mla_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_afp_6_vxvy_vxvy_mul" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mul_d_q,neon_fp_mul_d_scalar_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_6_vxvy_vxvy_mla" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_mla_d_q,neon_fp_mla_d_scalar_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_afp_4_vxvy_vxvy_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_cvt_narrow_s_q,neon_fp_cvt_narrow_d_q")) + "falkor_vxvy+falkor_vxvy,falkor_vxvy") + +(define_insn_reservation "falkor_afp_6_vx_vy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_div_s")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_afp_11_vx_vy" 11 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_div_d")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_afp_6_vx_vy_vx_vy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_div_s_q")) + "(falkor_vx+falkor_vy),(falkor_vx+falkor_vy)") + +(define_insn_reservation "falkor_afp_11_vx_vy_vx_vy" 11 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_div_d_q")) + "(falkor_vx+falkor_vy),(falkor_vx+falkor_vy)") + +(define_insn_reservation "falkor_afp_12_vx_vy" 12 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_sqrt_s")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_afp_22_vx_vy" 22 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_sqrt_d")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_afp_12_vx_vy_vx_vy" 12 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_sqrt_s_q")) + "(falkor_vx+falkor_vy),(falkor_vx+falkor_vy)") + +(define_insn_reservation "falkor_afp_22_vx_vy_vx_vy" 22 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_sqrt_d_q")) + "(falkor_vx+falkor_vy),(falkor_vx+falkor_vy)") + +;; SIMD Integer Instructions + +(define_insn_reservation "falkor_ai_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_add,neon_reduc_add,neon_logic,neon_neg,neon_sub")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_1_vxvy_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_shift_imm_long,neon_add_q,neon_reduc_add_q,neon_logic_q,neon_neg_q,neon_sub_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_ai_2_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_add_long,neon_sub_long,neon_add_halve,neon_sub_halve,neon_shift_imm,neon_shift_reg,neon_minmax,neon_abs,neon_compare,neon_compare_zero,neon_tst")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_2_vxvy_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_add_halve_q,neon_sub_halve_q,neon_shift_imm_q,neon_shift_reg_q,neon_minmax_q,neon_abs_q,neon_compare_q,neon_compare_zero_q,neon_tst_q,neon_reduc_add_long")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_ai_3_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_shift_acc,neon_reduc_add_acc,neon_abd,neon_qadd,neon_qsub,neon_qabs,neon_qneg,neon_sat_shift_imm,neon_sat_shift_imm_narrow_q,neon_sat_shift_reg,neon_reduc_minmax")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_reduc_minmax_q")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_3_vxvy_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_shift_acc_q,neon_reduc_add_acc_q,neon_abd_q,neon_abd_long,neon_qadd_q,neon_qsub_q,neon_qabs_q,neon_qneg_q,neon_sat_shift_imm_q,neon_sat_shift_reg_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy_mul" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_mul_b,neon_mul_h,neon_mul_s,neon_mul_h_scalar,neon_mul_s_scalar,neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s,neon_sat_mul_h_scalar,neon_sat_mul_s_scalar")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy_mla" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,neon_mla_s_scalar")) + "falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy_vxvy_mul" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_mul_b_q,neon_mul_h_q,neon_mul_s_q,neon_mul_h_scalar_q,neon_mul_s_scalar_q,neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,neon_mul_d_long,neon_mul_h_scalar_long,neon_mul_s_scalar_long,neon_sat_mul_b_long,neon_sat_mul_h_long,neon_sat_mul_s_long,neon_sat_mul_h_scalar_q,neon_sat_mul_s_scalar_q,neon_sat_mul_h_scalar_long,neon_sat_mul_s_scalar_long")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy_vxvy_mla" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,neon_mla_h_scalar_q,neon_mla_s_scalar_q,neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,neon_mla_h_scalar_long,neon_mla_s_scalar_long,neon_sat_mla_b_long,neon_sat_mla_h_long,neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,neon_sat_mla_s_scalar_long")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_ai_4_vxvy_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_add_halve_narrow_q,neon_sub_halve_narrow_q,neon_arith_acc")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_2_ai_vxvy_vxvy_vxvy_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_add_widen,neon_sub_widen")) + "(falkor_vxvy+falkor_vxvy),(falkor_vxvy+falkor_vxvy)") + +(define_insn_reservation "falkor_4_ai_vxvy_vxvy_vxvy_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_arith_acc_q")) + "(falkor_vxvy+falkor_vxvy),(falkor_vxvy+falkor_vxvy)") + +;; SIMD Load Instructions + +(define_insn_reservation "falkor_ald_4_ld" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,neon_load1_all_lanes,neon_load2_one_lane")) + "falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_none" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_2reg,neon_load2_2reg,neon_load2_all_lanes")) + "falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_ld" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_2reg_q,neon_load2_2reg_q,neon_load2_all_lanes_q,neon_load3_one_lane,neon_load4_one_lane,neon_ldp,neon_ldp_q")) + "falkor_ld,falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_ld_none" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_3reg,neon_load3_3reg,neon_load3_all_lanes")) + "falkor_ld,falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_ld_ld" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_3reg_q,neon_load3_3reg_q,neon_load3_all_lanes_q")) + "falkor_ld,falkor_ld,falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_ld_none_none" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_4reg,neon_load4_4reg")) + "falkor_ld,falkor_ld") + +(define_insn_reservation "falkor_ald_4_ld_ld_ld_ld" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_load1_4reg_q,neon_load4_4reg_q,neon_load4_all_lanes,neon_load4_all_lanes_q")) + "falkor_ld,falkor_ld,falkor_ld,falkor_ld") + +;; Arithmetic and Logical Instructions + +(define_insn_reservation "falkor_alu_1_xyz" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) + "falkor_xyz") + +;; SIMD Miscellaneous Instructions + +;; No separate type for ins and dup. But this is correct for both. + +(define_insn_reservation "falkor_am_3_gtov" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_from_gp")) + "falkor_gtov") + +;; No separate type for ins and dup. Assuming dup is more common. Ins is +;; gtov+vxvy and latency of 4. + +(define_insn_reservation "falkor_am_3_gtov_gtov" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_from_gp_q")) + "falkor_gtov,falkor_gtov") + +;; neon_to_gp_q is used for 32-bit ARM instructions that move 64-bits of data +;; so no use needed here. + +(define_insn_reservation "falkor_am_3_vtog" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_to_gp")) + "falkor_vtog") + +(define_insn_reservation "falkor_am_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_bsl,neon_dup,neon_ext,neon_ins,neon_ins_q,neon_move,neon_rev,neon_tbl1,neon_permute,neon_shift_imm_narrow_q")) + "falkor_vxvy") + +(define_insn_reservation "falkor_am_1_vxvy_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_bsl_q,neon_dup_q,neon_ext_q,neon_move_q,neon_rev_q,neon_tbl1_q,neon_permute_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_am_2_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_cls,neon_cnt,neon_rbit")) + "falkor_vxvy") + +(define_insn_reservation "falkor_am_4_vxvy_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_rbit_q,neon_tbl2")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_am_3_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recpe_s,neon_fp_recpe_d,neon_fp_rsqrte_s,neon_fp_rsqrte_d,neon_fp_recpx_s,neon_fp_recpx_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_am_3_vxvy_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recpe_s_q,neon_fp_recpe_d_q,neon_fp_rsqrte_s_q,neon_fp_rsqrte_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_am_5_vxvy" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recps_s")) + "falkor_vxvy") + +(define_insn_reservation "falkor_am_5_vxvy_vxvy" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recps_s_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_am_6_vxvy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recps_d,neon_fp_rsqrts_d")) + "falkor_vxvy") + +(define_insn_reservation "falkor_am_6_vxvy_vxvy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_fp_recps_d_q,neon_fp_rsqrts_d_q")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_am_5_vxvy_vxvy_vxvy" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_tbl2_q,neon_tbl3")) + "(falkor_vxvy+falkor_vxvy),falkor_vxvy") + +(define_insn_reservation "falkor_am_6_vxvy_vxvy_vxvy_vxvy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_tbl3_q,neon_tbl4")) + "(falkor_vxvy+falkor_vxvy),(falkor_vxvy+falkor_vxvy)") + +(define_insn_reservation "falkor_am_7_vxvy_vxvy_vxvy_vxvy_vxvy" 7 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_tbl4_q")) + "(falkor_vxvy+falkor_vxvy),(falkor_vxvy+falkor_vxvy),falkor_vxvy") + +;; SIMD Store Instructions + +;; ??? stp is neon_store1_2reg in aarch64.md, but neon_stp in aarch64-simd.md. +;; Similarly with ldp. + +(define_insn_reservation "falkor_ast_st_vsd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,neon_store1_one_lane,neon_store1_one_lane_q,neon_store1_2reg,neon_store2_2reg,neon_store2_one_lane,neon_store2_one_lane_q,neon_stp")) + "falkor_st+falkor_vsd") + +(define_insn_reservation "falkor_as_0_st_vsd_st_vsd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_store1_2reg_q,neon_store1_3reg,neon_store1_4reg,neon_store2_2reg_q,neon_store3_3reg,neon_store4_4reg,neon_store3_one_lane,neon_store3_one_lane_q,neon_store4_one_lane,neon_store4_one_lane_q,neon_stp_q")) + "(falkor_st+falkor_vsd),(falkor_st+falkor_vsd)") + +(define_insn_reservation "falkor_as_0_st_vsd_st_vsd_st_vsd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_store1_3reg_q,neon_store3_3reg_q")) + "(falkor_st+falkor_vsd),(falkor_st+falkor_vsd),(falkor_st+falkor_vsd)") + +(define_insn_reservation "falkor_as_0_st_vsd_st_vsd_st_vsd_st_vsd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "neon_store1_4reg_q,neon_store4_4reg_q")) + "(falkor_st+falkor_vsd),(falkor_st+falkor_vsd),(falkor_st+falkor_vsd),(falkor_st+falkor_vsd)") + +;; Branch Instructions + +(define_insn_reservation "falkor_branch_0_zb" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "branch")) + "falkor_zb") + +(define_insn_reservation "falkor_call_0_xyzb" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "call")) + "falkor_xyzb") + +;; Cryptography Extensions + +(define_insn_reservation "falkor_cry_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_sha1_fast")) + "falkor_vxvy") + +(define_insn_reservation "falkor_cry_2_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_aesmc")) + "falkor_vxvy") + +(define_insn_reservation "falkor_cry_2_vxvy_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_sha1_xor,crypto_sha256_fast,crypto_pmull")) + "falkor_vxvy+falkor_vxvy") + +(define_insn_reservation "falkor_cry_4_vy_vx" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_sha1_slow")) + "falkor_vy+falkor_vx") + +(define_insn_reservation "falkor_cry_6_vy_vx" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_sha256_slow")) + "falkor_vy+falkor_vx") + +(define_insn_reservation "falkor_cry_3_vxvy_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crypto_aese")) + "falkor_vxvy+falkor_vxvy") + +;; FP Load Instructions + +(define_insn_reservation "falkor_fld_4_ld" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_loads,f_loadd")) + "falkor_ld") + +;; No separate FP store section, these are found in the SIMD store section. + +(define_insn_reservation "falkor_fld_0_st_vsd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_stores,f_stored")) + "falkor_st+falkor_vsd") + +;; FP Data Processing Instructions + +(define_insn_reservation "falkor_fpdt_0_vxvy" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_5_vtog" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_cvtf2i")) + "falkor_vtog") + +(define_insn_reservation "falkor_fpdt_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "ffariths,ffarithd,fcsel")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_2_vxvy" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_minmaxd,f_minmaxs,f_rintd,f_rints")) + "falkor_vxvy") + +;; Scalar FP ABD is handled same as vector FP ABD. + +(define_insn_reservation "falkor_fpdt_3_vxvy" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "faddd,fadds")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_4_vxvy" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_cvt")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_5_vxvy_mul" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fmuls")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_5_vxvy_mla" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fmacs,ffmas")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_6_vxvy_mul" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fmuld")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_6_vxvy_mla" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fmacd,ffmad")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_6_vx_vy" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fdivs")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_fpdt_11_vx_vy" 11 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fdivd")) + "falkor_vx+falkor_vy") + +(define_insn_reservation "falkor_fpdt_12_vx_vy" 12 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fsqrts")) + "falkor_vxvy") + +(define_insn_reservation "falkor_fpdt_22_vx_vy" 22 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fsqrtd")) + "falkor_vxvy") + +;; FP Miscellaneous Instructions + +(define_insn_reservation "falkor_fpmsc_3_vtog" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_mrc")) + "falkor_vtog") + +(define_insn_reservation "falkor_fpmsc_3_gtov" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_mcr")) + "falkor_gtov") + +(define_insn_reservation "falkor_fpmsc_1_vxvy" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "fmov,fconsts,fconstd")) + "falkor_vxvy") + +;; No separate type for float-to-fixed conversions. Same type as +;; float-to-int conversions. They schedule the same though, so no problem. + +(define_insn_reservation "falkor_fpmsc_6_gtov" 6 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "f_cvti2f")) + "falkor_gtov") + +;; Load Instructions + +(define_insn_reservation "falkor_ld_3_ld" 3 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "load1,load2")) + "falkor_ld") + +;; Miscellaneous Data-Processing Instructions + +(define_insn_reservation "falkor_misc_1_xyz" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "bfx,bfm,extend,rotate_imm,shift_imm")) + "falkor_xyz") + +(define_insn_reservation "falkor_misc_2_x" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "crc")) + "falkor_x") + +(define_insn_reservation "falkor_misc_2_xyz" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "clz,rbit,rev")) + "falkor_xyz") + +;; Divide and Multiply Instructions + +(define_insn_reservation "falkor_muldiv_4_x_mul" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "mul")) + "falkor_x") + +(define_insn_reservation "falkor_muldiv_4_x_mla" 4 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "mla,smlal,umlal")) + "falkor_x") + +(define_insn_reservation "falkor_muldiv_5_x_mul" 5 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "smull,umull")) + "falkor_x") + +(define_insn_reservation "falkor_md_11_x_z" 11 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "sdiv,udiv")) + "falkor_x+falkor_z") + +;; Move and Shift Instructions + +(define_insn_reservation "falkor_mvs_1_xyz" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "mov_imm,shift_reg")) + "falkor_xyz") + +(define_insn_reservation "falkor_mvs_1_xyzb" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "adr")) + "falkor_xyzb") + +;; Other Instructions + +;; Block is for instruction scheduling blockage insns in RTL. There are no +;; hardware instructions emitted for them, so don't use any resources. + +(define_insn_reservation "falkor_other_0_nothing" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "no_insn,trap,block")) + "nothing") + +(define_insn_reservation "falkor_other_2_z" 2 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "mrs")) + "falkor_z") + +;; Assume multiple instructions use all pipes. + +(define_insn_reservation "falkor_extra" 1 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "multiple")) + "falkor_x+falkor_y+falkor_z+falkor_b+falkor_vx+falkor_vy+falkor_ld+falkor_st+falkor_sd+falkor_vsd+falkor_gtov+falkor_vtog") + +;; Store Instructions + +;; No use of store_rel, store3, or store4 in aarch64. + +(define_insn_reservation "falkor_st_0_st_sd" 0 + (and (eq_attr "tune" "falkor") + (eq_attr "type" "store1,store2")) + "falkor_st+falkor_sd") + +;; Muliply bypasses. + +;; 1 cycle latency (0 bubble) for an integer mul or mac feeding into a mac. + +(define_bypass 1 + "falkor_ai_4_vxvy_mul,falkor_ai_4_vxvy_mla,falkor_ai_4_vxvy_vxvy_mul,falkor_ai_4_vxvy_vxvy_mla,falkor_muldiv_4_x_mul,falkor_muldiv_4_x_mla,falkor_muldiv_5_x_mul" + "falkor_ai_4_vxvy_mla,falkor_ai_4_vxvy_vxvy_mla,falkor_muldiv_4_x_mla") + +;; 3 cycle latency (2 bubbles) for an FP mul or mac feeding into a mac. + +(define_bypass 3 + "falkor_afp_5_vxvy_mul,falkor_afp_5_vxvy_mla,falkor_afp_5_vxvy_vxvy_mul,falkor_afp_5_vxvy_vxvy_mla,falkor_afp_6_vxvy_mul,falkor_afp_6_vxvy_mla,falkor_afp_6_vxvy_vxvy_mul,falkor_afp_6_vxvy_vxvy_mla,falkor_fpdt_5_vxvy_mul,falkor_fpdt_5_vxvy_mla,falkor_fpdt_6_vxvy_mul,falkor_fpdt_6_vxvy_mla" + "falkor_afp_5_vxvy_mla,falkor_afp_5_vxvy_vxvy_mla,falkor_afp_6_vxvy_mla,falkor_afp_6_vxvy_vxvy_mla,falkor_fpdt_5_vxvy_mla,falkor_fpdt_6_vxvy_mla") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 067cef78533..cceb57525c7 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -523,6 +523,17 @@ (SI "SI") (HI "HI") (QI "QI")]) +;; Define element mode for each vector mode (lower case). +(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") + (V4HI "hi") (V8HI "hi") + (V2SI "si") (V4SI "si") + (DI "di") (V2DI "di") + (V4HF "hf") (V8HF "hf") + (V2SF "sf") (V4SF "sf") + (V2DF "df") (DF "df") + (SI "si") (HI "hi") + (QI "qi")]) + ;; 64-bit container modes the inner or scalar source mode. (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") (V4HI "V4HI") (V8HI "V4HI") diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 95d28cfa33c..11243c4ce00 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -57,11 +57,6 @@ (ior (match_operand 0 "register_operand") (match_test "op == const0_rtx")))) -(define_predicate "aarch64_reg_or_fp_float" - (ior (match_operand 0 "register_operand") - (and (match_code "const_double") - (match_test "aarch64_float_const_rtx_p (op)")))) - (define_predicate "aarch64_reg_or_fp_zero" (ior (match_operand 0 "register_operand") (and (match_code "const_double") |