diff options
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 4686 |
1 files changed, 4650 insertions, 36 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eb945484a55..27e4af12cbc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,4616 @@ +2017-07-31 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * config.gcc: Add z14. + * config/s390/driver-native.c (s390_host_detect_local_cpu): Add + CPU model numbers for z13s and z14. + * config/s390/s390-c.c (s390_resolve_overloaded_builtin): Replace + arch12 with z14. + * config/s390/s390-opts.h (enum processor_type): Rename + PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. + * config/s390/s390.c (processor_table): Add field for CPU name to + be passed to Binutils. + (s390_asm_output_machine_for_arch): Use the new field in + processor_table for Binutils. + (s390_expand_builtin): Replace arch12 with z14. + (s390_issue_rate): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. + (s390_get_sched_attrmask): Likewise. + (s390_get_unit_mask): Likewise. + * config/s390/s390.opt: Add z14 to processor_type enum. + +2017-07-31 Martin Jambor <mjambor@suse.cz> + + PR hsa/81477 + * ipa-fnsummary.c (ipa_fn_summary_generate): Set versionable + regardless of optimization level. + +2017-07-31 Jan Hubicka <hubicka@ucw.cz> + Martin Liska <mliska@suse.cz> + + * predict.def: Remove old comment and adjust probability. + * gimplify.c (should_warn_for_implicit_fallthrough): Ignore + PREDICT statements. + +2017-07-31 Uros Bizjak <ubizjak@gmail.com> + + PR target/25967 + * config/i386/i386.c (ix86_function_naked): New function. + (ix86_can_use_return_insn_p): Return false for naked functions. + (ix86_expand_prologue): Skip prologue for naked functions. + (ix86_expand_epilogue): Skip epilogue for naked functions + and emit trap instruction. + (ix86_warn_func_return): New function. + (ix86_attribute_table): Add "naked" attribute specification. + (TARGET_WARN_FUNC_RETURN): Define. + * doc/extend.texi (x86 Function Attributes) <naked>: Document it. + +2017-07-31 Martin Liska <mliska@suse.cz> + + * gimple-pretty-print.c (dump_gimple_label): Never dump BB info. + (dump_gimple_bb_header): Always dump BB info. + (pp_cfg_jump): Do not append info about BB when dumping a jump. + +2017-07-31 Martin Liska <mliska@suse.cz> + + PR sanitize/81530 + * convert.c (convert_to_integer_1): Guard condition with flag_sanitize_p + also with current_function_decl non-null equality. + +2017-07-31 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/81604 + * ubsan.c (ubsan_type_descriptor): For UBSAN_PRINT_ARRAY don't + change type to the element type, instead add eltype variable and + use it where we are interested in the element type. + + PR tree-optimization/81603 + * ipa-polymorphic-call.c + (ipa_polymorphic_call_context::ipa_polymorphic_call_context): Perform + offset arithmetic in offset_int, bail out if the resulting bit offset + doesn't fit into shwi. + +2017-07-31 Martin Liska <mliska@suse.cz> + + * gimplify.c (mostly_copy_tree_r): Remove Java specific hunk. + (gimplify_save_expr): Fix comment. + +2017-07-30 H.J. Lu <hongjiu.lu@intel.com> + + PR target/79793 + * config/i386/i386.c (ix86_function_arg): Update arguments for + exception handler. + (ix86_compute_frame_layout): Set the initial stack offset to + INCOMING_FRAME_SP_OFFSET. Update red-zone offset with + INCOMING_FRAME_SP_OFFSET. + (ix86_expand_epilogue): Don't pop the 'ERROR_CODE' off the + stack before exception handler returns. + * config/i386/i386.h (INCOMING_FRAME_SP_OFFSET): Add the + the 'ERROR_CODE' for exception handler. + +2017-07-30 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.h (ASM_PRINTF_EXTENSIONS): New macro. + (ASM_OUTPUT_REG_PUSH): Rewrite with new operand modifiers. + (ASM_OUTPUT_REG_POP): Ditto. + * config/i386/i386.c (ix86_asm_output_function_label): Use fputs + instead of asm_fprintf to output pure string. + +2017-07-29 Jakub Jelinek <jakub@redhat.com> + + * debug.h (struct gcc_debug_hooks): Add IMPLICIT argument + to imported_module_or_decl hook. + (debug_nothing_tree_tree_tree_bool): Remove. + (debug_nothing_tree_tree_tree_bool_bool): New declaration. + * debug.c (do_nothing_debug_hooks): Use + debug_nothing_tree_tree_tree_bool_bool instead of + debug_nothing_tree_tree_tree_bool. + * vmsdbgout.c (vmsdbg_debug_hooks): Likewise. + * dbxout.c (dbx_debug_hooks, xcoff_debug_hooks): Likewise. + * sdbout.c (sdb_debug_hooks): Likewise. + * dwarf2out.c (dwarf2_lineno_debug_hooks): Likewise. + (gen_namespace_die): Add DW_AT_export_symbols attribute if + langhook wants it. + (dwarf2out_imported_module_or_decl): Add IMPLICIT argument, + if true, -gdwarf-5 and decl will have DW_AT_export_symbols + attribute, don't add anything. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * fold-const.c (fold_build1_stat_loc): Remove _stat from name. + (fold_build2_stat_loc): Likewise. + (fold_build3_stat_loc): Likewise. + * fold-const.h (fold_build1, fold_build2, fold_build3): Adjust. + (fold_build1_loc): Remove macro. + (fold_build2_loc): Likewise. + (fold_build3_loc): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * gimple.c (gimple_build_debug_bind_stat): Remove _stat from name. + (gimple_build_debug_bind_source_stat): Likewise. + * gimple.h (gimple_build_debug_bind): Remove macro. + (gimple_build_debug_bind_source): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * bitmap.c (bitmap_alloc): Adjust. + (bitmap_gc_alloc): Likewise. + * bitmap.h (bitmap_initialize_stat): Remove _stat from name. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * bitmap.c (bitmap_obstack_alloc_stat): Rename to bitmap_alloc. + (bitmap_gc_alloc_stat): Rename to bitmap_gc_alloc. + * bitmap.h (bitmap_obstack_alloc_stat): Adjust prototype. + (bitmap_gc_alloc_stat): Likewise. + (BITMAP_ALLOC, BITMAP_GGC_ALLOC): Adjust. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * rtl.c (shallow_copy_rtx_stat): Remove _stat from name. + * rtl.h (shallow_copy_rtx): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * emit-rtl.c (gen_raw_REG): Adjust. + * gengenrtl.c (gendef): Likewise. + * rtl.c (rtx_alloc_stat): Remove _stat from name. + * rtl.h (rtx_alloc): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (build_tree_list_vec_stat): Remove _stat from name. + (build_tree_list_stat): Likewise. + * tree.h (build_tree_list): Remove macro. + (build_tree_list_vec): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (make_vector_stat): Remove _stat from name. + (build_vector_stat): Likewise. + * tree.h (make_vector_stat): Remove macro. + (build_vector_stat): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.h (build_var_debug_value): Remove prototype. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (tree_cons_stat): Remove _stat from name. + * tree.h (tree_cons): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (build_vl_exp_stat): Remove _stat from name. + * tree.h (build_vl_exp): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (build_decl_stat): Remove _stat from name. + * tree.h (build_decl): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * gimple.c (gimple_build_with_ops_stat): Adjust. + (gimple_alloc_stat): Remove _stat from name. + * gimple.h (gimple_alloc): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (make_tree_vec_stat): Remove _stat from name. + (grow_tree_vec_stat): Likewise. + * tree.h (make_tree_vec_stat): Adjust prototype. + (grow_tree_vec_stat): Likewise. + (make_tree_vec): Remove macro. + (grow_tree_vec): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * fold-const.c (fold_build1_stat_loc): Adjust. + (fold_build2_stat_loc): Likewise. + (fold_build3_stat_loc): Likewise. + * tree.c (build0_stat): Remove _stat from name. + (build1_stat): Likewise. + (build2_stat): Likewise. + (build3_stat): Likewise. + (build4_stat): Likewise. + (build5_stat): Likewise. + * tree.h (build1_loc): Remove macro, and rename _stat function + to this. + (build2_loc): Likewise. + (build3_loc): Likewise. + (build4_loc): Likewise. + (build5_loc): Likewise. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (make_int_cst_stat): Remove _stat from name. + * tree.h (make_int_cst_stat): Adjust prototype. + (make_int_cst): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (make_tre_binfo_stat): Remove _stat from name. + * tree.h (make_tree_binfo_stat): Adjust prototype. + (make_tree_binfo): Remove. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (copy_node_stat): Rename to copy_node. + (build_distinct_type_copy): Adjust. + * tree.h (copy_node_stat): Adjust prototype. + (copy_node): Remove macro. + +2017-07-28 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> + + * tree.c (make_node_stat): rename to make_node. + (build_tree_list_stat): Adjust. + (build0_stat): Likewise. + (build2_stat): Likewise. + (build3_stat): Likewise. + (build4_stat): Likewise. + (build5_stat): Likewise. + (build_decl_stat): Likewise. + * tree.h (make_node_stat): Adjust prototype. + (make_node): remove macro. + +2017-07-28 Peter Bergner <bergner@vnet.ibm.com> + + * config/rs6000/ppc-auxv.h (PPC_FEATURE2_DARN): New define. + (PPC_FEATURE2_SCV): Likewise. + * config/rs6000/rs6000.c (cpu_supports_info): Use them. + +2017-07-28 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.c + (aarch64_internal_mov_immediate): Add new special pattern. + * config/aarch64/aarch64.md (*movdi_aarch64): + Add reg/32bit const mov case. + +2017-07-28 Tamar Christina <tamar.christina@arm.com> + Richard Sandiford <richard.sandiford@linaro.org> + + * config/aarch64/aarch64.md (mov<mode>): Generalize. + (*movhf_aarch64, *movsf_aarch64, *movdf_aarch64): + Add integer and movi cases. + (movi-split-hf-df-sf split, fp16): New. + (enabled): Added TARGET_FP_F16INST. + * config/aarch64/iterators.md (GPF_HF): New. + * config/aarch64/predicates.md (aarch64_reg_or_fp_float): New. + +2017-07-28 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.c + (aarch64_simd_container_mode): Add prototype. + (aarch64_expand_mov_immediate): Add HI support. + (aarch64_reinterpret_float_as_int, aarch64_float_const_rtx_p: New. + (aarch64_can_const_movi_rtx_p): New. + (aarch64_preferred_reload_class): + Remove restrictions of using FP registers for certain SIMD operations. + (aarch64_rtx_costs): Added new cost for CONST_DOUBLE moves. + (aarch64_valid_floating_const): Add integer move validation. + (aarch64_simd_imm_scalar_p): Remove. + (aarch64_output_scalar_simd_mov_immediate): Generalize function. + (aarch64_legitimate_constant_p): Expand list of supported cases. + * config/aarch64/aarch64-protos.h + (aarch64_float_const_rtx_p, aarch64_can_const_movi_rtx_p): New. + (aarch64_reinterpret_float_as_int): New. + (aarch64_simd_imm_scalar_p): Remove. + * config/aarch64/constraints.md (Uvi): New. + (Dd): Split into Ds and new Dd. + * config/aarch64/aarch64.md (*movsi_aarch64): + Add SIMD mov case. + (*movdi_aarch64): Add SIMD mov case. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c: (struct chain): Handle store-store chain in which + stores for elimination only store loop invariant values. + (execute_pred_commoning_chain): Ditto. + (prepare_initializers_chain_store_elim): Ditto. + (prepare_finalizers): Ditto. + (is_inv_store_elimination_chain): New function. + (initialize_root_vars_store_elim_1): New function. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c: Revise general description of the pass. + (enum chain_type): New enum type for store elimination. + (struct chain): New field supporting store elimination. + (struct component): Ditto. + (dump_chain): Dump store-stores chain. + (release_chain): Release resources. + (split_data_refs_to_components): Compute and create component + contains only stores for elimination. + (get_chain_last_ref_at): New function. + (make_invariant_chain): Initialization. + (make_rooted_chain): Specify chain type in parameter and record it. + (add_looparound_copies): Skip for store-stores chain. + (determine_roots_comp): Compute type of chain and pass it to + make_rooted_chain. + (initialize_root_vars_store_elim_2): New function. + (finalize_eliminated_stores): New function. + (remove_stmt): Handle store for elimination. + (execute_pred_commoning_chain): Execute predictive commoning on + store-store chains. + (determine_unroll_factor): Skip unroll for store-stores chain. + (prepare_initializers_chain_store_elim): New function. + (prepare_initializers_chain): Hanlde store-store chain. + (prepare_finalizers_chain, prepare_finalizers): New function. + (tree_predictive_commoning_loop): Return integer value indicating + if loop is unrolled or lcssa form is corrupted. + (tree_predictive_commoning): Rewrite for lcssa form if necessary. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c (initialize_root): Delete. + (execute_pred_commoning_chain): Initialize root vars and replace + reference of non-combined chain directly, rather than call above + function. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c (ref_at_iteration): Add parameter NITERS. Compute + memory reference to DR at (NITERS + ITERS)-th iteration of loop. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c (struct chain): New field init_seq. + (release_chain): Release init_seq. + (prepare_initializers_chain): Record intialization stmts in above + field. + (insert_init_seqs): New function. + (tree_predictive_commoning_loop): Call insert_init_seqs. + +2017-07-28 Bin Cheng <bin.cheng@arm.com> + + * tree-predcom.c (determine_roots_comp): Skip trivial components. + +2017-07-28 Richard Biener <rguenther@suse.de> + + * match.pd: Remove superfluous :c. + * genmatch.c (simplify::id): Add member. + (lower_commutative, lower_opt_convert, lower_cond, lower_for): + Copy id. + (current_id): New global. + (dt_node::parent): Move from ... + (dt_operand::parent): ... here. Add for_id member. + (is_a_helper <dt_operand *>::test): DT_TRUE is also a dt_operand. + (decision_tree::find_node): Relax order requirement when + merging DT_TRUE nodes to ones inbetween the current simplify + and the one we try to merge with. Add diagnostic whenever + we need to enforce pattern order by not merging. + (decision_tree::insert): Set current_id. + (decision_tree::print_node): Dump parent node and for_id. + (parser::last_id): Add member. + (parser::push_simplify): Assign unique id. + (parser::parser): Initialize last_id. + +2017-07-28 Martin Liska <mliska@suse.cz> + + PR sanitizer/81340 + * sanopt.c (sanitize_rewrite_addressable_params): Set VALUE_EXPR after + gimple_build_debug_bind. + +2017-07-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81502 + * match.pd: Add pattern combining BIT_INSERT_EXPR with + BIT_FIELD_REF. + * tree-cfg.c (verify_expr): Verify types of BIT_FIELD_REF + size/pos operands. + (verify_gimple_assign_ternary): Likewise for BIT_INSERT_EXPR pos. + * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Use bitsizetype + for BIT_FIELD_REF args. + * fold-const.c (make_bit_field_ref): Likewise. + * tree-vect-stmts.c (vectorizable_simd_clone_call): Likewise. + +2017-07-28 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/80998 + * sanopt.c (pass_sanopt::execute): Handle IFN_UBSAN_PTR. + * tree-ssa-alias.c (call_may_clobber_ref_p_1): Likewise. + * flag-types.h (enum sanitize_code): Add SANITIZER_POINTER_OVERFLOW. + Or it into SANITIZER_UNDEFINED. + * ubsan.c: Include gimple-fold.h and varasm.h. + (ubsan_expand_ptr_ifn): New function. + (instrument_pointer_overflow): New function. + (maybe_instrument_pointer_overflow): New function. + (instrument_object_size): Formatting fix. + (pass_ubsan::execute): Call instrument_pointer_overflow + and maybe_instrument_pointer_overflow. + * internal-fn.c (expand_UBSAN_PTR): New function. + * ubsan.h (ubsan_expand_ptr_ifn): Declare. + * sanitizer.def (__ubsan_handle_pointer_overflow, + __ubsan_handle_pointer_overflow_abort): New builtins. + * tree-ssa-tail-merge.c (merge_stmts_p): Handle IFN_UBSAN_PTR. + * internal-fn.def (UBSAN_PTR): New internal function. + * opts.c (sanitizer_opts): Add pointer-overflow. + * lto-streamer-in.c (input_function): Handle IFN_UBSAN_PTR. + * fold-const.c (build_range_check): Compute pointer range check in + integral type if pointer arithmetics would be needed. Formatting + fixes. + +2017-07-28 Martin Liska <mliska@suse.cz> + + PR sanitizer/81460 + * sanopt.c (sanitize_rewrite_addressable_params): Do not rewrite + parameters that are of a variable-length. + +2017-07-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config.gcc (powerpc-*-rtems*): Remove rs6000/eabi.h. Add + rs6000/biarch64.h. + * config/rs6000/rtems.h (ASM_DECLARE_FUNCTION_SIZE): New macro. + (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise. + (CRT_CALL_STATIC_FUNCTION): Likewise. + (ASM_DEFAULT_SPEC): New define. + (ASM_SPEC32): Likewise. + (ASM_SPEC64): Likewise. + (ASM_SPEC_COMMON): Likewise. + (ASM_SPEC): Likewise. + (INVALID_64BIT): Likewise. + (LINK_OS_DEFAULT_SPEC): Likewise. + (LINK_OS_SPEC32): Likewise. + (LINK_OS_SPEC64): Likewise. + (POWERPC_LINUX): Likewise. + (PTRDIFF_TYPE): Likewise. + (RESTORE_FP_PREFIX): Likewise. + (RESTORE_FP_SUFFIX): Likewise. + (SAVE_FP_PREFIX): Likewise. + (SAVE_FP_SUFFIX): Likewise. + (SIZE_TYPE): Likewise. + (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. + (TARGET_64BIT): Likewise. + (TARGET_64BIT): Likewise. + (TARGET_AIX): Likewise. + (WCHAR_TYPE_SIZE): Likewise. + (WCHAR_TYPE): Undefine. + (TARGET_OS_CPP_BUILTINS): Add 64-bit PowerPC defines. + (CPP_OS_DEFAULT_SPEC): Use previous CPP_OS_RTEMS_SPEC. + (CPP_OS_RTEMS_SPEC): Delete. + (SUBSUBTARGET_EXTRA_SPECS): Remove cpp_os_rtems. Add + asm_spec_common, asm_spec32, asm_spec64, link_os_spec32, and + link_os_spec64. + * config/rs6000/t-rtems: Add mcpu=e6500/m64 multilibs. + +2017-07-28 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81578 + * tree-parloops.c (build_new_reduction): Bail out if + reduction_code isn't one of the standard OpenMP reductions. + Move the details printing after that decision. + +2017-07-27 Peter Bergner <bergner@vnet.ibm.com> + + * config/rs6000/predicates.md (volatile_mem_operand): Remove code + related to reload_in_progress. + (splat_input_operand): Likewise. + * config/rs6000/rs6000-protos.h (rs6000_secondary_memory_needed_rtx): + Delete prototype. + * config/rs6000/rs6000.c (machine_function): Remove sdmode_stack_slot + field. + (TARGET_EXPAND_TO_RTL_HOOK): Delete. + (TARGET_INSTANTIATE_DECLS): Likewise. + (legitimate_indexed_address_p): Delete reload_in_progress code. + (rs6000_debug_legitimate_address_p): Likewise. + (rs6000_eliminate_indexed_memrefs): Likewise. + (rs6000_emit_le_vsx_store): Likewise. + (rs6000_emit_move_si_sf_subreg): Likewise. + (rs6000_emit_move): Likewise. + (register_to_reg_type): Likewise. + (rs6000_pre_atomic_barrier): Likewise. + (rs6000_machopic_legitimize_pic_address): Likewise. + (rs6000_allocate_stack_temp): Likewise. + (rs6000_address_for_fpconvert): Likewise. + (rs6000_address_for_altivec): Likewise. + (rs6000_secondary_memory_needed_rtx): Delete function. + (rs6000_check_sdmode): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_instantiate_decls): Likewise. + * config/rs6000/rs6000.h (SECONDARY_MEMORY_NEEDED_RTX): Delete. + * config/rs6000/rs6000.md (splitter for *movsi_got_internal): + Delete reload_in_progress. + (*vec_reload_and_plus_<mptrsize>): Likewise. + * config/rs6000/vsx.md (vsx_mul_v2di): Likewise. + (vsx_div_v2di): Likewise. + (vsx_udiv_v2di): Likewise. + +2017-07-27 Peter Bergner <bergner@vnet.ibm.com> + + * config/rs6000/rs6000.opt (mlra): Replace with stub. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete OPTION_MASK_LRA. + * config/rs6000/rs6000.c (TARGET_LRA_P): Delete. + (rs6000_debug_reg_global): Delete print of LRA status. + (rs6000_option_override_internal): Delete dead LRA related code. + (rs6000_lra_p): Delete function. + * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mlra. + +2017-07-27 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*). + * config/riscv/rtems.h: New file. + +2017-07-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + Sudakshina Das <sudi.das@arm.com> + + * config/aarch64/aarch64.md + (define_split for and<mode>3nr_compare): Move + non aarch64_logical_operand to a register. + (define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non + register immediate operand to a register. + * config/aarch64/predicates.md (aarch64_mov_imm_operand): New. + +2017-07-27 Peter Bergner <bergner@vnet.ibm.com> + + PR middle-end/81564 + * tree-cfg.c (group_case_labels_stmt): Handle already deleted blocks. + +2017-07-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81573 + PR tree-optimization/81494 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Handle + multi defuse cycle case. + +2017-07-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81571 + * tree-vect-slp.c (vect_build_slp_tree): Properly verify reduction + PHIs. + +2017-07-27 Eric Botcazou <ebotcazou@adacore.com> + + * config/sparc/sparc.c (sparc_option_override): Set MASK_FSMULD flag + earlier and only if MASK_FPU is set. Adjust formatting. + +2017-07-27 Martin Liska <mliska@suse.cz> + + * opt-functions.awk: Add validation of value of Init. + * optc-gen.awk: Pass new argument. + +2017-07-27 Martin Liska <mliska@suse.cz> + + * auto-profile.c (autofdo_source_profile::update_inlined_ind_target): + Fix wrong condition. + +2017-07-27 Martin Liska <mliska@suse.cz> + + * auto-profile.c (afdo_annotate_cfg): Assign zero counts to + BBs and edges seen by autoFDO. + +2017-07-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81502 + * tree-ssa.c (non_rewritable_lvalue_p): Handle BIT_INSERT_EXPR + with incompatible but same sized type. + (execute_update_addresses_taken): Likewise. + +2017-07-27 James Greenhalgh <james.greenhalgh@arm.com> + + * tree-ssa-loop-ch.c (pass_ch::process_loop_p): Guard on + flag_tree_loop_vectorize rather than flag_tree_vectorize. + +2017-07-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + PR target/81534 + * config/s390/s390.md ("*atomic_compare_and_swap<mode>_1") + ("*atomic_compare_and_swapdi_2", "*atomic_compare_and_swapsi_3"): + Change s_operand to memory_operand. + +2017-07-27 Richard Sandiford <richard.sandiford@linaro.org> + + * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_permute): Declare. + * config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Replace with... + (rs6000_emit_le_vsx_permute): ...this. Take the destination as input. + Emit instructions rather than returning an expression. Handle TFmode + and KFmode by casting to TImode. + (rs6000_emit_le_vsx_load): Update to use rs6000_emit_le_vsx_permute. + (rs6000_emit_le_vsx_store): Likewise. + * config/rs6000/vsx.md (VSX_TI): New iterator. + (*vsx_le_permute_<mode>): Use it instead of VSX_LE_128. + (*vsx_le_undo_permute_<mode>): Likewise. + (*vsx_le_perm_load_<mode>): Use rs6000_emit_le_vsx_permute to + emit the split sequence. + (*vsx_le_perm_store_<mode>): Likewise. + +2017-07-27 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81555 + PR tree-optimization/81556 + * tree-ssa-reassoc.c (rewrite_expr_tree): Add NEXT_CHANGED argument, + if true, force CHANGED for the recursive invocation. + (reassociate_bb): Remember original length of ops array, pass + len != orig_len as NEXT_CHANGED in rewrite_expr_tree call. + + * attribs.c (decl_attributes): Imply noinline, noclone and no_icf + attributes for noipa attribute. For naked attribute use + lookup_attribute first before lookup_attribute_spec. + * final.c (rest_of_handle_final): Disable IPA RA for functions with + noipa attribute. + * ipa-visibility.c (non_local_p): Fix comment typos. Return true + for functions with noipa attribute. + (cgraph_externally_visible_p): Return true for functions with noipa + attribute. + * cgraph.c (cgraph_node::get_availability): Return AVAIL_INTERPOSABLE + for functions with noipa attribute. + * doc/extend.texi: Document noipa function attribute. + * tree-ssa-structalias.c (refered_from_nonlocal_fn): Set *nonlocal_p + also for functions with noipa attribute. + (ipa_pta_execute): Set nonlocal_p also for nodes with noipa attribute. + +2017-07-26 Andrew Pinski <apinski@cavium.com> + + * config/aarch64/aarch64.c (thunderx_vector_cost): Decrease cost of + vec_unalign_load_cost and vec_unalign_store_cost. + +2017-07-26 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete + -mvsx-small-integer option. + (ISA_3_0_MASKS_IEEE): Likewise. + (OTHER_VSX_VECTOR_MASKS): Likewise. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise. + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify + code, only testing for DImode being allowed in non-VSX floating + point registers. + (rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER + to TARGET_P8_VECTOR test. Remove redundant VSX test inside of + another VSX test. + (rs6000_option_override_internal): Delete -mvsx-small-integer. + (rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to + TARGET_P8_VECTOR test. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER, + since TARGET_P9_VECTOR was already tested. + (rs6000_opt_masks): Remove -mvsx-small-integer. + * config/rs6000/vsx.md (vsx_extract_<mode>): Delete + TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was + used. + (vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a + test for TARGET_VEXTRACTUB was used, and that uses + TARGET_P9_VECTOR. + (p9 extract splitter): Likewise. + (vsx_extract_<mode>_di_p9): Likewise. + (vsx_extract_<mode>_store_p9): Likewise. + (vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test + for TARGET_P9_VECTOR was used. Delete code that is now dead with + the elimination of TARGET_VSX_SMALL_INTEGER. + (vsx_extract_<mode>_p8): Likewise. + (vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise. + (vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise. + (vsx_set_<mode>_p9): Likewise. + (vsx_set_v4sf_p9): Likewise. + (vsx_set_v4sf_p9_zero): Likewise. + (vsx_insert_extract_v4sf_p9): Likewise. + (vsx_insert_extract_v4sf_p9_2): Likewise. + * config/rs6000/rs6000.md (sign extend splitter): Change + TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. + (floatsi<mode>2_lfiwax_mem): Likewise. + (floatunssi<mode>2_lfiwzx_mem): Likewise. + (float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER, + since a test for TARGET_P9_VECTOR was used. + (float<QHI:mode><FP_ISA3:mode>2_internal): Likewise. + (floatuns<QHI:mode><FP_ISA3:mode>2): Likewise. + (floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise. + (fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to + TARGET_P8_VECTOR test. + (fix_trunc<mode>si2_stfiwx): Likewise. + (fix_trunc<mode>si2_internal): Likewise. + (fix_trunc<SFDF:mode><QHI:mode>2): Delete + TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was + used. + (fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise. + (fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to + TARGET_P8_VECTOR test. + (fixuns_trunc<mode>si2_stfiwx): Likewise. + (fixuns_trunc<SFDF:mode><QHI:mode>2): Delete + TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was + used. + (fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise. + (fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER, + since a test for TARGET_P9_VECTOR was used. + (splitter for loading small constants): Likewise. + +2017-07-26 Andrew Pinski <apinski@cavium.com> + + * config/aarch64/aarch64.c (thunderx_vector_cost): Fix + vec_fp_stmt_cost. + +2017-07-26 H.J. Lu <hongjiu.lu@intel.com> + + PR target/81563 + * config/i386/i386.c (sp_valid_at): Properly check CFA offset. + (fp_valid_at): Likewise. + +2017-07-26 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64.c (cortexa57_addrcost_table): Remove. + (qdf24xx_addrcost_table): Likewise. + (cortexa57_tunings): Update to use generic_branch_cost. + (cortexa72_tunings): Likewise. + (cortexa73_tunings): Likewise. + (qdf24xx_tunings): Likewise. + +2017-07-26 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64.c (cortexa57_branch_cost): Remove. + (thunderx2t99_branch_cost): Likewise. + (cortexa35_tunings): Update to use generic_branch_cost. + (cortexa53_tunings): Likewise. + (cortexa57_tunings): Likewise. + (cortexa72_tunings): Likewise. + (cortexa73_tunings): Likewise. + (thunderx2t99_tunings): Likewise. + +2017-07-26 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD. + (sparc_option_override): Honour MASK_FSMULD. + * config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD. + * config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD. + * config/sparc/sparc.opt (mfsmuld): New option. + * doc/invoke.texi (mfsmuld): Document option. + +2017-07-26 Marek Polacek <polacek@redhat.com> + + PR middle-end/70992 + * tree.c (build2_stat): Don't set TREE_CONSTANT on divisions by zero. + +2017-07-26 Richard Biener <rguenther@suse.de> + + * gimple-match-head.c (do_valueize): Return OP if valueize + returns NULL_TREE. + (get_def): New helper to get at the def stmt of a SSA name + if valueize allows. + * genmatch.c (dt_node::gen_kids_1): Use get_def instead of + do_valueize to get at the def stmt. + (dt_operand::gen_gimple_expr): Simplify do_valueize calls. + +2017-07-26 Wilco Dijkstra <wdijkstr@arm.com> + + PR middle-end/46932 + * auto-inc-dec.c (parse_add_or_inc): Block autoinc on sfp. + +2017-07-26 Martin Liska <mliska@suse.cz> + + PR sanitize/81186 + * function.c (expand_function_start): Make expansion of + nonlocal_goto_save_area after parm_birth_insn. + +2017-07-26 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/sparc/sparc.c (sparc_option_override): Remove MASK_FPU + from all CPU target flags enable members. + +2017-07-26 Richard Biener <rguenther@suse.de> + + * genmatch.c (dt_simplify::gen): Make iterator vars const. + (decision_tree::gen): Make 'type' const. + (write_predicate): Likewise. + +2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): + Eliminate TARGET_UPPER_REGS_{DF,DI,SF} usage. + (rs6000_option_override_internal): Likewise. + (rs6000_expand_vector_set): Likewise. + * config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Delete. + (TARGET_UPPER_REGS_SF): Likewise. + (TARGET_UPPER_REGS_DI): Likewise. + (TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_{DF,DI,SF}. + (TARGET_DIRECT_MOVE_64BIT): Likewise. + * config/rs6000/rs6000.md (ALTIVEC_DFORM): Likewise. + (float<QHI:mode><FP_ISA3:mode>2_internal): Likewise. + (Splitters for DI constants in Altivec registers): Likewise. + * config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise. + (vsx_set_v4sf_p9): Likewise. + (vsx_set_v4sf_p9_zero): Likewise. + (vsx_insert_extract_v4sf_p9): Likewise. + (vsx_insert_extract_v4sf_p9_2): Likewise. + +2017-07-25 Carl Love <cel@us.ibm.com> + + * doc/extend.texi: Update the built-in documentation file for the + existing built-in functions + vector signed char vec_cnttz (vector signed char); + vector unsigned char vec_cnttz (vector unsigned char); + vector signed short vec_cnttz (vector signed short); + vector unsigned short vec_cnttz (vector unsigned short); + vector signed int vec_cnttz (vector signed int); + vector unsigned int vec_cnttz (vector unsigned int); + vector signed long long vec_cnttz (vector signed long long); + vector unsigned long long vec_cnttz (vector unsigned long long); + +2017-07-25 Andrew Pinski <apinski@cavium.com> + + * tree-ssa-uninit.c (warn_uninitialized_vars): Don't warn about memory + accesses where the use is for the first operand of a BIT_INSERT. + +2017-07-25 Jim Wilson <jim.wilson@linaro.org> + + PR bootstrap/81521 + * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look + for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. + +2017-07-25 Jim Wilson <jim.wilson@linaro.org> + + * config/i386/gstabs.h: Delete. + * config/i386/openbsd.h, config/i386/t-openbsd: Likewise. + +2017-07-25 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_decompose_address): Do not check for + register RTX when looking at index_reg or base_reg. + * config/i386/i386.h (INCOMING_RETURN_ADDR_RTX): Use stack_pointer_rtx. + +2017-07-25 Eric Botcazou <ebotcazou@adacore.com> + + * gimple.c (gimple_assign_set_rhs_with_ops): Do not ask gsi_replace + to update EH info here. + +2017-07-25 Alexander Monakov <amonakov@ispras.ru> + + * match.pd ((X * CST1) * CST2): Simplify to X * (CST1 * CST2). + +2017-07-25 Alexander Monakov <amonakov@ispras.ru> + + * match.pd ((X * CST) * Y): Reassociate to (X * Y) * CST. + +2017-07-25 Torsten Duwe <duwe@suse.de> + + * common.opt: Introduce -fpatchable-function-entry + command line option, and its variables function_entry_patch_area_size + and function_entry_patch_area_start. + * opts.c (common_handle_option): Add -fpatchable_function_entry_ case, + including a two-value parser. + * target.def (print_patchable_function_entry): New target hook. + * targhooks.h (default_print_patchable_function_entry): New function. + * targhooks.c (default_print_patchable_function_entry): Likewise. + * toplev.c (process_options): Switch off IPA-RA if + patchable function entries are being generated. + * varasm.c (assemble_start_function): Look at the + patchable-function-entry command line switch and current + function attributes and maybe generate NOP instructions by + calling the print_patchable_function_entry hook. + * doc/extend.texi: Document patchable_function_entry attribute. + * doc/invoke.texi: Document -fpatchable_function_entry + command line option. + * doc/tm.texi.in (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): + New target hook. + * doc/tm.texi: Re-generate. + +2017-07-25 Jakub Jelinek <jakub@redhat.com> + + PR target/81532 + * config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for + TARGET_AVX512DQ rather than TARGET_AVX512BW. + +2017-07-25 Tamar Christina <tamar.christina@arm.com> + + * config/arm/parsecpu.awk (all_cores): Remove duplicates. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81455 + * tree-ssa-loop-unswitch.c (find_loop_guard): Make sure to + not walk in cycles when looking for guards. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81529 + * tree-vect-stmts.c (process_use): Disregard live induction PHIs + when optimizing backedge uses. + +2017-07-25 David Edelsohn <dje.gcc@gmail.com> + + * dwarf2asm.c (dw2_asm_output_nstring): Encode double quote + character for AIX. + * dwarf2out.c (output_macinfo): Copy debug_line_section_label + to dl_section_ref. On AIX, append an expression to subtract + the size of the section length to dl_section_ref. + +2017-07-25 Segher Boessenkool <segher@kernel.crashing.org> + + * configure.ac: If any of the config.* scripts fail, exit 1. + * configure: Regenerate. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR middle-end/81546 + * tree-ssa-operands.c (verify_imm_links): Remove cap on number + of immediate uses, be more verbose on errors. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81510 + * tree-vect-loop.c (vect_is_simple_reduction): When the + reduction stmt is not inside the loop bail out. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81303 + * tree-vect-loop-manip.c (vect_loop_versioning): Build + profitability check against LOOP_VINFO_NITERSM1. + +2017-07-25 Alexander Monakov <amonakov@ispras.ru> + + * domwalk.c (cmp_bb_postorder): Simplify. + (sort_bbs_postorder): New function. Use it... + (dom_walker::walk): ...here to optimize common cases. + +2017-07-25 Martin Liska <mliska@suse.cz> + + PR ipa/81520 + * ipa-visibility.c (function_and_variable_visibility): Make the + redirection just on target that supports aliasing. + Fix GNU coding style. + +2017-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de> + + PR libgcc/61152 + * config/aarch64/rtems.h: Add GCC Runtime Library Exception. + Format changes. + * config/arm/rtems.h: Likewise. + * config/bfin/rtems.h: Likewise. + * config/i386/rtemself.h: Likewise. + * config/lm32/rtems.h: Likewise. + * config/m32c/rtems.h: Likewise. + * config/m68k/rtemself.h: Likewise. + * config/microblaze/rtems.h: Likewise. + * config/mips/rtems.h: Likewise. + * config/moxie/rtems.h: Likewise. + * config/nios2/rtems.h: Likewise. + * config/powerpcspe/rtems.h: Likewise. + * config/rs6000/rtems.h: Likewise. + * config/rtems.h: Likewise. + * config/sh/rtems.h: Likewise. + * config/sh/rtemself.h: Likewise. + * config/sparc/rtemself.h: Likewise. + +2017-07-25 Georg-Johann Lay <avr@gjlay.de> + + PR 81487 + * hsa-brig.c (brig_init): Use xasprintf instead of asprintf. + * gimple-pretty-print.c (dump_profile, dump_probability): Same. + * tree-ssa-structalias.c (alias_get_name): Same. + +2017-07-25 Bin Cheng <bin.cheng@arm.com> + + PR target/81414 + * config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac + instructions if no du chain is found. + +2017-07-25 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr-log.c (avr_log_vadump) ['T']: Print NULL-TREE. + +2017-07-25 Richard Biener <rguenther@suse.de> + + PR middle-end/81505 + * fold-const.c (fold_negate_const): TREE_OVERFLOW should be + sticky. + +2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete + upper-regs options. + (ISA_2_7_MASKS_SERVER): Likewise. + (ISA_3_0_MASKS_IEEE): Likewise. + (OTHER_P8_VECTOR_MASKS): Likewise. + (OTHER_VSX_VECTOR_MASKS): Likewise. + (POWERPC_MASKS): Likewise. + (power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a + duplicate list of options. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove + explicit -mupper-regs options. + * config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete + -mupper-regs* options. Delete -mvsx-scalar-memory, which was an + alias for -mupper-regs-df. + * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs + options in terms of whether -mvsx or -mpower8-vector was used. + (TARGET_UPPER_REGS_DI): Likewise. + (TARGET_UPPER_REGS_SF): Likewise. + * doc/invoke.texi (RS/6000 and PowerPC Options): Delete the + -mupper-regs-* options. + +2017-07-24 Segher Boessenkool <segher@kernel.crashing.org> + + * passes.c (emergency_dump_function): Print some empty lines and a + header before the RTL dump. + +2017-07-24 Segher Boessenkool <segher@kernel.crashing.org> + + * cfgrtl.c (rtl_dump_bb): Don't call NEXT_INSN on NULL. + +2017-07-24 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/79041 + * config/aarch64/aarch64.c (aarch64_classify_symbol): + Avoid SYMBOL_SMALL_ABSOLUTE for literals with pc-relative literals. + +2017-07-24 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for built-in functions + vector float vec_extract_fp32_from_shorth (vector unsigned short); + vector float vec_extract_fp32_from_shortl (vector unsigned short); + * config/rs6000/altivec.h (vec_extract_fp_from_shorth, + vec_extract_fp_from_shortl): Add defines for the two builtins. + * config/rs6000/rs6000-builtin.def (VEXTRACT_FP_FROM_SHORTH, + VEXTRACT_FP_FROM_SHORTL): Add BU_P9V_OVERLOAD_1 and BU_P9V_VSX_1 + new builtins. + * config/rs6000/vsx.md vsx_xvcvhpsp): Add define_insn. + (vextract_fp_from_shorth, vextract_fp_from_shortl): Add define_expands. + * doc/extend.texi: Update the built-in documentation file for the + new built-in function. + +2017-07-24 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/81521 + * tree.def: Remove TYPE_METHODS documentation, adjust TYPE_FIELDS + documentation. + * doc/generic.texi: Likewise. + * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look + for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. + +2017-07-24 Jackson Woodruff <jackson.woodruff@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): New. + (aarch64_mls_elt_merge<mode>): Likewise. + +2017-07-23 Krister Walfridsson <krister.walfridsson@gmail.com> + + * config.gcc (*-*-netbsd*): Remove check for NetBSD versions not + having __cxa_atexit. + +2017-07-23 Michael Collison <michael.collison@arm.com> + + * config/arm/arm.c (arm_option_override): Deprecate + use of -mstructure-size-boundary. + * config/arm/arm.opt: Deprecate -mstructure-size-boundary. + * doc/invoke.texi: Deprecate -mstructure-size-boundary. + +2017-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/80695 + * config/rs6000/rs6000.c (rs6000_builtin_vectorization_cost): + Reduce cost estimate for direct moves. + +2017-07-23 Uros Bizjak <ubizjak@gmail.com> + + PR target/80569 + * config/i386/i386.c (ix86_option_override_internal): Disable + BMI, BMI2 and TBM instructions for -m16. + +2017-07-21 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW, + ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries. + * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin, + builtin_function_type): Add ALTIVEC_BUILTIN_* case statements. + * config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW, + VMULOSW): New enum "unspec" values. + (altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw, + altivec_vmulosw): New patterns. + * config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW, + VMULOSW): Add definitions. + +2017-07-21 Jim Wilson <jim.wilson@linaro.org> + + * config/aarch64/aarch64-cores.def (falkor): Add AARCH64_FL_RDMA. + (qdf24xx): Likewise. + * config/aarch64/aarch64-options-extensions.def (rdma); New. + * config/aarch64/aarch64.h (AARCH64_FL_RDMA): New. + (AARCH64_FL_V8_1): Renumber. + (AARCH64_FL_FOR_ARCH8_1): Add AARCH64_FL_RDMA. + (AARCH64_ISA_RDMA): Use AARCH64_FL_RDMA. + * config/aarch64/arm_neon.h: Use +rdma instead of arch=armv8.1-a. + * doc/invoke.texi (AArch64 Options): Mention +rmda in -march docs. Add + rdma to feature modifiers list. + +2017-07-21 Yury Gribov <tetra2005@gmail.com> + + PR middle-end/56727 + * ipa-visibility (function_and_variable_visibility): Convert + recursive PLT call to direct call if appropriate. + +2017-07-21 Andrew Pinski <apinski@cavium.com> + + * tree-ssa-sccvn.c (vn_nary_op_eq): Check BIT_INSERT_EXPR's + operand 1 to see if the types precision matches. + * fold-const.c (operand_equal_p): Likewise. + +2017-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81303 + * tree-vect-data-refs.c (vect_get_peeling_costs_all_drs): Pass + in datarefs vector. Allow NULL dr0 for no peeling cost estimate. + (vect_peeling_hash_get_lowest_cost): Adjust. + (vect_enhance_data_refs_alignment): Likewise. Use + vect_get_peeling_costs_all_drs to compute the penalty for no + peeling to match up costs. + +2017-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81500 + * tree-vect-loop.c (vect_is_simple_reduction): Properly fail if + we didn't identify a reduction path. + +2017-07-21 Tom de Vries <tom@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + PR gcov-profile/81442 + * config/nvptx/nvptx.c (nvptx_goacc_reduction_init): Add missing edge + probabilities. + +2017-07-21 Tom de Vries <tom@codesourcery.com> + + PR lto/81430 + * config/nvptx/nvptx.c (nvptx_override_options_after_change): New + function. + (TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define to + nvptx_override_options_after_change. + +2017-07-21 Ulrich Drepper <drepper@redhat.com> + + * dwarf2out.c (output_file_names): Avoid double testing for + dwarf_version >= 5. + +2017-07-21 Georg-Johann Lay <avr@gjlay.de> + + * doc/invoke.texi (AVR Built-in Functions): Re-layout section. + +2016-07-21 Jan Hubicka <hubicka@ucw.cz> + + * cfgcleanup.c (flow_find_cross_jump): Do not crossjump across + hot/cold regions. + (try_crossjump_to_edge): Do not punt on partitioned functions. + +2016-07-21 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (find_rarely_executed_basic_blocks_and_crossing_edges): + Put all BBs reachable only via paths crossing cold region to cold + region. + * cfgrtl.c (find_bbs_reachable_by_hot_paths): New function. + +2016-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81303 + * tree-vect-loop.c (vect_estimate_min_profitable_iters): Take + into account prologue and epilogue iterations when raising + min_profitable_iters to sth at least covering one vector iteration. + +2017-07-21 Tamar Christina <tamar.christina@arm.com> + + * config/arm/arm.c (arm_test_cpu_arch_dat): + Check for overlap. + +2017-07-20 Nathan Sidwell <nathan@acm.org> + + Remove TYPE_METHODS. + * tree.h (TYPE_METHODS): Delete. + * dwarf2out.c (gen_member_die): Member fns are on TYPE_FIELDS. + * dbxout.c (dbxout_type_fields): Ignore FUNCTION_DECLs. + (dbxout_type_methods): Scan TYPE_FIELDS. + (dbxout_type): Don't check TYPE_METHODS here. + * function.c (use_register_for_decl): Always ignore register for + class types when not optimizing. + * ipa-devirt.c (odr_types_equivalent_p): Delete TYPE_METHODS scan. + * tree.c (free_lang_data_in_type): Stitch out member functions and + templates from TYPE_FIELDS. + (build_distinct_type_copy, verify_type_variant, + verify_type): Member fns are on TYPE_FIELDS. + * tree-dump.c (dequeue_and_dump): No TYPE_METHODS. + * tree-pretty-print.c (dump_generic_node): Likewise. + +2017-07-20 Jakub Jelinek <jakub@redhat.com> + + PR target/80846 + * config/i386/i386.c (ix86_expand_vector_init_general): Handle + V2TImode and V4TImode. + (ix86_expand_vector_extract): Likewise. + * config/i386/sse.md (VMOVE): Enable V4TImode even for just + TARGET_AVX512F, instead of only for TARGET_AVX512BW. + (ssescalarmode): Handle V4TImode and V2TImode. + (VEC_EXTRACT_MODE): Add V4TImode and V2TImode. + (*vec_extractv2ti, *vec_extractv4ti): New insns. + (VEXTRACTI128_MODE): New mode iterator. + (splitter for *vec_extractv?ti first element): New. + (VEC_INIT_MODE): New mode iterator. + (vec_init<mode>): Consolidate 3 expanders into one using + VEC_INIT_MODE mode iterator. + +2017-07-20 Alexander Monakov <amonakov@ispras.ru> + + * lra-assigns.c (pseudo_compare_func): Fix comparison step based on + non_spilled_static_chain_regno_p. + +2017-07-20 Alexander Monakov <amonakov@ispras.ru> + + * gimple-ssa-store-merging.c (sort_by_bitpos): Return 0 on equal bitpos. + +2017-07-20 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (connect_traces): Allow copying of blocks within + single partition. + +2017-07-20 Richard Biener <rguenther@suse.de> + + * gimple.h (gimple_phi_result): Add gphi * overload. + (gimple_phi_result_ptr): Likewise. + (gimple_phi_arg): Likewise. Adjust index assert to only + allow actual argument accesses rather than all slots available + by capacity. + (gimple_phi_arg_def): Add gphi * overload. + * tree-phinodes.c (make_phi_node): Initialize only actual + arguments. + (resize_phi_node): Clear memory not covered by old node, + do not initialize excess argument slots. + (reserve_phi_args_for_new_edge): Initialize new argument slot + completely. + +2017-07-20 Bin Cheng <bin.cheng@arm.com> + + PR tree-optimization/81388 + Revert r238585: + 2016-07-21 Bin Cheng <bin.cheng@arm.com> + + * tree-ssa-loop-niter.c (number_of_iterations_lt_to_ne): Clean up + by removing computation of may_be_zero. + +2017-07-18 Jan Hubicka <hubicka@ucw.cz> + Tom de Vries <tom@codesourcery.com> + + PR middle-end/81030 + * cfgbuild.c (find_many_sub_basic_blocks): Update REG_BR_PROB note + when gimple level profile disagrees with what RTL expander did. + +2017-07-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61171 + * tree-vectorizer.h (slp_instance): Add reduc_phis member. + (vect_analyze_stmt): Add slp instance parameter. + (vectorizable_reduction): Likewise. + * tree-vect-loop.c (vect_analyze_loop_operations): Adjust. + (vect_is_simple_reduction): Deal with chains not detected + as SLP reduction chain, specifically not properly associated + chains containing a mix of plus/minus. + (get_reduction_op): Remove. + (get_initial_defs_for_reduction): Simplify, pass in whether + this is a reduction chain, pass in the SLP node for the PHIs. + (vect_create_epilog_for_reduction): Get the SLP instance as + arg and adjust. + (vectorizable_reduction): Get the SLP instance as arg. + During analysis remember the SLP node with the PHIs in the + instance. Simplify getting at the vectorized reduction PHIs. + * tree-vect-slp.c (vect_slp_analyze_node_operations): Pass + through SLP instance. + (vect_slp_analyze_operations): Likewise. + * tree-vect-stms.c (vect_analyze_stmt): Likewise. + (vect_transform_stmt): Likewise. + +2017-07-20 Tom de Vries <tom@codesourcery.com> + + PR tree-optimization/81489 + * gimple-ssa-isolate-paths.c (find_implicit_erroneous_behavior): Move + read of phi arg location to before loop that modifies phi. + +2017-07-20 Naveen H.S <Naveen.Hurugalawadi@cavium.com> + + * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0): + New pattern. + +2017-07-19 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/81331 + * except.c (execute): Fix ordering issue. + +2018-07-19 Segher Boessenkool <segher@kernel.crashing.org> + + PR rtl-optimization/81423 + * combine.c (make_compound_operation_int): Don't try to optimize + the AND of a SUBREG of an LSHIFTRT if that SUBREG is paradoxical. + +2017-07-19 Segher Boessenkool <segher@kernel.crashing.org> + + PR rtl-optimization/81423 + * simplify-rtx.c (simplify_truncation): Handle truncating an IOR + with a constant that is -1 in the truncated to mode. + +2017-07-19 Jan Hubicka <hubicka@ucw.cz> + + * predict.c (propagate_unlikely_bbs_forward): Break out from ... + (determine_unlikely_bbs): ... here. + * predict.h (propagate_unlikely_bbs_forward): Declare. + * cfgexpand.c (pass_expand::execute): Use it. + * bb-reorder.c (sanitize_hot_paths): Do not consider known to be + unlikely edges. + (find_rarely_executed_basic_blocks_and_crossing_edges): Use + propagate_unlikely_bbs_forward. + +2017-07-19 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/81331 + * except.c (maybe_add_nop_after_section_switch): New function. + (execute): Use it. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * gimple.h (gimple_phi_set_arg): Make assert more strict. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * gimple.h (gimple_phi_arg): Make assert more strict. + +2017-07-19 Steven Munroe <munroesj@gcc.gnu.org> + + * config.gcc (powerpc*-*-*): Add mmintrin.h. + * config/rs6000/mmintrin.h: New file. + * config/rs6000/x86intrin.h [__ALTIVEC__]: Include mmintrin.h. + +2017-07-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81346 + * match.pd: Optimize (X - 1U) <= INT_MAX-1U into (int) X > 0. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * config/nvptx/nvptx.md (VECIM): Add V2DI. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * config/nvptx/nvptx-modes.def: Add V2DImode. + * config/nvptx/nvptx-protos.h (nvptx_data_alignment): Declare. + * config/nvptx/nvptx.c (nvptx_ptx_type_from_mode): Handle V2DImode. + (nvptx_output_mov_insn): Handle lack of mov.b128. + (nvptx_print_operand): Handle 'H' and 'L' codes. + (nvptx_vector_mode_supported): Allow V2DImode. + (nvptx_preferred_simd_mode): New function. + (nvptx_data_alignment): New function. + (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Redefine to + nvptx_preferred_simd_mode. + * config/nvptx/nvptx.h (STACK_BOUNDARY, BIGGEST_ALIGNMENT): Change from + 64 to 128 bits. + (DATA_ALIGNMENT): Define. Set to nvptx_data_alignment. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * config/nvptx/nvptx-modes.def: New file. Add V2SImode. + * config/nvptx/nvptx.c (nvptx_ptx_type_from_mode): Handle V2SImode. + (nvptx_vector_mode_supported): New function. Allow V2SImode. + (TARGET_VECTOR_MODE_SUPPORTED_P): Redefine to nvptx_vector_mode_supported. + * config/nvptx/nvptx.md (VECIM): New mode iterator. Add V2SI. + (mov<VECIM>_insn): New define_insn. + (define_expand "mov<VECIM>): New define_expand. + +2017-07-19 Tom de Vries <tom@codesourcery.com> + + * config/nvptx/nvptx.c (nvptx_print_operand): Handle v2 vector mode. + +2017-07-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81346 + * fold-const.h (fold_div_compare, range_check_type): Declare. + * fold-const.c (range_check_type): New function. + (build_range_check): Use range_check_type. + (fold_div_compare): No longer static, rewritten into + a match.pd helper function. + (fold_comparison): Don't call fold_div_compare here. + * match.pd (X / C1 op C2): New optimization using fold_div_compare + as helper function. + +2017-07-19 Nathan Sidwell <nathan@acm.org> + + * tree.h (TYPE_MINVAL, TYPE_MAXVAL): Rename to ... + (TYPE_MIN_VALUE_RAW, TYPE_MAX_VALUE_RAW): ... these. + * tree.c (find_decls_types_r, verify_type): Use + TYPE_{MIN,MAX}_VALUE_RAW. + * lto-streamer-out.c (DFS::DFS_write_tree_body): Likewise. + (hash_tree): Likewise. + * tree-streamer-in.c (lto_input_ts_type_non_common_tree_pointers): + Likewise. + * tree-streamer-out.c (write_ts_type_non_common_tree_pointers): + Likewise. + +2017-07-18 Tom de Vries <tom@codesourcery.com> + + PR middle-end/81464 + * omp-expand.c (expand_omp_for_static_chunk): Handle + equal-argument loop exit phi. + +2017-07-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/81471 + * config/i386/i386.md (rorx_immediate_operand): New mode attribute. + (*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as + operand 2 predicate. + (*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as + operand 2 predicate. + (ror,rol -> rorx splitters): Use const_int_operand as + operand 2 predicate. + +2017-06-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81410 + * tree-vect-stmts.c (vectorizable_load): Properly adjust for + the gap in the ! slp_perm SLP case after each group. + +2017-07-18 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/81463 + * cfgloopmanip.c (scale_loop_profile): Watch out for zero frequency + again. + +2017-07-18 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/81462 + * predict.c (set_even_probabilities): Cleanup; do not affect + probabilities that are already known. + (combine_predictions_for_bb): Call even when count is set. + +2017-07-18 Nathan Sidwell <nathan@acm.org> + + * tree-parloops.c (try_transform_to_exit_first_loop_alt): Use + TYPE_MAX_VALUE. + +2017-07-18 Bin Cheng <bin.cheng@arm.com> + + PR target/81408 + * tree-ssa-loop-niter.c (number_of_iterations_exit): Dump missed + optimization for loop niter analysis. + +2017-07-18 Georg-Johann Lay <avr@gjlay.de> + + PR target/81473 + * config/avr/avr.c (avr_optimize_casesi): Don't use + INT8_MIN, INT8_MAX, UINT8_MAX, INT16_MIN, INT16_MAX, UINT16_MAX. + +2017-07-18 Robin Dapp <rdapp@linux.vnet.ibm.com> + + * tree-vect-data-refs.c (vect_enhance_data_refs_alignment): Remove + body_cost_vec from _vect_peel_extended_info. + (vect_peeling_hash_get_lowest_cost): Do not set body_cost_vec. + (vect_peeling_hash_choose_best_peeling): Remove body_cost_vec and + npeel. + +2017-07-18 Bin Cheng <bin.cheng@arm.com> + + * config/arm/arm.c (emit_unlikely_jump): Remove unused var. + +2017-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/80620 + PR tree-optimization/81403 + * tree-ssa-pre.c (phi_translate_1): Clear range and points-to + info when re-using a VN table entry. + +2017-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81418 + * tree-vect-loop.c (vectorizable_reduction): Properly compute + vectype_in. Verify that with lane-reducing reduction operations + we have a single def-use cycle. + +2017-07-17 Carl Love <cel@us.ibm.com> + + Revert commit r249424 2017-06-20 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW, + ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries. + * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin, + builtin_function_type): Add ALTIVEC_BUILTIN_* case statements. + * config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW, + VMULOSW): New enum "unspec" values. + (vec_widen_umult_even_v4si, vec_widen_smult_even_v4si, + vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, + altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw, + altivec_vmulosw): New patterns. + * config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW, + VMULOSW): Add definitions. +2017-07-17 Uros Bizjak <ubizjak@gmail.com> + + * config/alpha/alpha.c: Include predict.h. + +2017-07-17 Yury Gribov <tetra2005@gmail.com> + + * tree-vrp.c (compare_assert_loc): Fix comparison function + to return predictable results. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.md (adddi3): Remove support for mexpand-adddi + option. + (subdi3): Likewise. + * config/arc/arc.opt (mexpand-adddi): Deprecate it. + * doc/invoke.texi (mexpand-adddi): Update text. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.md (clzsi2): Expand to an arc_clzsi2 instruction + that also clobbers the CC register. The old expand code is moved + to ... + (*arc_clzsi2): ... here. + (ctzsi2): Expand to an arc_ctzsi2 instruction that also clobbers + the CC register. The old expand code is moved to ... + (arc_ctzsi2): ... here. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.opt (mindexed-loads): Use initial value + TARGET_INDEXED_LOADS_DEFAULT. + (mauto-modify-reg): Use initial value + TARGET_AUTO_MODIFY_REG_DEFAULT. + * config/arc/elf.h (TARGET_INDEXED_LOADS_DEFAULT): Define. + (TARGET_AUTO_MODIFY_REG_DEFAULT): Likewise. + * config/arc/linux.h (TARGET_INDEXED_LOADS_DEFAULT): Define. + (TARGET_AUTO_MODIFY_REG_DEFAULT): Likewise. + +2017-07-17 Martin Liska <mliska@suse.cz> + + PR sanitizer/81302 + * opts.c (finish_options): Do not allow -fgnu-tm + w/ -fsanitize={kernel-,}address. Say sorry. + +2017-07-17 Bin Cheng <bin.cheng@arm.com> + + PR target/81369 + * tree-loop-distribution.c (classify_partition): Only assert on + numer of iterations. + (merge_dep_scc_partitions): Delete prameter. Update function call. + (distribute_loop): Remove code handling loop with unknown niters. + (pass_loop_distribution::execute): Skip loop with unknown niters. + +2017-07-17 Bin Cheng <bin.cheng@arm.com> + + PR target/81369 + * tree-loop-distribution.c (merge_dep_scc_partitions): Sink call to + function sort_partitions_by_post_order. + +2017-07-17 Bin Cheng <bin.cheng@arm.com> + + PR tree-optimization/81374 + * tree-loop-distribution.c (pass_loop_distribution::execute): Record + the max index of basic blocks, rather than number of basic blocks. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc-protos.h (arc_legitimate_pc_offset_p): Remove + proto. + (arc_legitimate_pic_operand_p): Likewise. + * config/arc/arc.c (arc_legitimate_pic_operand_p): Remove + function. + (arc_needs_pcl_p): Likewise. + (arc_legitimate_pc_offset_p): Likewise. + (arc_legitimate_pic_addr_p): Remove LABEL_REF case, as this + function is also used in constrains.md. + (arc_legitimate_constant_p): Use arc_legitimate_pic_addr_p to + validate pic constants. Handle CONST_INT, CONST_DOUBLE, MINUS and + PLUS. Only return true/false in known cases, otherwise assert. + (arc_legitimate_address_p): Remove arc_legitimate_pic_addr_p as it + is already called in arc_legitimate_constant_p. + * config/arc/arc.h (CONSTANT_ADDRESS_P): Consider also LABEL for + pic addresses. + (LEGITIMATE_PIC_OPERAND_P): Use + arc_raw_symbolic_reference_mentioned_p function. + * config/arc/constraints.md (Cpc): Use arc_legitimate_pic_addr_p + function. + (Cal): Likewise. + (C32): Likewise. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + Andrew Burgess <andrew.burgess@embecosm.com> + + * config/arc/arc-protos.h (arc_compute_function_type): Change prototype. + (arc_return_address_register): New function. + * config/arc/arc.c (arc_handle_fndecl_attribute): New function. + (arc_handle_fndecl_attribute): Add naked attribute. + (TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS): Define. + (TARGET_WARN_FUNC_RETURN): Likewise. + (arc_allocate_stack_slots_for_args): New function. + (arc_warn_func_return): Likewise. + (machine_function): Change type fn_type. + (arc_compute_function_type): Consider new naked function type, + change function return type. + (arc_must_save_register): Adapt to handle new + arc_compute_function_type's return type. + (arc_expand_prologue): Likewise. + (arc_expand_epilogue): Likewise. + (arc_return_address_regs): Delete. + (arc_return_address_register): New function. + (arc_epilogue_uses): Use above function. + * config/arc/arc.h (arc_return_address_regs): Delete prototype. + (arc_function_type): Change encoding, add naked type. + (ARC_INTERRUPT_P): Change to handle the new encoding. + (ARC_FAST_INTERRUPT_P): Likewise. + (ARC_NORMAL_P): Define. + (ARC_NAKED_P): Likewise. + (arc_compute_function_type): Delete prototype. + * config/arc/arc.md (in_ret_delay_slot): Use + arc_return_address_register function. + (simple_return): Likewise. + (p_return_i): Likewise. + +2017-07-17 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81428 + * match.pd (X / X -> one): Don't optimize _Fract divisions, as 1 + can't be built for those types. + +2017-07-17 Georg-Johann Lay <avr@gjlay.de> + + Remove stuff dead since r239246. + + * config/avr/avr-arch.h (avr_inform_devices): Remove dead proto. + * config/avr/avr-devices.c (mcu_name, comparator, avr_mcus_str) + (avr_inform_devices): Remove dead stuff. + +2017-07-17 Tamar Christina <tamar.christina@arm.com> + + * config/arm/arm_neon.h: Fix softp typo. + +2017-07-17 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81365 + * tree-ssa-phiprop.c (propagate_with_phi): When considering hoisting + aggregate moves onto bb predecessor edges, make sure there are no + loads that could alias the lhs in between the start of bb and the + loads from *phi. + +2017-07-17 Georg-Johann Lay <avr@gjlay.de> + + PR 80929 + * config/avr/avr.c (avr_mul_highpart_cost): New static function. + (avr_rtx_costs_1) [TRUNCATE]: Use it to compute mul_highpart cost. + [LSHIFTRT, outer_code = TRUNCATE]: Same. + +2017-07-17 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/81396 + * tree-ssa-math-opts.c (struct symbolic_number): Add n_ops field. + (init_symbolic_number): Initialize it to 1. + (perform_symbolic_merge): Add n_ops from both operands into the new + n_ops. + (find_bswap_or_nop): Don't consider n->n == cmpnop computations + without base_addr as useless if they need more than one operation. + (bswap_replace): Handle !bswap case for NULL base_addr. + +2017-07-17 Tom de Vries <tom@codesourcery.com> + + PR target/81069 + * config/nvptx/nvptx.c (nvptx_single): Insert diverging branch as late + as possible. + +2017-07-17 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add + conditional builtin define __FIX_LEON3FT_B2BST. + +2017-07-17 Daniel Cederman <cederman@gaisler.com> + + * config/sparc/t-rtems: Add mfix-gr712rc multilibs. Replace + MULTILIB_EXCEPTIONS with MULTILIB_REQUIRED. Match -mfix-gr712rc + with -mfix-ut700. + +2017-07-16 Eric Botcazou <ebotcazou@adacore.com> + + PR rtl-optimization/81424 + * optabs.c (prepare_cmp_insn): Use copy_to_reg instead of force_reg + to remove potential trapping from operands if -fnon-call-exceptions. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * tree-ssa-loop-manip.c (tree_transform_and_unroll_loop): Use + profile_proability for scalling. + * scale_profile_for_vect_loop.c (scale_profile_for_vect_loop): Likewise. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * cgraph.c (cgraph_edge::redirect_call_stmt_to_caller): Cleanup. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * cfgloopmanip.c (scale_loop_profile): Avoid use of REG_BR_PROB_BASE + fixpoint arithmetics. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * tree-ssa-loop-unswitch.c (hoist_guard): Avoid use of REG_BR_PROB_BASE + fixpoint arithmetics. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * asan.c (create_cond_insert_point): Avoid use of REG_BR_PROB_BASE + fixpoint arithmetics. + +2017-07-16 Jan Hubicka <hubicka@ucw.cz> + + * profile-count.h (profile_probability::from_reg_br_prob_note, + profile_probability::to_reg_br_prob_note): New functions. + * doc/rtl.texi (REG_BR_PROB_NOTE): Update documentation. + * reg-notes.h (REG_BR_PROB, REG_BR_PRED): Update docs. + * predict.c (probability_reliable_p): Update. + (edge_probability_reliable_p): Update. + (br_prob_note_reliable_p): Update. + (invert_br_probabilities): Update. + (add_reg_br_prob_note): New function. + (combine_predictions_for_insn): Update. + * asan.c (asan_clear_shadow): Update. + * cfgbuild.c (compute_outgoing_frequencies): Update. + * cfgrtl.c (force_nonfallthru_and_redirect): Update. + (update_br_prob_note): Update. + (rtl_verify_edges): Update. + (purge_dead_edges): Update. + (fixup_reorder_chain): Update. + * emit-rtl.c (try_split): Update. + * ifcvt.c (cond_exec_process_insns): Update. + (cond_exec_process_if_block): Update. + (dead_or_predicable): Update. + * internal-fn.c (expand_addsub_overflow): Update. + (expand_neg_overflow): Update. + (expand_mul_overflow): Update. + * loop-doloop.c (doloop_modify): Update. + * loop-unroll.c (compare_and_jump_seq): Update. + * optabs.c (emit_cmp_and_jump_insn_1): Update. + * predict.h: Update. + * reorg.c (mostly_true_jump): Update. + * rtl.h: Update. + * config/aarch64/aarch64.c (aarch64_emit_unlikely_jump): Update. + * config/alpha/alpha.c (emit_unlikely_jump): Update. + * config/arc/arc.c: (emit_unlikely_jump): Update. + * config/arm/arm.c: (emit_unlikely_jump): Update. + * config/bfin/bfin.c (cbranch_predicted_taken_p): Update. + * config/frv/frv.c (frv_print_operand_jump_hint): Update. + * config/i386/i386.c (ix86_expand_split_stack_prologue): Update. + (ix86_print_operand): Update. + (ix86_split_fp_branch): Update. + (predict_jump): Update. + * config/ia64/ia64.c (ia64_print_operand): Update. + * config/mmix/mmix.c (mmix_print_operand): Update. + * config/powerpcspe/powerpcspe.c (output_cbranch): Update. + (rs6000_expand_split_stack_prologue): Update. + * config/rs6000/rs6000.c: Update. + * config/s390/s390.c (s390_expand_vec_strlen): Update. + (s390_expand_vec_movstr): Update. + (s390_expand_cs_tdsi): Update. + (s390_expand_split_stack_prologue): Update. + * config/sh/sh.c (sh_print_operand): Update. + (expand_cbranchsi4): Update. + (expand_cbranchdi4): Update. + * config/sparc/sparc.c (output_v9branch): Update. + * config/spu/spu.c (get_branch_target): Update. + (ea_load_store_inline): Update. + * config/tilegx/tilegx.c (cbranch_predicted_p): Update. + * config/tilepro/tilepro.c: Update. + +2017-07-16 Eric Botcazou <ebotcazou@adacore.com> + + * gimplify.c (mostly_copy_tree_r): Revert latest change. + (gimplify_save_expr): Likewise. + +2017-07-07 Jan Hubicka <hubicka@ucw.cz> + + * ipa-visibility.c (function_and_variable_visibility): Fix pasto. + +2017-07-07 Jan Hubicka <hubicka@ucw.cz> + + * ipa-fnsummary.c (pass_data_ipa_fn_summary): Use + TV_IPA_FNSUMMARY. + * timevar.def (TV_IPA_FNSUMMARY): Define. + +2017-07-16 Daniel Cederman <cederman@gaisler.com> + + * config/sparc/sparc.md (divdf3_fix): Add NOP to prevent back + to back store errata sensitive sequence from being generated. + (sqrtdf2_fix): Likewise. + +2017-07-07 Jan Hubicka <hubicka@ucw.cz> + + * tree-ssa-threadupdate.c (compute_path_counts, + update_joiner_offpath_counts): Use profile_probability. + +2017-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Revert: + 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-c.c (arm_cpu_builtins): Define + __ARM_FEATURE_NUMERIC_MAXMIN solely based on TARGET_VFP5. + +2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + array entries to represent __ieee128 versions of the + scalar_test_data_class, scalar_test_neg, scalar_extract_exp, + scalar_extract_sig, and scalar_insert_exp built-in functions. + (altivec_resolve_overloaded_builtin): Add special case handling + for the __builtin_scalar_insert_exp function, as represented by + the P9V_BUILTIN_VEC_VSIEDP constant. + * config/rs6000/rs6000-builtin.def (VSEEQP): Add scalar extract + exponent support for __ieee128 argument. + (VSESQP): Add scalar extract signature support for __ieee128 + argument. + (VSTDCNQP): Add scalar test negative support for __ieee128 + argument. + (VSIEQP): Add scalar insert exponent support for __int128 argument + with __ieee128 result. + (VSIEQPF): Add scalar insert exponent support for __ieee128 + argument with __ieee128 result. + (VSTDCQP): Add scalar test data class support for __ieee128 + argument. + (VSTDCNQP): Add overload support for scalar test negative with + __ieee128 argument. + (VSTDCQP): Add overload support for scalar test data class + __ieee128 argument. + * config/rs6000/vsx.md (UNSPEC_VSX_SXSIG) Replace + UNSPEC_VSX_SXSIGDP. + (UNSPEC_VSX_SIEXPQP): New constant. + (xsxexpqp): New insn for VSX scalar extract exponent quad + precision. + (xsxsigqp): New insn for VSX scalar extract significand quad + precision. + (xsiexpqpf): New insn for VSX scalar insert exponent quad + precision with floating point argument. + (xststdcqp): New expand for VSX scalar test data class quad + precision. + (xststdcnegqp): New expand for VSX scalar test negative quad + precision. + (xststdcqp): New insn to match expansions for VSX scalar test data + class quad precision and VSX scalar test negative quad precision. + * config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add + special case operand checking to enforce that second operand of + VSX scalar test data class with quad precision argument is a 7-bit + unsigned literal. + * doc/extend.texi (PowerPC AltiVec Built-in Functions): Add + prototypes and descriptions of __ieee128 versions of + scalar_extract_exp, scalar_extract_sig, scalar_insert_exp, + scalar_test_data_class, and scalar_test_neg built-in functions. + +2016-07-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR tree-optimization/81162 + * gimple-ssa-strength-reduction.c (replace_mult_candidate): Don't + replace a negate with an add. + +2017-07-14 James Greenhalgh <james.greenhalgh@arm.com> + + * doc/invoke.texi (arm/-mcpu): Document +crypto. + +2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-c.c (arm_cpu_builtins): Define + __ARM_FEATURE_NUMERIC_MAXMIN solely based on TARGET_VFP5. + +2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-cpus.in (cortex-r52): Add new entry. + (armv8-r): Set ARM Cortex-R52 as default CPU. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Regenerate. + * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM + Cortex-R52. + * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp + extension for -mcpu=cortex-r52. + +2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator. + (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32. + * config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5. + (fp-armv8): Define it as FP_ARMv8 only. + config/arm/arm.h (TARGET_FPU_ARMV8): Delete. + (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than + TARGET_FPU_ARMV8. + config/arm/arm.c (arm_rtx_costs_internal): Replace checks against + TARGET_FPU_ARMV8 by checks against TARGET_VFP5. + * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define + first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather + than TARGET_FPU_ARMV8. + * config/arm/arm-c.c (arm_cpu_builtins): Likewise for + __ARM_FEATURE_NUMERIC_MAXMIN macro definition. + * config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than + TARGET_FPU_ARMV8. + * config/arm/neon.md (neon_vrint): Likewise. + (neon_vcvt): Likewise. + (neon_<fmaxmin_op><mode>): Likewise. + (<fmaxmin><mode>3): Likewise. + * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise. + * config/arm/predicates.md (arm_cond_move_operator): Check against + TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing. + +2017-07-14 Jackson Woodruff <jackson.woodruff@arm.com> + + * config/aarch64/aarch64.c (aarch64_print_operand): Move comments + to top of function. + +2017-07-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gimple-ssa-store-merging.c (clear_bit_region): Replace reference to + loop in comment with memset. + +2017-07-14 Martin Liska <mliska@suse.cz> + + * cfgexpand.c (expand_gimple_basic_block): Remove dead comment. + * dwarf2out.c (is_java): Remove the function. + (output_pubname): Remove usage of the function. + (lower_bound_default): Remove usage of DW_LANG_Java. + (gen_compile_unit_die): Likewise. + * gcc.c: Remove compiler defaults for .java and .zip files. + * gimple-expr.c (remove_suffix): Change as there's no longer + extension than 4-letter one. + * gimplify.c (mostly_copy_tree_r): Remove Java-special part. + (gimplify_save_expr): Likewise. + * ipa-utils.h (polymorphic_type_binfo_p): Remove the comment + as it's possible even for other languages than Java. + * langhooks.h (struct lang_hooks): Remove Java from a comment. + * lto-opts.c (lto_write_options): Remove reference to Java. + * opts.c (strip_off_ending): Update file extension handling. + * tree-cfg.c (verify_gimple_call): Remove comment with Java. + * tree-eh.c (lower_resx): Likewise. + * tree.c (free_lang_data_in_type): Remove dead code. + (find_decls_types_r): Likewise. + (build_common_builtin_nodes): Remove Java from a comment. + (verify_type): Remove dead code. + * varasm.c (assemble_external): Remove Java from a comment. + +2017-07-14 Martin Liska <mliska@suse.cz> + + * opts.c (finish_options): Add quotes. + (common_handle_option): Likewise. + +2017-07-14 Martin Liska <mliska@suse.cz> + + * dbxout.c (get_lang_number): Do not handle GNU Pascal. + * dbxout.h (extern void dbxout_stab_value_internal_label_diff): + Remove N_SO_PASCAL. + * dwarf2out.c (lower_bound_default): Do not handle + DW_LANG_Pascal83. + (gen_compile_unit_die): Likewise. + * gcc.c: Remove default extension binding for GNU Pascal. + * stmt.c: Remove Pascal language from a comment. + * xcoffout.c: Likewise. + +2017-07-13 David Malcolm <dmalcolm@redhat.com> + + PR c/81405 + * diagnostic-show-locus.c (fixit_cmp): New function. + (layout::layout): Sort m_fixit_hints. + (column_range::column_range): Assert that the values are valid. + (struct char_span): New struct. + (correction::overwrite): New method. + (struct source_line): New struct. + (line_corrections::add_hint): Add assertions. Reimplement memcpy + calls in terms of classes source_line and char_span, and + correction::overwrite. + (selftest::test_overlapped_fixit_printing_2): New function. + (selftest::diagnostic_show_locus_c_tests): Call it. + +2017-07-13 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Return + early if there is no lhs. + +2017-07-13 Martin Liska <mliska@suse.cz> + + * dwarf2out.c (gen_pointer_type_die): Remove dead code. + (gen_reference_type_die): Likewise. + * stor-layout.c: Remove Pascal-related comment. + +2017-07-13 Martin Liska <mliska@suse.cz> + + * opts.c (finish_options): Add quotes to error messages. + (parse_sanitizer_options): Likewise. + +2017-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * doc/invoke.texi (armv8-r): Document +fp.sp ARMv8-R extension. + +2017-07-13 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/vxworks.h (TARGET_ENDIAN_DEFAULT): Define. + +2017-07-13 Maxim Ostapenko <m.ostapenko@samsung.com> + + * asan.c (asan_emit_allocas_unpoison): Use ptr_mode for arguments + during expansion. + * builtins.c (expand_asan_emit_allocas_unpoison): Likewise. + +2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/81193 + * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC + provides the hardware capability bits, define the macro + __BUILTIN_CPU_SUPPORTS__. + * config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning + if GLIBC does not provide the hardware capability bits. Add a + gcc_unreachable call if the built-in cpu function is neither + __builtin_cpu_is nor __builtin_cpu_supports. + (rs6000_get_function_versions_dispatcher): Change the warning + that an old GLIBC is used which does not export the capability + bits to be an error. + * doc/extend.texi (target_clones attribute): Document the + restriction that GLIBC 2.23 or newer is needed on the PowerPC. + (PowerPC built-in functions): Document that GLIBC 2.23 or newer is + needed by __builtin_cpu_is and __builtin_cpu_supports. Document + the macros defined by GCC if the newer GLIBC is available. + +2017-07-12 Jeff Law <law@redhat.com> + + * config/riscv/riscv.c: Remove unnecessary includes. Reorder + remaining includes slightly. + * config/riscv/riscv-builtins.c: Include profile-count.h. + +2017-07-12 Georg-Johann Lay <avr@gjlay.de> + + PR target/79883 + * config/avr/avr.c (avr_set_current_function): In diagnostic + messages: Quote keywords and (parts of) identifiers. + [WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or + "INTERUPT". + +2017-07-12 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for built-in functions + vector bool char vec_revb (vector bool char); + vector bool short vec_revb (vector short char); + vector bool int vec_revb (vector bool int); + vector bool long long vec_revb (vector bool long long); + * doc/extend.texi: Update the built-in documentation file for the + new built-in functions. + +2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * config/s390/s390.md: Remove movcc splitter. + +2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * config/s390/s390.c (s390_rtx_costs): Return proper costs for + load/store on condition. + +2017-07-12 Georg-Johann Lay <avr@gjlay.de> + + PR target/81407 + * config/avr/avr.c (avr_encode_section_info) + [progmem && !TREE_READONLY]: Error if progmem object needs + constructing. + +2017-07-11 Michael Collison <michael.collison@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_sub<mode>_compare0): + New pattern. + +2017-07-11 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for builtins + vector unsigned int vec_parity_lsbb (vector signed int); + vector unsigned int vec_parity_lsbb (vector unsigned int); + vector unsigned __int128 vec_parity_lsbb (vector signed __int128); + vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128); + vector unsigned long long vec_parity_lsbb (vector signed long long); + vector unsigned long long vec_parity_lsbb (vector unsigned long long); + * config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1. + * config/rs6000/altivec.h (vec_parity_lsbb): Add define. + * doc/extend.texi: Update the built-in documentation file for the + new built-in functions. + +2017-07-11 David Malcolm <dmalcolm@redhat.com> + + * diagnostic-show-locus.c: Include "gcc-rich-location.h". + (layout::m_primary_loc): New field. + (layout::layout): Initialize new field. Move location filtering + logic from here to... + (layout::maybe_add_location_range): ...this new method. Add + support for filtering to just the lines already specified by other + locations. + (layout::will_show_line_p): New method. + (gcc_rich_location::add_location_if_nearby): New method. + (selftest::test_add_location_if_nearby): New test function. + (selftest::diagnostic_show_locus_c_tests): Call it. + * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby): + New method. + +2017-07-11 Tom de Vries <tom@codesourcery.com> + + * config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG): New macro. + (bb_first_real_insn): New function. + (nvptx_single): Add extra initialization of broadcasted condition + variables. + +2017-07-11 Nathan Sidwell <nathan@acm.org> + + * dwarf2out.c (gen_member_die): Remove useless check for anon ctors. + +2017-07-11 Georg-Johann Lay <avr@gjlay.de> + + * doc/extend.texi (AVR Function Attributes): Remove weblink to + Binutils doc as TEXI will mess them up. + * doc/invoke.texi (AVR Options): Same here. + +2017-07-11 Daniel Cederman <cederman@gaisler.com> + + * config/sparc/sparc.opt (mfix-ut700): New option. + (mfix-gr712rc): Likewise. + (sparc_fix_b2bst): New variable. + * doc/invoke.texi (SPARC options): Document them. + (ARM options): Fix warnings. + * config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP + instructions to prevent sequences that can trigger the store-store + errata for certain LEON3FT processors. + (pass_work_around_errata::gate): Also test sparc_fix_b2bst. + (sparc_option_override): Set sparc_fix_b2bst appropriately. + * config/sparc/sparc.md (fix_b2bst): New attribute. + (in_branch_delay): Prevent stores in delay slot if fix_b2bst. + +2017-07-10 Uros Bizjak <ubizjak@gmail.com> + + PR target/81375 + * config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH. + (rcpps): Ditto. + (*rsqrtsf2_sse): Ditto. + (rsqrtsf2): Ditto. + (div<mode>3): Macroize insn from divdf3 and divsf3 + using MODEF mode iterator. + +2017-07-10 Martin Sebor <msebor@redhat.com> + + PR tree-optimization/80397 + * gimple-ssa-sprintf.c (format_integer): Use INTEGRAL_TYPE_P() + instead of testing for equality to INTEGER_TYPE. + +2017-07-10 Vineet Gupta <vgupta@synopsys.com> + + * config.gcc: Remove uclibc from arc target spec. + +2017-07-10 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Define. + +2017-07-07 Jan Hubicka <hubicka@ucw.cz> + + PR lto/80838 + * lto-wrapper.c (remove_option): New function. + (merge_and_complain): Merge PIC/PIE options more realistically. + +2017-07-10 Georg-Johann Lay <avr@gjlay.de> + + Better ISR prologues by supporting GASes __gcc_isr pseudo insn. + + PR target/20296 + PR target/81268 + * configure.ac [target=avr]: Add GAS check for -mgcc-isr. + (HAVE_AS_AVR_MGCCISR_OPTION): If so, AC_DEFINE it. + * config.in: Regenerate. + * configure: Regenerate. + * doc/extend.texi (AVR Function Attributes) <no_gccisr>: Document it. + * doc/invoke.texi (AVR Options) <-mgas-isr-prologues>: Document it. + * config/avr/avr.opt (-mgas-isr-prologues): New option and... + (TARGET_GASISR_PROLOGUES): ...target mask. + * common/config/avr/avr-common.c + (avr_option_optimization_table) [OPT_LEVELS_1_PLUS_NOT_DEBUG]: + Set -mgas-isr-prologues. + * config/avr/avr-passes.def (avr_pass_pre_proep): Add + INSERT_PASS_BEFORE for it. + * config/avr/avr-protos.h (make_avr_pass_pre_proep): New proto. + * config/avr/avr.c (avr_option_override) + [!HAVE_AS_AVR_MGCCISR_OPTION]: Unset TARGET_GASISR_PROLOGUES. + (avr_no_gccisr_function_p, avr_hregs_split_reg): New static functions. + (avr_attribute_table) <no_gccisr>: Add new function attribute. + (avr_set_current_function) <is_no_gccisr>: Init machine field. + (avr_pass_data_pre_proep, avr_pass_pre_proep): New pass data + and rtl_opt_pass. + (make_avr_pass_pre_proep): New function. + (emit_push_sfr) <treg>: Add argument to function and use it + instead of TMP_REG. + (avr_expand_prologue) [machine->gasisr.maybe]: Emit gasisr insn + and set machine->gasisr.yes. + (avr_expand_epilogue) [machine->gasisr.yes]: Similar. + (avr_asm_function_end_prologue) [machine->gasisr.yes]: Add + __gcc_isr.n_pushed to .L__stack_usage. + (TARGET_ASM_FINAL_POSTSCAN_INSN): Define to... + (avr_asm_final_postscan_insn): ...this new static function. + * config/avr/avr.h (machine_function) + <is_no_gccisr, use_L__stack_usage>: New fields. + <gasisr, gasisr.yes, gasisr.maybe, gasisr.regno>: New fields. + * config/avr/avr.md (UNSPECV_GASISR): Add unspecv enum. + (GASISR_Prologue, GASISR_Epilogue, GASISR_Done): New define_constants. + (gasisr, *gasisr): New expander and insn. + * config/avr/gen-avr-mmcu-specs.c (print_mcu) + [HAVE_AS_AVR_MGCCISR_OPTION]: Print asm_gccisr spec. + * config/avr/specs.h (ASM_SPEC) <asm_gccisr>: Add sub spec. + +2017-07-10 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/parsecpu.awk (gen_comm_data): Do not escape single quotes + in quoted strings. + +2017-07-10 Georg-Johann Lay <avr@gjlay.de> + + Move jump-tables out of .text again. + + PR target/81075 + * config/avr/avr.c (ASM_OUTPUT_ADDR_VEC_ELT): Remove function. + (ASM_OUTPUT_ADDR_VEC): New function. + (avr_adjust_insn_length) [JUMP_TABLE_DATA_P]: Return 0. + (avr_final_prescan_insn) [avr_log.insn_addresses]: Dump + INSN_ADDRESSes as asm comment. + * config/avr/avr.h (JUMP_TABLES_IN_TEXT_SECTION): Adjust comment. + (ASM_OUTPUT_ADDR_VEC_ELT): Remove define. + (ASM_OUTPUT_ADDR_VEC): Define to avr_output_addr_vec. + * config/avr/avr.md (*tablejump): Adjust comment. + * config/avr/elf.h (ASM_OUTPUT_BEFORE_CASE_LABEL): Remove. + * config/avr/avr-log.c (avr_log_set_avr_log) <insn_addresses>: + New detail. + * config/avr/avr-protos.h (avr_output_addr_vec_elt): Remove proto. + (avr_output_addr_vec): New proto. + (avr_log_t) <insn_addresses>: New field. + +2017-07-09 H.J. Lu <hongjiu.lu@intel.com> + + PR target/81313 + * config/i386/i386.c (ix86_function_arg_advance): Set + outgoing_args_on_stack to true if there are outgoing arguments + on stack. + (ix86_function_arg): Likewise. + (ix86_get_drap_rtx): Use DRAP only if there are outgoing + arguments on stack and ACCUMULATE_OUTGOING_ARGS is false. + * config/i386/i386.h (machine_function): Add + outgoing_args_on_stack. + +2017-07-09 Krister Walfridsson <krister.walfridsson@gmail.com> + + * config.gcc (*-*-netbsd*): Remove check for NetBSD versions not + supporting pthreds. + * config/netbsd.h (NETBSD_LIBGCC_SPEC): Always enable pthreads. + +2017-07-08 Richard Sandiford <richard.sandiford@linaro.org> + + * Makefile.in (HOOKS_H, RTL_BASE_H, FUNCTION_H, EXPR_H, REGS_H) + (REAL_H): Remove $(MACHMODE_H). + (FIXED_VALUE_H, TREE_CORE_H, CFGLOOP_H): Remove $(MACHMODE_H) and + double-int.h. + (CORETYPES_H): Add signop.h, wide-int.h, wide-int-print.h, + $(MACHMODE_H) and double-int.h. + (build/min-insn-modes.o): Depend on $(CORETYPES_H) rather than + $(MACHMODE_H). + (gengtype-state.o, gengtype.o, build/gengtype.o): Don't depend on + double-int.h. + +2017-07-07 Andrew Pinski <apinski@cavium.com> + + * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Check + prev_set and curr_set for AARCH64_FUSE_ALU_BRANCH. + +2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (rs6000_get_function_versions_dispatcher): + Add warning if GCC was not configured to link against a GLIBC that + exports the hardware capability bits. + (make_resolver_func): Make resolver function private and not a + COMDAT function. Create the name with clone_function_name instead + of make_unique_name. + + PR target/81348 + * config/rs6000/rs6000.md (HI sign_extend splitter): Use the + correct operand in doing the split. + +2017-07-07 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c: Add support for built-in function + vector unsigned short vec_pack_to_short_fp32 (vector float, + vector float). + * config/rs6000/rs6000-builtin.def (CONVERT_4F32_8I16): Add + BU_P9V_AV_2 and BU_P9V_OVERLOAD_2 definitions. + * config/rs6000/altivec.h (vec_pack_to_short_fp32): Add define. + * config/rs6000/altivec.md(UNSPEC_CONVERT_4F32_8I16): Add UNSPEC. + (convert_4f32_8i16): Add define_expand. + * doc/extend.texi: Update the built-in documentation file for the + new built-in function. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/m8.md: New file. + * config/sparc/sparc.md: Include m8.md. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/sparc.opt: New option -mvis4b. + * config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B. + (sparc_option_override): Handle VIS4B. + (enum sparc_builtins): Define + SPARC_BUILTIN_DICTUNPACK{8,16,32}, + SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL, + SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL, + SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and + SPARC_BUILTIN_FPCMPUR{8,16,32}SHL. + (check_constant_argument): New function. + (sparc_vis_init_builtins): Define builtins + __builtin_vis_dictunpack{8,16,32}, + __builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl, + __builtin_vis_fpcmpu{le,gt}{8,16,32}shl, + __builtin_vis_fpcmpde{8,16,32}shl and + __builtin_vis_fpcmpur{8,16,32}shl. + (sparc_expand_builtin): Check that the constant operands to + __builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed + constant and in range. + * config/sparc/sparc-c.c (sparc_target_macros): Handle + TARGET_VIS4B. + * config/sparc/sparc.h (SPARC_IMM2_P): Define. + (SPARC_IMM5_P): Likewise. + * config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b". + (enabled): Handle vis4b. + (UNSPEC_DICTUNPACK): New unspec. + (UNSPEC_FPCMPSHL): Likewise. + (UNSPEC_FPUCMPSHL): Likewise. + (UNSPEC_FPCMPDESHL): Likewise. + (UNSPEC_FPCMPURSHL): Likewise. + (cpu_feature): New CPU feature `vis4b'. + (dictunpack{8,16,32}): New insns. + (FPCSMODE): New mode iterator. + (fpcscond): New code iterator. + (fpcsucond): Likewise. + (fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns. + (fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise. + (fpcmpde{8,16,32}{si,di}shl): Likewise. + (fpcmpur{8,16,32}{si,di}shl): Likewise. + * config/sparc/constraints.md: Define constraints `q' for unsigned + 2-bit integer constants and `t' for unsigned 5-bit integer + constants. + * config/sparc/predicates.md (imm5_operand_dictunpack8): New + predicate. + (imm5_operand_dictunpack16): Likewise. + (imm5_operand_dictunpack32): Likewise. + (imm2_operand): Likewise. + * doc/invoke.texi (SPARC Options): Document -mvis4b. + * doc/extend.texi (SPARC VIS Built-in Functions): Document the + ditunpack* and fpcmp*shl builtins. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config.gcc: Handle m8 in --with-{cpu,tune} options. + * config.in: Add HAVE_AS_SPARC6 define. + * config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC + M8. + * config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for + TARGET_CPU_m8. + (ASM_CPU32_DEFAUILT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle m8. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc-opts.h (enum processor_type): Add + PROCESSOR_M8. + * config/sparc/sparc.c (m8_costs): New struct. + (sparc_option_override): Handle TARGET_CPU_m8. + (sparc32_initialize_trampoline): Likewise. + (sparc64_initialize_trampoline): Likewise. + (sparc_issue_rate): Likewise. + (sparc_register_move_cost): Likewise. + * config/sparc/sparc.h (TARGET_CPU_m8): Define. + (CPP_CPU64_DEFAULT_SPEC): Define for M8. + (ASM_CPU64_DEFAULT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle M8. + (ASM_CPU_SPEC): Likewise. + (AS_M8_FLAG): Define. + * config/sparc/sparc.md: Add m8 to the cpu attribute. + * config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets. + * configure.ac (HAVE_AS_SPARC6): Check for assembler support for + M8 instructions. + * configure: Regenerate. + * doc/invoke.texi (SPARC Options): Document -mcpu=m8 and + -mtune=m8. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/niagara7.md: Rework the DFA scheduler to use insn + subtypes. + * config/sparc/sparc.md: Remove the `v3pipe' insn attribute. + ("*movdi_insn_sp32"): Do not set v3pipe. + ("*movsi_insn"): Likewise. + ("*movdi_insn_sp64"): Likewise. + ("*movsf_insn"): Likewise. + ("*movdf_insn_sp32"): Likewise. + ("*movdf_insn_sp64"): Likewise. + ("*zero_extendsidi2_insn_sp64"): Likewise. + ("*sign_extendsidi2_insn"): Likewise. + ("*mov<VM32:mode>_insn"): Likewise. + ("*mov<VM64:mode>_insn_sp64"): Likewise. + ("*mov<VM64:mode>_insn_sp32"): Likewise. + ("<plusminus_insn><VADDSUB:mode>3"): Likewise. + ("<vlop:code><VL:mode>3"): Likewise. + ("*not_<vlop:code><VL:mode>3"): Likewise. + ("*nand<VL:mode>_vis"): Likewise. + ("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise. + ("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise. + ("one_cmpl<VL:mode>2"): Likewise. + ("faligndata<VM64:mode>_vis"): Likewise. + ("alignaddrsi_vis"): Likewise. + ("alignaddrdi_vis"): Likweise. + ("alignaddrlsi_vis"): Likewise. + ("alignaddrldi_vis"): Likewise. + ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. + ("bmaskdi_vis"): Likewise. + ("bmasksi_vis"): Likewise. + ("bshuffle<VM64:mode>_vis"): Likewise. + ("cmask8<P:mode>_vis"): Likewise. + ("cmask16<P:mode>_vis"): Likewise. + ("cmask32<P:mode>_vis"): Likewise. + ("pdistn<P:mode>_vis"): Likewise. + ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/sparc.md ("subtype"): New insn attribute. + ("*wrgsr_sp64"): Set insn subtype. + ("*rdgsr_sp64"): Likewise. + ("alignaddrsi_vis"): Likewise. + ("alignaddrdi_vis"): Likewise. + ("alignaddrlsi_vis"): Likewise. + ("alignaddrldi_vis"): Likewise. + ("<plusminus_insn><VADDSUB:mode>3"): Likewise. + ("fexpand_vis"): Likewise. + ("fpmerge_vis"): Likewise. + ("faligndata<VM64:mode>_vis"): Likewise. + ("bshuffle<VM64:mode>_vis"): Likewise. + ("cmask8<P:mode>_vis"): Likewise. + ("cmask16<P:mode>_vis"): Likewise. + ("cmask32<P:mode>_vis"): Likewise. + ("fchksm16_vis"): Likewise. + ("v<vis3_shift_patname><GCM:mode>3"): Likewise. + ("fmean16_vis"): Likewise. + ("fp<plusminus_insn>64_vis"): Likewise. + ("<plusminus_insn>v8qi3"): Likewise. + ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. + ("<vis4_minmax_patname><VMMAX:mode>3"): Likewise. + ("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise. + ("<vis3_addsub_ss_patname>v8qi3"): Likewise. + ("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise. + ("*movqi_insn"): Likewise. + ("*movhi_insn"): Likewise. + ("*movsi_insn"): Likewise. + ("movsi_pic_gotdata_op"): Likewise. + ("*movdi_insn_sp32"): Likewise. + ("*movdi_insn_sp64"): Likewise. + ("movdi_pic_gotdata_op"): Likewise. + ("*movsf_insn"): Likewise. + ("*movdf_insn_sp32"): Likewise. + ("*movdf_insn_sp64"): Likewise. + ("*zero_extendhisi2_insn"): Likewise. + ("*zero_extendqihi2_insn"): Likewise. + ("*zero_extendqisi2_insn"): Likewise. + ("*zero_extendqidi2_insn"): Likewise. + ("*zero_extendhidi2_insn"): Likewise. + ("*zero_extendsidi2_insn_sp64"): Likewise. + ("ldfsr"): Likewise. + ("prefetch_64"): Likewise. + ("prefetch_32"): Likewise. + ("tie_ld32"): Likewise. + ("tie_ld64"): Likewise. + ("*tldo_ldub_sp32"): Likewise. + ("*tldo_ldub1_sp32"): Likewise. + ("*tldo_ldub2_sp32"): Likewise. + ("*tldo_ldub_sp64"): Likewise. + ("*tldo_ldub1_sp64"): Likewise. + ("*tldo_ldub2_sp64"): Likewise. + ("*tldo_ldub3_sp64"): Likewise. + ("*tldo_lduh_sp32"): Likewise. + ("*tldo_lduh1_sp32"): Likewise. + ("*tldo_lduh_sp64"): Likewise. + ("*tldo_lduh1_sp64"): Likewise. + ("*tldo_lduh2_sp64"): Likewise. + ("*tldo_lduw_sp32"): Likewise. + ("*tldo_lduw_sp64"): Likewise. + ("*tldo_lduw1_sp64"): Likewise. + ("*tldo_ldx_sp64"): Likewise. + ("*mov<VM32:mode>_insn"): Likewise. + ("*mov<VM64:mode>_insn_sp64"): Likewise. + ("*mov<VM64:mode>_insn_sp32"): Likewise. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/sparc.md ("type"): New insn type viscmp. + ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to + viscmp. + ("fpcmp<gcond:code>8<P:mode>_vis"): Likewise. + ("fucmp<gcond:code>8<P:mode>_vis"): Likewise. + ("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. + * config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle + viscmp. + ("n7_vis_logical_11cycle"): Likewise. + * config/sparc/niagara4.md ("n4_vis_logical"): Likewise. + * config/sparc/niagara2.md ("niag3_vis": Likewise. + * config/sparc/niagara.md ("niag_vis"): Likewise. + * config/sparc/ultra3.md ("us3_fga"): Likewise. + * config/sparc/ultra1_2.md ("us1_fga_double"): Likewise. + +2017-07-07 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/sparc.md: New instruction type `bmask'. + (bmaskdi_vis): Use the `bmask' type. + (bmasksi_vis): Likewise. + * config/sparc/ultra3.md (us3_array): Likewise. + * config/sparc/niagara7.md (n7_array): Likewise. + * config/sparc/niagara4.md (n4_array): Likewise. + * config/sparc/niagara2.md (niag2_vis): Likewise. + (niag3_vis): Likewise. + * config/sparc/niagara.md (niag_vis): Likewise. + +2017-07-06 Jan Hubicka <hubicka@ucw.cz> + + * ipa-comdats.c: Remove optimize check from gate. + * ipa-fnsummary.c (ipa_fn_summary_generate): do not generate summary + for functions not optimized. + (ipa_fn_summary_read): Skip optimize check. + (ipa_fn_summary_write): Likewise. + * ipa-inline-analysis.c (do_estimate_growth_1): Check that caller + is optimized. + * ipa-inline.c (can_inline_edge_p): Not optimized functions are + uninlinable. + (can_inline_edge_p): Check flag_pcc_struct_return for match. + (check_callers): Give up on caller which is not optimized. + (inline_small_functions): Likewise. + (ipa_inline): Do not give up when not optimizing. + * ipa-visbility.c (function_and_variable_visibility): Do not optimize + away unoptimizes cdtors. + (whole_program_function_and_variable_visibility): Do + ipa_discover_readonly_nonaddressable_vars in LTO mode. + * ipa.c (process_references): Do not check optimize. + (symbol_table::remove_unreachable_nodes): Update optimize check. + (set_writeonly_bit): Update optimize check. + (pass_ipa_cdtor_merge::gate): Do not check optimize. + (pass_ipa_single_use::gate): Remove. + +2017-07-06 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (union_defs, union_uses, insn_is_load_p, + insn_is_store_p, insn_is_swap_p, const_load_sequence_p, v2df_reduction_p, + rtx_is_swappable_p, insn_is_swappable_p, chain_contains_only_swaps, + mark_swaps_for_removal, swap_const_vector_halves, adjust_subreg_index, + permute_load, permute_store, adjust_extract, adjust_splat, + adjust_xxpermdi, adjust_concat, adjust_vperm, handle_special_swappables, + replace_swap_with_copy, dump_swap_insn_table, + alignment_with_canonical_addr, alignment_mask, find_alignment_op, + recombine_lvx_pattern, recombine_stvx_pattern, + recombine_lvx_stvx_patterns, rs6000_analyze_swaps, + make_pass_analyze_swaps): Move all code related to p8 swap optimizations + to file rs6000-p8swap.c. + * config/rs6000/rs6000-p8swap.c: New file. + * config/rs6000/t-rs6000: Add rule to build rs6000-p8swap.o. + * config.gcc: Add rs6000-p8swap.o to extra_objs for powerpc*-*-* + and rs6000*-*-* targets. + +2017-07-06 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (selftest): Remove dependency on s-selftest-c++. + +2017-07-06 Jan Hubicka <hubicka@ucw.cz> + + * lto-wrapper.c (merge_and_complain): Do not merge + fexceptions, fnon_call_exceptions, ftrapv, ffp_contract_, fmath_errno, + fsigned_zeros, ftrapping_math, fwrapv. + (append_compiler_options): Do not track these options. + (append_linker_options): Likewie + +2017-07-06 Jan Hubicka <hubicka@ucw.cz> + + * cgraphunit.c (cgraph_node::finalize_function): When + !flag_toplevel_reorde set no_reorder flag. + (varpool_node::finalize_decl): Likewise. + (symbol_table::compile): Drop no toplevel reorder path. + +2017-07-06 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (better_edge_p): Do not build traces across abnormal/eh + edges; zero probability is not better than uninitialized. + +2017-07-06 Maxim Ostapenko <m.ostapenko@samsung.com> + + * asan.h (asan_sanitize_allocas_p): Declare. + * asan.c (asan_sanitize_allocas_p): New function. + (handle_builtin_stack_restore): Bail out if !asan_sanitize_allocas_p. + (handle_builtin_alloca): Likewise. + * cfgexpand.c (expand_used_vars): Do not add allocas unpoisoning stuff + if !asan_sanitize_allocas_p. + * params.def (asan-instrument-allocas): Add new option. + * params.h (ASAN_PROTECT_ALLOCAS): Define. + * opts.c (common_handle_option): Disable allocas sanitization for + KASan by default. + +2017-07-06 Maxim Ostapenko <m.ostapenko@samsung.com> + + * asan.c: Include gimple-fold.h. + (get_last_alloca_addr): New function. + (handle_builtin_stackrestore): Likewise. + (handle_builtin_alloca): Likewise. + (asan_emit_allocas_unpoison): Likewise. + (get_mem_refs_of_builtin_call): Add new parameter, remove const + quallifier from first paramerer. Handle BUILT_IN_ALLOCA, + BUILT_IN_ALLOCA_WITH_ALIGN and BUILT_IN_STACK_RESTORE builtins. + (instrument_builtin_call): Pass gimple iterator to + get_mem_refs_of_builtin_call. + (last_alloca_addr): New global. + * asan.h (asan_emit_allocas_unpoison): Declare. + * builtins.c (expand_asan_emit_allocas_unpoison): New function. + (expand_builtin): Handle BUILT_IN_ASAN_ALLOCAS_UNPOISON. + * cfgexpand.c (expand_used_vars): Call asan_emit_allocas_unpoison + if function calls alloca. + * gimple-fold.c (replace_call_with_value): Remove static keyword. + * gimple-fold.h (replace_call_with_value): Declare. + * internal-fn.c: Include asan.h. + * sanitizer.def (BUILT_IN_ASAN_ALLOCA_POISON, + BUILT_IN_ASAN_ALLOCAS_UNPOISON): New builtins. + +2017-07-06 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (SELFTEST_FLAGS): Drop "-x c", moving it to... + (C_SELFTEST_FLAGS): New. + (CPP_SELFTEST_FLAGS): New. + (SELFTEST_DEPS): New, from deps of s-selftest. + (C_SELFTEST_DEPS): New, from deps of s-selftest. + (CPP_SELFTEST_DEPS): New. + (selftest): Add dependency on s-selftest-c++. + (s-selftest): Rename to... + (s-selftest-c): ...this, moving deps to SELFTEST_DEPS + and C_SELFTEST_DEPS, and using C_SELFTEST_FLAGS rather + than SELFTEST_FLAGS. + (selftest-gdb): Rename to... + (selftest-c-gdb): ...this, using C_SELFTEST_DEPS and + C_SELFTEST_FLAGS. + (selftest-gdb): Reintroduce as an alias for selftest-c-gdb. + (selftest-valgrind): Rename to... + (selftest-c-valgrind): ...this, using C_SELFTEST_DEPS and + C_SELFTEST_FLAGS. + (selftest-valgrind): Reintroduce as an alias for + selftest-c-valgrind. + (s-selftest-c++): New. + (selftest-c++-gdb): New. + (selftest-c++-valgrind): New. + +2017-07-06 Olivier Hainque <hainque@adacore.com> + + * gcc.c (process_command): When deciding if undefined variables + should be ignored when processing specs, accept "gcc -v" as well. + +2017-07-06 Jan Hubicka <hubicka@ucw.cz> + + * auto-profile.c (afdo_set_bb_count, afdo_propagate_edge, + afdo_annotate_cfg): Set counts/probabilities as determined by afdo. + +2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/arm-cpus.in (armv8-r): Add new entry. + * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R + enumerator. + * doc/invoke.texi: Mention -march=armv8-r and its extensions. + +2017-07-06 Carl Love <cel@us.ibm.com> + + * ChangeLog: Clean up from mid air collision + +2017-07-06 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for built-in functions + vector signed int vec_subc (vector signed int, vector signed int); + vector signed __int128 vec_subc (vector signed __int128, + vector signed __int128); + vector unsigned __int128 vec_subc (vector unsigned __int128, + vector unsigned __int128); + vector signed int vec_sube (vector signed int, vector signed int, + vector signed int); + vector unsigned int vec_sube (vector unsigned int, + vector unsigned int, + vector unsigned int); + vector signed __int128 vec_sube (vector signed __int128, + vector signed __int128, + vector signed__int128); + vector unsigned __int128 vec_sube (vector unsigned __int128, + vector unsigned __int128, + vector unsigned __int128); + vector signed int vec_subec (vector signed int, vector signed int, + vector signed int); + vector unsigned int vec_subec (vector unsigned int, + vector unsigned int, + vector unsigned int); + vector signed __int128 vec_subec (vector signed __int128, + vector signed __int128, + vector signed__int128); + vector unsigned __int128 vec_subec (vector unsigned __int128, + vector unsigned __int128, + vector unsigned __int128); + * config/rs6000/rs6000.c (ALTIVEC_BUILTIN_VEC_SUBE, + ALTIVEC_BUILTIN_VEC_SUBEC): Add ef_builtins. + * config/rs6000/rs6000-builtin.def (SUBE, SUBEC): Add + BU_ALTIVEC_OVERLOAD_X definitions. + * config/rs6000/altivec.h (vec_sube, vec_subec): Add builtin defines. + * doc/extend.texi: Update the built-in documentation file for the new + built-in functions. + +2017-07-06 David Malcolm <dmalcolm@redhat.com> + + PR c++/79300 + * diagnostic-show-locus.c (layout::layout): Use start and finish + spelling location for the start and finish of each range. + * genmatch.c (linemap_client_expand_location_to_spelling_point): + Add unused aspect param. + * input.c (expand_location_1): Add "aspect" param, and use it + to access the correct part of the location. + (expand_location): Pass LOCATION_ASPECT_CARET to new param of + expand_location_1. + (expand_location_to_spelling_point): Likewise. + (linemap_client_expand_location_to_spelling_point): Add "aspect" + param, and pass it to expand_location_1. + +2017-07-06 Sebastian Peryt <sebastian.peryt@intel.com> + + * config/i386/avx512fintrin.h (_mm_mask_getexp_round_ss, + _mm_maskz_getexp_round_ss, _mm_mask_getexp_round_sd, + _mm_maskz_getexp_round_sd, _mm_mask_getmant_round_sd, + _mm_maskz_getmant_round_sd, _mm_mask_getmant_round_ss, + _mm_maskz_getmant_round_ss, _mm_mask_getexp_ss, _mm_maskz_getexp_ss, + _mm_mask_getexp_sd, _mm_maskz_getexp_sd, _mm_mask_getmant_sd, + _mm_maskz_getmant_sd, _mm_mask_getmant_ss, + _mm_maskz_getmant_ss): New intrinsics. + (__builtin_ia32_getexpss128_mask): Changed to ... + __builtin_ia32_getexpss128_round ... this. + (__builtin_ia32_getexpsd128_mask): Changed to ... + __builtin_ia32_getexpsd128_round ... this. + * config/i386/i386-builtin-types.def + ((V2DF, V2DF, V2DF, INT, V2DF, UQI, INT), + (V4SF, V4SF, V4SF, INT, V4SF, UQI, INT)): New function type aliases. + * config/i386/i386-builtin.def (__builtin_ia32_getexpsd_mask_round, + __builtin_ia32_getexpss_mask_round, __builtin_ia32_getmantsd_mask_round, + __builtin_ia32_getmantss_mask_round): New builtins. + * config/i386/i386.c (V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI_INT, + V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI_INT): Handle new types. + (CODE_FOR_avx512f_vgetmantv2df_mask_round, + CODE_FOR_avx512f_vgetmantv4sf_mask_round): New cases. + * config/i386/sse.md + (avx512f_sgetexp<mode><round_saeonly_name>): Changed to ... + avx512f_sgetexp<mode><mask_scalar_name> + <round_saeonly_scalar_name> ... this. + (vgetexp<ssescalarmodesuffix>\t{<round_saeonly_op3>%2, %1, %0| + %0, %1, %2<round_saeonly_op3>}): Changed to ... + vgetexp<ssescalarmodesuffix> + \t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>| + %0<mask_scalar_operand3>, %1, %2<round_saeonly_scalar_mask_op3>} ... this. + (avx512f_vgetmant<mode><round_saeonly_name>): Changed to ... + avx512f_vgetmant<mode><mask_scalar_name> + <round_saeonly_scalar_name> ... this. + (vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0| + %0, %1, %2<round_saeonly_op4>, %3}): Changed to ... + vgetmant<ssescalarmodesuffix> + \t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>| + %0<mask_scalar_operand4>, %1, %2 + <round_saeonly_scalar_mask_op4>, %3} ... this. + * config/i386/subst.md (mask_scalar_operand4, + round_saeonly_scalar_mask_operand4, round_saeonly_scalar_mask_op4, + round_saeonly_scalar_nimm_predicate): New subst attributes. + +2017-07-06 Julia Koval <julia.koval@intel.com> + + * config/i386/i386.c (ix86_erase_embedded_rounding): + Remove code for old rounding pattern. + +2017-07-06 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/t-arm (GTM_H): Add arm-cpu.h. + +2017-07-06 Christophe Lyon <christophe.lyon@linaro.org> + + * doc/sourcebuild.texi (Test Directives, Variants of + dg-require-support): Add documentation for dg-require-stack-check. + +2017-07-05 Sebastian Peryt <sebastian.peryt@intel.com> + + * config/i386/subst.md (mask_scalar, round_scalar, + round_saeonly_scalar): New meta-templates. + (mask_scalar_name, mask_scalar_operand3, round_scalar_name, + round_scalar_mask_operand3, round_scalar_mask_op3, + round_scalar_constraint, round_scalar_prefix, round_saeonly_scalar_name, + round_saeonly_scalar_mask_operand3, round_saeonly_scalar_mask_op3, + round_saeonly_scalar_constraint, + round_saeonly_scalar_prefix): New subst attribute. + * config/i386/sse.md + (<sse>_vm<plusminus_insn><mode>3<mask_name><round_name>): Renamed to ... + <sse>_vm<plusminus_insn><mode>3<mask_scalar_name> + <round_scalar_name> ... this. + (<sse>_vm<multdiv_mnemonic><mode>3<mask_name><round_name>): Renamed to ... + <sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name> + <round_scalar_name> ... this. + (<sse>_vm<code><mode>3<mask_name><round_saeonly_name>): Renamed to ... + <sse>_vm<code><mode>3<mask_scalar_name> + <round_saeonly_scalar_name> ... this. + (v<plusminus_mnemonic><ssescalarmodesuffix> + \t{<round_mask_op3>%2, %1, %0<mask_operand3>| + %0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ... + v<plusminus_mnemonic><ssescalarmodesuffix> + \t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>| + %0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this. + (v<multdiv_mnemonic><ssescalarmodesuffix> + \t{<round_mask_op3>%2, %1, %0<mask_operand3>| + %0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ... + v<multdiv_mnemonic><ssescalarmodesuffix> + \t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>| + %0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this. + (v<maxmin_float><ssescalarmodesuffix> + \t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>| + %0<mask_operand3>, %1, %<iptr>2<round_saeonly_mask_op3>}): Changed to ... + v<maxmin_float><ssescalarmodesuffix> + \t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>| + %0<mask_scalar_operand3>, %1, %<iptr>2 + <round_saeonly_scalar_mask_op3>} ... this. + +2017-07-05 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.c (arm_fixed_condition_code_regs): New function. + (TARGET_FIXED_CONDITION_CODE_REGS): Redefine. + +2017-07-05 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + + * combine.c (simplify_if_then_else): Remove "enum" before + "machine_mode". + * compare-elim.c (can_eliminate_compare): Likewise. + * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type): + Likewise. + (aarch64_lookup_simd_builtin_type): Likewise. + (aarch64_simd_builtin_type): Likewise. + (aarch64_init_simd_builtin_types): Likewise. + (aarch64_simd_expand_args): Likewise. + * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist): + Likewise. + (aarch64_reverse_mask): Likewise. + (aarch64_simd_emit_reg_reg_move): Likewise. + (aarch64_gen_adjusted_ldpstp): Likewise. + (aarch64_ccmp_mode_to_code): Likewise. + (aarch64_operands_ok_for_ldpstp): Likewise. + (aarch64_operands_adjust_ok_for_ldpstp): Likewise. + * config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class): + Likewise. + (aarch64_min_divisions_for_recip_mul): Likewise. + (aarch64_reassociation_width): Likewise. + (aarch64_get_condition_code_1): Likewise. + (aarch64_simd_emit_reg_reg_move): Likewise. + (aarch64_simd_attr_length_rglist): Likewise. + (aarch64_reverse_mask): Likewise. + (aarch64_operands_ok_for_ldpstp): Likewise. + (aarch64_operands_adjust_ok_for_ldpstp): Likewise. + (aarch64_gen_adjusted_ldpstp): Likewise. + * config/aarch64/cortex-a57-fma-steering.c (fma_node::rename): + Likewise. + * config/arc/arc.c (legitimate_offset_address_p): Likewise. + * config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise. + (arm_lookup_simd_builtin_type): Likewise. + (arm_simd_builtin_type): Likewise. + (arm_init_simd_builtin_types): Likewise. + (arm_expand_builtin_args): Likewise. + * config/arm/arm-protos.h (arm_expand_builtin): Likewise. + * config/ft32/ft32.c (ft32_libcall_value): Likewise. + (ft32_setup_incoming_varargs): Likewise. + (ft32_function_arg): Likewise. + (ft32_function_arg_advance): Likewise. + (ft32_pass_by_reference): Likewise. + (ft32_arg_partial_bytes): Likewise. + (ft32_valid_pointer_mode): Likewise. + (ft32_addr_space_pointer_mode): Likewise. + (ft32_addr_space_legitimate_address_p): Likewise. + * config/i386/i386-protos.h (ix86_operands_ok_for_move_multiple): + Likewise. + * config/i386/i386.c (ix86_setup_incoming_vararg_bounds): Likewise. + (ix86_emit_outlined_ms2sysv_restore): Likewise. + (iamcu_alignment): Likewise. + (canonicalize_vector_int_perm): Likewise. + (ix86_noce_conversion_profitable_p): Likewise. + (ix86_mpx_bound_mode): Likewise. + (ix86_operands_ok_for_move_multiple): Likewise. + * config/microblaze/microblaze-protos.h + (microblaze_expand_conditional_branch_reg): Likewise. + * config/microblaze/microblaze.c + (microblaze_expand_conditional_branch_reg): Likewise. + * config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok): + Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_invalid_binary_op): Likewise. + (fusion_p9_p): Likewise. + (emit_fusion_p9_load): Likewise. + (emit_fusion_p9_store): Likewise. + * config/riscv/riscv-protos.h (riscv_regno_mode_ok_for_base_p): + Likewise. + (riscv_hard_regno_mode_ok_p): Likewise. + (riscv_address_insns): Likewise. + (riscv_split_symbol): Likewise. + (riscv_legitimize_move): Likewise. + (riscv_function_value): Likewise. + (riscv_hard_regno_nregs): Likewise. + (riscv_expand_builtin): Likewise. + * config/riscv/riscv.c (riscv_build_integer_1): Likewise. + (riscv_build_integer): Likewise. + (riscv_split_integer): Likewise. + (riscv_legitimate_constant_p): Likewise. + (riscv_cannot_force_const_mem): Likewise. + (riscv_regno_mode_ok_for_base_p): Likewise. + (riscv_valid_base_register_p): Likewise. + (riscv_valid_offset_p): Likewise. + (riscv_valid_lo_sum_p): Likewise. + (riscv_classify_address): Likewise. + (riscv_legitimate_address_p): Likewise. + (riscv_address_insns): Likewise. + (riscv_load_store_insns): Likewise. + (riscv_force_binary): Likewise. + (riscv_split_symbol): Likewise. + (riscv_force_address): Likewise. + (riscv_legitimize_address): Likewise. + (riscv_move_integer): Likewise. + (riscv_legitimize_const_move): Likewise. + (riscv_legitimize_move): Likewise. + (riscv_address_cost): Likewise. + (riscv_subword): Likewise. + (riscv_output_move): Likewise. + (riscv_canonicalize_int_order_test): Likewise. + (riscv_emit_int_order_test): Likewise. + (riscv_function_arg_boundary): Likewise. + (riscv_pass_mode_in_fpr_p): Likewise. + (riscv_pass_fpr_single): Likewise. + (riscv_pass_fpr_pair): Likewise. + (riscv_get_arg_info): Likewise. + (riscv_function_arg): Likewise. + (riscv_function_arg_advance): Likewise. + (riscv_arg_partial_bytes): Likewise. + (riscv_function_value): Likewise. + (riscv_pass_by_reference): Likewise. + (riscv_setup_incoming_varargs): Likewise. + (riscv_print_operand): Likewise. + (riscv_elf_select_rtx_section): Likewise. + (riscv_save_restore_reg): Likewise. + (riscv_for_each_saved_reg): Likewise. + (riscv_register_move_cost): Likewise. + (riscv_hard_regno_mode_ok_p): Likewise. + (riscv_hard_regno_nregs): Likewise. + (riscv_class_max_nregs): Likewise. + (riscv_memory_move_cost): Likewise. + * config/rl78/rl78-protos.h (rl78_split_movsi): Likewise. + * config/rl78/rl78.c (rl78_split_movsi): Likewise. + (rl78_addr_space_address_mode): Likewise. + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Likewise. + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_invalid_binary_op): Likewise. + (fusion_p9_p): Likewise. + (emit_fusion_p9_load): Likewise. + (emit_fusion_p9_store): Likewise. + * config/visium/visium-protos.h (prepare_move_operands): Likewise. + (ok_for_simple_move_operands): Likewise. + (ok_for_simple_move_strict_operands): Likewise. + (ok_for_simple_arith_logic_operands): Likewise. + (visium_legitimize_reload_address): Likewise. + (visium_select_cc_mode): Likewise. + (output_cbranch): Likewise. + (visium_split_double_move): Likewise. + (visium_expand_copysign): Likewise. + (visium_expand_int_cstore): Likewise. + (visium_expand_fp_cstore): Likewise. + * config/visium/visium.c (visium_pass_by_reference): Likewise. + (visium_function_arg): Likewise. + (visium_function_arg_advance): Likewise. + (visium_libcall_value): Likewise. + (visium_setup_incoming_varargs): Likewise. + (visium_legitimate_constant_p): Likewise. + (visium_legitimate_address_p): Likewise. + (visium_legitimize_address): Likewise. + (visium_secondary_reload): Likewise. + (visium_register_move_cost): Likewise. + (visium_memory_move_cost): Likewise. + (prepare_move_operands): Likewise. + (ok_for_simple_move_operands): Likewise. + (ok_for_simple_move_strict_operands): Likewise. + (ok_for_simple_arith_logic_operands): Likewise. + (visium_function_value_1): Likewise. + (rtx_ok_for_offset_p): Likewise. + (visium_legitimize_reload_address): Likewise. + (visium_split_double_move): Likewise. + (visium_expand_copysign): Likewise. + (visium_expand_int_cstore): Likewise. + (visium_expand_fp_cstore): Likewise. + (visium_split_cstore): Likewise. + (visium_select_cc_mode): Likewise. + (visium_split_cbranch): Likewise. + (output_cbranch): Likewise. + (visium_print_operand_address): Likewise. + * expmed.c (flip_storage_order): Likewise. + * expmed.h (emit_cstore): Likewise. + (flip_storage_order): Likewise. + * genrecog.c (validate_pattern): Likewise. + * hsa-gen.c (gen_hsa_addr): Likewise. + * internal-fn.c (expand_arith_overflow): Likewise. + * ira-color.c (allocno_copy_cost_saving): Likewise. + * lra-assigns.c (find_hard_regno_for_1): Likewise. + * lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise. + (process_invariant_for_inheritance): Likewise. + * lra-eliminations.c (move_plus_up): Likewise. + * omp-low.c (lower_oacc_reductions): Likewise. + * simplify-rtx.c (simplify_subreg): Likewise. + * target.def (TARGET_SETUP_INCOMING_VARARG_BOUNDS): Likewise. + (TARGET_CHKP_BOUND_MODE): Likewise.. + * targhooks.c (default_chkp_bound_mode): Likewise. + (default_setup_incoming_vararg_bounds): Likewise. + * targhooks.h (default_chkp_bound_mode): Likewise. + (default_setup_incoming_vararg_bounds): Likewise. + * tree-ssa-math-opts.c (divmod_candidate_p): Likewise. + * tree-vect-loop.c (calc_vec_perm_mask_for_shift): Likewise. + (have_whole_vector_shift): Likewise. + * tree-vect-stmts.c (vectorizable_load): Likewise. + * doc/tm.texi: Regenerate. + +2017-07-05 Georg-Johann Lay <avr@gjlay.de> + + Graceful degrade if Binutils PR21472 is not available. + + PR target/81072 + * configure.ac [target=avr]: WARN instead of ERROR if avrxmega3 + .rodata in flash test fails. + (HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH): Define it if test passes. + * confgure: Regenerate. + * config.in: Regenerate. + * config/avr/avr.c (avr_asm_named_section) + [HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH]: Only trigger + __do_copy_data for stuff in .rodata if flash_pm_offset = 0. + (avr_asm_init_sections): Same. + +2017-07-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * config/arm/neon.md (fma<VCVTF:mode>4): Remove %?. + (fma<VH:mode>4_intrinsic): Likewise. + (*fmsub<VCVTF:mode>4): Likewise. + (*fmsub<VH:mode>4_intrinsic): Likewise. + +2017-07-05 Georg-Johann Lay <avr@gjlay.de> + + PR target/81305 + * config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]: + Don't depend on "optimize > 0". + (out_movhi_r_mr, out_movqi_mr_r): Same. + (out_movhi_mr_r, out_movqi_r_mr): Same. + (avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for + io_address_operand on "optimize > 0". + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c: Add general explanantion on the pass. + (generate_loops_for_partition): Mark distributed loop. + (pg_add_dependence_edges): New parameter. Handle alias data + dependence specially and record it in the parameter if asked. + (struct pg_vdata, pg_edata, pg_edge_callback_data): New structs. + (init_partition_graph_vertices, add_partition_graph_edge): New. + (pg_skip_alias_edge, free_partition_graph_edata_cb): New. + (free_partition_graph_vdata, build_partition_graph): New. + (sort_partitions_by_post_order, merge_dep_scc_partitions): New. + (pg_collect_alias_ddrs, break_alias_scc_partitions): New. + (data_ref_segment_size, latch_dominated_by_data_ref): New. + (compute_alias_check_pairs, version_loop_by_alias_check): New. + (version_for_distribution_p, finalize_partitions): New. + (distribute_loop): Handle alias data dependence specially. Factor + out loop fusion code as functions and call these functions. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (classify_partition): New parameter and + better handle reduction statement. + (rdg_build_partitions): Revise comment. + (distribute_loop): Compute statements in all partitions and pass it + to classify_partition. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (enum partition_type): New. + (struct partition): New field type. + (partition_merge_into): Add parameter. Update partition type. + (data_dep_in_cycle_p, update_type_for_merge): New functions. + (build_rdg_partition_for_vertex): Compute partition type. + (rdg_build_partitions): Dump partition type. + (distribute_loop): Update calls to partition_merge_into. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (struct ddr_hasher): New. + (ddr_hasher::hash, ::equal, get_data_dependence): New function. + (ddrs_table): New. + (classify_partition): Call get_data_dependence. + (pg_add_dependence_edges): Ditto. + (distribute_loop): Release data dependence hash table. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (ref_base_address): Delete. + (similar_memory_accesses): Rename ... + (share_memory_accesses): ... to this. Check if partitions access + the same memory reference. + (distribute_loop): Call share_memory_accesses. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (struct partition): New field recording + its data reference. + (partition_alloc, partition_free): Init and release data refs. + (partition_merge_into): Merge data refs. + (build_rdg_partition_for_vertex): Collect data refs for partition. + (pg_add_dependence_edges): Change parameters from vector to bitmap. + Update uses. + (distribute_loop): Remve data refs from vertice data of partition + graph. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (params.h): Include header file. + (MAX_DATAREFS_NUM, DR_INDEX): New macro. + (datarefs_vec): New global var. + (create_rdg_vertices): Use datarefs_vec directly. + (free_rdg): Don't free data references. + (build_rdg): Update use. Don't free data references. + (distribute_loop): Compute global variable for data references. + Bail out if there are too many data references. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (loop_nest): New global var. + (build_rdg): Use loop directly, rather than loop nest. + (pg_add_dependence_edges): Remove loop nest parameter. Use global + variable directly. + (distribute_loop): Compute global variable loop nest. Update use. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (enum fuse_type, fuse_message): New. + (partition_merge_into): New parameter. Dump reason for fusion. + (distribute_loop): Update use of partition_merge_into. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (bb_top_order_index): New. + (bb_top_order_index_size, bb_top_order_cmp): New. + (stmts_from_loop): Use topological order. + (pass_loop_distribution::execute): Compute and release topological + order for basic blocks. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * tree-loop-distribution.c (pass_loop_distribution::execute): Skip + if no loops. + +2017-07-05 Bin Cheng <bin.cheng@arm.com> + + * cfgloop.h (struct loop): Add comment. New field orig_loop_num. + * cfgloopmanip.c (lv_adjust_loop_entry_edge): Comment change. + * internal-fn.c (expand_LOOP_DIST_ALIAS): New function. + * internal-fn.def (LOOP_DIST_ALIAS): New. + * tree-vectorizer.c (fold_loop_vectorized_call): Rename to ... + (fold_loop_internal_call): ... this. + (vect_loop_dist_alias_call): New function. + (set_uid_loop_bbs): Call fold_loop_internal_call. + (vectorize_loops): Fold IFN_LOOP_VECTORIZED and IFN_LOOP_DIST_ALIAS + internal calls. + +2017-07-04 Uros Bizjak <ubizjak@gmail.com> + + PR target/81300 + * config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes): + Require dead FLAGS_REG at the beginning of a peephole. + +2017-07-04 Uros Bizjak <ubizjak@gmail.com> + + PR target/81294 + * config/i386/adxintrin.h (_subborrow_u32): Swap _X and _Y + arguments in the call to __builtin_ia32_sbb_u32. + (_subborrow_u64): Swap _X and _Y arguments in the call to + __builtin_ia32_sbb_u64. + +2017-07-04 Jakub Jelinek <jakub@redhat.com> + + PR debug/81278 + * tree-vrp.c (compare_assert_loc): Turn into a function template + with stable template parameter. Only test if a->e is NULL, + !a->e == !b->e has been verified already. Use e == NULL or + e != NULL instead of e or ! e tests. If stable is true, don't use + iterative_hash_expr, on the other side allow a or b or both NULL + and sort the NULLs last. + (process_assert_insertions): Sort using compare_assert_loc<false> + instead of compare_assert_loc, later sort using + compare_assert_loc<true> before calling process_assert_insertions_for + in a loop. Use break instead of continue once seen NULL pointer. + +2017-07-04 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM + Cortex-R7 and Cortex-R8 processors. + +2017-07-04 Jan Hubicka <hubicka@ucw.cz> + + * ipa-utils.c (ipa_merge_profiles): Fix merging when dst is + uninitialized while src is not. + +2017-07-04 Richard Earnshaw <rearnsha@arm.com> + + * common/config/arm/arm-common.c: Adjust include path for + arm-cpu-cdata.h + * config/arm/t-arm (TM_H): Adjust path for arm-cpu.h. + (arm-cpu.h): Create in build directory. Adjust dependency rules. + (arm-cpu-data.h): Likewise. + (arm-cpu-cdata.h): Likewise. + * config/arm/arm-cpu.h: Delete. + * config/arm/arm-cpu-cdata.h: Delete. + * config/arm/arm-cpu-data.h: Delete. + +2017-07-04 James Greenhalgh <james.greenhalgh@arm.com> + + * config/arm/arm-cpus.in (cortex-a55): New. + (cortex-a75): Likewise. + (cortex-a75.cortex-a55): Likewise. + * config/arm/driver-arm.c (arm_cpu_table): Add cortex-a55 and + cortex-a75. + * doc/invoke.texi (-mcpu): Document cortex-a55 and cortex-a75. + * config/arm/arm-cpu-cdata.h: Regenerate. + * config/arm/arm-cpu-data.h: Regenerate. + * config/arm/arm-cpu.h: Regenerate. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Regenerate. + +2017-07-04 Jan Hubicka <hubicka@ucw.cz> + + * haifa-sched.c (sched_create_recovery_edges): Update profile. + +2017-07-04 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (better_edge_p): Fix handling of uninitialized + probability. + +2017-07-04 Richard Sandiford <richard.sandiford@linaro.org> + + PR tree-optimization/81292 + * tree-ssa-strlen.c (handle_builtin_strlen): When setting + full_string_p, also call adjust_related_strinfos if the adjustment + is simple, otherwise invalidate related strinfos. + +2017-07-04 Martin Liska <mliska@suse.cz> + + PR sanitizer/81040 + * sanopt.c (sanitize_rewrite_addressable_params): Mark the + newly created variable as DECL_IGNORED_P. + +2017-07-04 Martin Liska <mliska@suse.cz> + + PR ipa/81293 + * ipa-inline.c (inline_small_functions): + Use xstrdup_for_dump. + +2017-07-04 Tom de Vries <tom@codesourcery.com> + + * graph.c (draw_cfg_edges): Save and restore EDGE_DFS_BACK. + +2017-07-03 Dominique d'Humieres <dominiq@lps.ens.fr> + + PR target/81033 + * config/darwin.c (darwin_function_switched_text_sections): + Fix spaces. + +2017-07-03 Jan Hubicka <hubicka@ucw.cz> + + * tree-vect-loop-manip.c (vect_do_peeling): Fix scaling up. + +2017-07-03 Richard Earnshaw <rearnsha@arm.com> + + * doc/invoke.texi (ARM Options): Add -mbe8 and -mbe32 to option summary. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-vect-loop.c (vect_analyze_loop_2): Treat min_scalar_loop_bound, + min_profitable_iters, and th as inclusive lower bounds. + Fix LOOP_VINFO_PEELING_FOR_GAPS condition. + (vect_estimate_min_profitable_iters): Return inclusive lower bounds + for min_profitable_iters and min_profitable_estimate. + (vect_transform_loop): Treat th as an inclusive lower bound. + * tree-vect-loop-manip.c (vect_loop_versioning): Likewise. + +2017-07-03 Dominique d'Humieres <dominiq@lps.ens.fr> + + PR target/81033 + * config/darwin.c (darwin_function_switched_text_sections): + Replace DECL_NAME with DECL_ASSEMBLER_NAME, split assemble_name_raw + in two pieces, and suppress the use of buf. + +2017-07-03 Nathan Sidwell <nathan@acm.org> + + * hash-table.h (hash_table_mod1): Fix indentation. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/81290 + * predict.c (force_edge_cold): Be more careful about propagation + backward. + * profile-count.h (profile_probability::guessed, + profile_probability::fdo, profile_count::guessed, profile_count::fdo): + New. + * tree-ssa-threadupdate.c (recompute_probabilities): Result is guessed. + +2017-07-03 James Greenhalgh <james.greenhalgh@arm.com> + + * doc/invoke.texi (rcpc architecture extension): Document it. + +2017-07-03 Richard Biener <rguenther@suse.de> + + PR tree-optimization/60510 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Pass in + the scalar reduction PHI and use it. + (vectorizable_reduction): Properly guard the single_defuse_cycle + path for non-SLP reduction chains where we cannot use it. + Rework reduc_def/index and vector type deduction. Rework + vector operand gathering during reduction op code-gen. + * tree-vect-slp.c (vect_analyze_slp): For failed SLP reduction + chains dissolve the chain and leave it to non-SLP reduction + handling. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.h (dr_alignment): Declare. + * tree-data-ref.c (dr_alignment): New function. + * tree-vectorizer.h (dataref_aux): Remove base_element_aligned. + * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Don't + set it. + * tree-vect-stmts.c (vectorizable_store): Use dr_alignment. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.h (innermost_loop_behavior): Add base_alignment + and base_misalignment fields. + (DR_BASE_ALIGNMENT, DR_BASE_MISALIGNMENT): New macros. + * tree-data-ref.c: Include builtins.h. + (dr_analyze_innermost): Set up the new innmost_loop_behavior fields. + * tree-vectorizer.h (STMT_VINFO_DR_BASE_ALIGNMENT): New macro. + (STMT_VINFO_DR_BASE_MISALIGNMENT): Likewise. + * tree-vect-data-refs.c: Include tree-cfg.h. + (vect_compute_data_ref_alignment): Use the new innermost_loop_behavior + fields instead of calculating an alignment here. + (vect_analyze_data_refs): Use dr_analyze_innermost. Dump the new + innermost_loop_behavior fields. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.h (innermost_loop_behavior): Add a step_alignment + field. + (DR_STEP_ALIGNMENT): New macro. + * tree-vectorizer.h (STMT_VINFO_DR_STEP_ALIGNMENT): Likewise. + * tree-data-ref.c (dr_analyze_innermost): Initalize step_alignment. + (create_data_ref): Print it. + * tree-vect-stmts.c (vectorizable_load): Use the step alignment + to tell whether the step preserves vector (mis)alignment. + * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Likewise. + Move the check for an integer step and generalise to all INTEGER_CST. + (vect_analyze_data_refs): Set DR_STEP_ALIGNMENT when setting DR_STEP. + Print the outer step alignment. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.h (innermost_loop_behavior): Replace aligned_to + with offset_alignment. + (DR_ALIGNED_TO): Delete. + (DR_OFFSET_ALIGNMENT): New macro. + * tree-vectorizer.h (STMT_VINFO_DR_ALIGNED_TO): Delete. + (STMT_VINFO_DR_OFFSET_ALIGNMENT): New macro. + * tree-data-ref.c (dr_analyze_innermost): Update after above changes. + (create_data_ref): Likewise. + * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Likewise. + (vect_analyze_data_refs): Likewise. + * tree-if-conv.c (if_convertible_loop_p_1): Use memset before + creating dummy innermost behavior. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.h (dr_analyze_innermost): Replace the dr argument + with a "innermost_loop_behavior *" and refeence tree. + * tree-data-ref.c (dr_analyze_innermost): Likewise. + (create_data_ref): Update call accordingly. + * tree-predcom.c (find_looparound_phi): Likewise. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-vectorizer.h (_stmt_vec_info): Replace individual dr_* + fields with dr_wrt_vec_loop. + (STMT_VINFO_DR_BASE_ADDRESS, STMT_VINFO_DR_INIT, STMT_VINFO_DR_OFFSET) + (STMT_VINFO_DR_STEP, STMT_VINFO_DR_ALIGNED_TO): Update accordingly. + (STMT_VINFO_DR_WRT_VEC_LOOP): New macro. + (vect_dr_behavior): New function. + (vect_create_addr_base_for_vector_ref): Remove loop parameter. + * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Use + vect_dr_behavior. Use a step_preserves_misalignment_p boolean to + track whether the step preserves the misalignment. + (vect_create_addr_base_for_vector_ref): Remove loop parameter. + Use vect_dr_behavior. + (vect_setup_realignment): Update call accordingly. + (vect_create_data_ref_ptr): Likewise. Use vect_dr_behavior. + * tree-vect-loop-manip.c (vect_gen_prolog_loop_niters): Update + call to vect_create_addr_base_for_vector_ref. + (vect_create_cond_for_align_checks): Likewise. + * tree-vect-patterns.c (vect_recog_bool_pattern): Copy + STMT_VINFO_DR_WRT_VEC_LOOP as a block. + (vect_recog_mask_conversion_pattern): Likewise. + * tree-vect-stmts.c (compare_step_with_zero): Use vect_dr_behavior. + (new_stmt_vec_info): Remove redundant zeroing. + +2017-07-03 Richard Earnshaw <rearnsha@arm.com> + + * common/config/arm/arm-common.c (arm_be8_option): New function. + * config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8. + (ISA_ARMv6): Add isa_bit_be8. + * config/arm/arm.h (arm_be8_option): Add prototype. + (BE8_SPEC_FUNCTION): New define. + (EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION. + * config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian. + (mlittle-endian): Similarly. + (mbe8, mbe32): New options. + * config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option. + * doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * tree-cfg.c (gimple_find_sub_bbs): Fix profile updating. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * tree-cfgcleanup.c (want_merge_blocks_p): New function. + (cleanup_tree_cfg_bb): Use it. + * profile-count.h (profile_count::of_for_merging, profile_count::merge): + New functions. + * tree-cfg.c (gimple_merge_blocks): Use profile_count::merge. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + PR bootstrap/81285 + * loop-doloop.c (add_test): Update profile. + +2017-07-03 Martin Liska <mliska@suse.cz> + + PR sanitize/81040 + * sanopt.c (rewrite_usage_of_param): New function. + (sanitize_rewrite_addressable_params): Likewise. + (pass_sanopt::execute): Call rewrite_usage_of_param. + +2017-07-03 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.c (vect_create_epilog_for_reduction): Revert + back to using VIEW_CONVERT_EXPR. + +2017-07-03 Martin Liska <mliska@suse.cz> + + PR other/78366 + * doc/extend.texi: Document when a resolver function is + generated for target_clones. + +2017-07-03 Martin Liska <mliska@suse.cz> + + * asan.c (asan_emit_stack_protection): Unpoison just red zones + and shadow memory of auto variables which are subject of + use-after-scope sanitization. + (asan_expand_mark_ifn): Add do set only when is_poison. + +2016-07-03 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.c (vect_analyze_loop_operations): Also analyze + reduction PHIs. + (vect_force_simple_reduction): Record reduction def -> phi mapping. + (vectorizable_reduction): Perform reduction PHI creation when + visiting a reduction PHI and adjust and simplify code generation + phase of the reduction op. Cache dts, use fold_binary, not fold_build2. + (vect_transform_loop): Visit reduction PHIs. + * tree-vect-slp.c (vect_get_and_check_slp_defs): Record reduction + defs into the SLP tree. + (vect_build_slp_tree): Reduction defs terminate the recursion. + * tree-vect-stmts.c (vect_get_vec_def_for_operand_1): Allow lookup + of reduction defs. + (vect_get_vec_defs_for_stmt_copy): Export. + (vect_get_vec_defs): Likewise. + * tree-vectorizer.h (struct _stmt_vec_info): Amend reduc_def + purpose. + (vect_get_vec_defs_for_stmt_copy): Declare. + (vect_get_vec_defs): Likewise. + +2017-07-03 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-data-ref.c (dr_analyze_innermost): Replace the "nest" + parameter with a "loop" parameter and use it instead of the + loop containing DR_STMT. Don't check simple_iv when doing + BB analysis. Describe the two analysis modes in the comment. + +2017-07-03 Tom de Vries <tom@codesourcery.com> + + PR tree-optimization/69468 + * tree-ssa-tail-merge.c (ignore_edge_flags): New constant. + (find_same_succ_bb): Handle ignore_edge_flags. + +2017-07-03 Tom de Vries <tom@codesourcery.com> + + PR tree-optimization/81192 + * tree-ssa-tail-merge.c (same_succ_hash): Use bb->loop_father->num in + hash. + (same_succ::equal): Don't find bbs to be equal if bb->loop_father + differs. + (find_same_succ_bb): Remove obsolete test on bb->loop_father->latch. + +2017-07-03 Tom de Vries <tom@codesourcery.com> + + PR tree-optimization/81192 + * tree-ssa-tail-merge.c (same_succ_flush_bb): Handle + BB_SAME_SUCC (bb) == NULL. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * cfgrtl.c (rtl_verify_edges): Enable checking of profile_probability + consistency. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * dumpfile.c: Include profile-count.h + * tree-cfg.c (gimple_duplicate_sese_tail): Drop UNUSED attributes; + update profile. + (insert_cond_bb): Update profile. + * tree-cfg.h (insert_cond_bb): Update prototype. + * tree-chkp-opt.c (chkp_optimize_string_function_calls): Update. + * tree-dump.c: Do not include tree-cfg. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (fix_up_crossing_landing_pad): Update profile. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * expect.c (dw2_build_landing_pads): Update profile of the landing pad + bb. + +2017-07-02 Jan Hubicka <hubicka@ucw.cz> + + * tree-complex.c (expand_complex_div_wide): update profile. + +2017-07-02 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + + * Makefile.in (MACHMODE_H): Remove insn-modes.h + (CORETYPES_H): New define. + (MOSTLYCLEANFILES): Add insn-modes-inline.h. + (insn-modes-inline.h, s-modes-inline-h): New rules. + (generated_files): Add insn-modes-inline.h. + (RTL_BASE_H, TREE_CORE_H): Use CORETYPES_H instead of coretypes.h. + (build/gensupport.o, build/ggc-none.o, build/print-rtl.o): Likewise. + (build/read-md.o, build/read-rtl.o, build/rtl.o): Likewise. + (build/vec.o, build/hash-table.o, build/inchash.o): Likewise. + (build/gencondmd.o, build/genattr.o, build/genattr-common.o): Likewise. + (build/genattrtab.o, build/genautomata.o, build/gencheck.o): Likewise. + (build/gencodes.o, build/genconditions.o): Likewise. + (build/genconfig.o, build/genconstants.o, build/genemit.o): Likewise. + (build/genenums.o, build/genextract.o, build/genflags.o): Likewise. + (build/gentarget-def.o, build/genmddeps.o, build/genopinit.o) + (build/genoutput.o, build/genpeep.o, build/genpreds.o): Likewise. + (build/genrecog.o, build/genmddump.o, build/genmatch.o): Likewise. + (build/gencfn-macros.o, build/gcov-iov.o): Likewise. + * coretypes.h: Include everything up to real.h for generators. + Include insn-modes.h first. Include wide-int-print.h after + wide-int.h. Include insn-modes-inline.h and then machmode.h. + * machmode.h: Don't include insn-modes.h here. + * function-tests.c: Remove includes of signop.h, machmode.h, + double-int.h and wide-int.h. + * rtl.h: Likewise. + * gcc-rich-location.c: Remove includes of machmode.h, double-int.h + and wide-int.h. + * optc-save-gen.awk: Likewise. + * gencheck.c (BITS_PER_UNIT): Delete dummy definition. + * godump.c: Remove include of wide-int-print.h. + * pretty-print.h: Likewise. + * wide-int-print.cc: Likewise. + * wide-int.cc: Likewise. + * hash-map-tests.c: Remove include of signop.h. + * hash-set-tests.c: Likewise. + * rtl-tests.c: Likewise. + * mkconfig.sh: Remove include of machmode.h. + * genmodes.c (emit_insn_modes_h): Split emission of inline functions + into... + (emit_insn_modes_inline_h): ...this new function. Emit the code + into an insn-modes-inline.h header file, adding appropriate + include guards and end comments. + (emit_insn_modes_c_header): Remove include of machmode.h. + (emit_min_insn_modes_c_header): Include coretypes.h rather than + machmode.h. + (main): Handle -i flag and call emit_insn_modes_inline_h when + it is passed. + +2017-07-02 Richard Sandiford <richard.sandiford@linaro.org> + + * tree-ssa-strlen.c (strinfo): Rename the length field to + nonzero_chars. Add a full_string_p field. + (compare_nonzero_chars, zero_length_string_p): New functions. + (get_addr_stridx): Add an offset_out parameter. + Use compare_nonzero_chars. + (get_stridx): Update accordingly. Use compare_nonzero_chars. + (new_strinfo): Update after above changes to strinfo. + (set_endptr_and_length): Set full_string_p. + (get_string_length): Update after above changes to strinfo. + (unshare_strinfo): Update call to new_strinfo. + (maybe_invalidate): Likewise. + (get_stridx_plus_constant): Change off to unsigned HOST_WIDE_INT. + Use compare_nonzero_chars and zero_string_p. Treat nonzero_chars + as a uhwi instead of an shwi. Update after above changes to + strinfo and new_strinfo. + (zero_length_string): Assert that chainsi contains full strings. + Use zero_length_string_p. Update call to new_strinfo. + (adjust_related_strinfos): Update after above changes to strinfo. + Copy full_string_p from origsi. + (adjust_last_stmt): Use zero_length_string_p. + (handle_builtin_strlen): Update after above changes to strinfo and + new_strinfo. Install the lhs as the string length if the previous + entry didn't describe a full string. + (handle_builtin_strchr): Update after above changes to strinfo + and new_strinfo. + (handle_builtin_strcpy): Likewise. + (handle_builtin_strcat): Likewise. + (handle_builtin_malloc): Likewise. + (handle_pointer_plus): Likewise. + (handle_builtin_memcpy): Likewise. Track nonzero characters + that aren't necessarily followed by a nul terminator. + (handle_char_store): Likewise. + +2017-07-02 Richard Sandiford <richard.sandiford@linaro.org> + + PR tree-optimization/80769 + * tree-ssa-strlen.c (strinfo): Document that "stmt" is also used + for malloc and calloc. Document the new invariant that all related + strinfos have delayed lengths or none do. + (verify_related_strinfos): Move earlier in file. + (set_endptr_and_length): New function, split out from... + (get_string_length): ...here. Also set the lengths of related + strinfos. + (zero_length_string): Assert that chainsi has known (rather than + delayed) lengths. + (adjust_related_strinfos): Likewise. + +2017-07-02 Richard Sandiford <richard.sandiford@linaro.org> + + PR tree-optimization/81136 + * tree-vect-data-refs.c (vect_update_misalignment_for_peel): Only + assert that two references with the same misalignment have the same + compile-time misalignment if those compile-time misalignments + are known. + +2017-07-01 Andi Kleen <ak@linux.intel.com> + + * print-tree.c (print_node): Print all attributes. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * cfg.c (scale_bbs_frequencies): New function. + * cfg.h (scale_bbs_frequencies): Declare it. + * cfgloopanal.c (single_likely_exit): Cleanup. + * cfgloopmanip.c (scale_loop_frequencies): Take profile_probability + as parameter. + (scale_loop_profile): Likewise. + (loop_version): Likewise. + (create_empty_loop_on_edge): Update. + * cfgloopmanip.h (scale_loop_frequencies, scale_loop_profile, + scale_loop_frequencies, scale_loop_profile, loopify, + loop_version): Update prototypes. + * modulo-sched.c (sms_schedule): Update. + * predict.c (unlikely_executed_edge_p): Also check probability. + (probably_never_executed_edge_p): Fix typo. + * tree-if-conv.c (version_loop_for_if_conversion): Update. + * tree-parloops.c (gen_parallel_loop): Update. + * tree-ssa-loop-ivcanon.c (try_peel_loop): Update. + * tree-ssa-loop-manip.c (tree_transform_and_unroll_loop): Update. + * tree-ssa-loop-split.c (split_loop): Update. + * tree-ssa-loop-unswitch.c (tree_unswitch_loop): Update. + * tree-vect-loop-manip.c (vect_do_peeling): Update. + (vect_loop_versioning): Update. + * tree-vect-loop.c (scale_profile_for_vect_loop): Update. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * trans-mem.c (split_bb_make_tm_edge): Update profile. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * tree-if-conv.c (combine_blocks): Use make_single_succ_edge + to keep profile consistent. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * cfgrtl.c (rtl_flow_call_edges_add): Update profile. + * tree-cfg.c (gimple_flow_call_edges_add): Likewise. + * profile-count.h (max_safe_multiplier): Make unsigned. + (profile_count::guessed_zero): New. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * bb-reorder.c (fix_up_crossing_landing_pad, + fix_crossing_conditional_branches): Use make_single_succ_edge + to keep profile consistent. + +2017-07-01 Jan Hubicka <hubicka@ucw.cz> + + * tree-vect-loop.c (optimize_mask_stores): Use make_single_succ_edge + to update profile. + +2017-07-01 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/81262 + * bb-reorder.c (fix_up_fall_thru_edges): Move variable declarations to + the right scopes, make sure cond_jump isn't preserved between multiple + iterations. Search for fallthru edge whenever there are 3+ edges and + use find_fallthru_edge for it. + +2017-06-29 Jan Hubicka <hubicka@ucw.cz> + + Patch by Alexander Monakov <amonakov@ispras.ru> + * sel-sched-ir.c (compute_succs_info): Handle uninitialized + probabilities consistently. + +2017-06-29 Jan Hubicka <hubicka@ucw.cz> + + * pa.c (pa_expand_compare_and_swap_loop): Update call of + emit_cmp_and_jump_insns. + +2017-06-29 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/81261 + * tree-inline.c (expand_call_inline): Combine profile statuses. + +2017-06-30 Andrew Pinski <apinski@cavium.com> + + * tree-if-conv.c (predicate_scalar_phi): Update new_stmt if + fold_stmt returned true. + +2017-06-30 Nathan Sidwell <nathan@acm.org> + + * ggc.h (empty_string): Delete. + * cfgexpand.c (expand_asm_stmt): Use plain "". + * optabs.c (expand_asm_memory_barrier): Likewise. + * stringpool.c (empty_string): Delete. + (digit_vector, digit_string): Delete. + (ggc_alloc_string): Use plain "", don't optimize single digit + strings. Use ggc_alloc_atomic. + +2017-06-30 Richard Earnshaw <rearnsha@arm.com> + + * rtlanal.c (insn_rtx_cost): If a parallel contains exactly one + comparison set and one other set, use the cost of the non-comparison + set. + +2017-06-30 Nathan Sidwell <nathan@acm.org> + + * ggc.h: Replace all 'static inline' with plain 'inline'. Fix + some formatting. + +2017-06-30 Peter Bergner <bergner@vnet.ibm.com> + + * tree-cfg.c (group_case_labels_stmt): Merge scanning and compressing + loops. Remove now unneeded calls to gimple_switch_set_label() that + just set removed labels to NULL_TREE. + +2017-06-30 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssanames.c (set_range_info_raw): Abstract from ... + (set_range_info): ...here. Only call set_range_info_raw if domain + is useful. + (set_nonzero_bits): Call set_range_info_raw. + * tree-ssanames.h (set_range_info_raw): New. + +2017-06-30 Jakub Jelinek <jakub@redhat.com> + + PR target/81225 + * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For V8FI, + V16FI and VI8F_256 iterators, use <store_mask_predicate> instead + of nonimmediate_operand and <store_mask_constraint> instead of m + for the input operand. For V8FI iterator, always split if input + is a MEM. For V16FI and V8SF_256 iterators, don't test if both + operands are MEM if <mask_applied>. For VI4F_256 iterator, use + <store_mask_predicate> instead of register_operand and + <store_mask_constraint> instead of v for the input operand. Make + sure both operands aren't MEMs for if not <mask_applied>. + +2017-06-30 Sylvestre Ledru <sylvestre@debian.org> + + * lto-wrapper.c (copy_file) Close both file descriptors before + exiting normally. + +2017-06-30 Martin Liska <mliska@suse.cz> + + PR ipa/81214 + * multiple_target.c (create_dispatcher_calls): Make ifunc + also for function that don't have calls or are not referenced. + +2017-06-30 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.c (vect_slp_analyze_node_operations): Only + analyze the first scalar stmt. Move vector type computation + for the BB case here from ... + * tree-vect-stmts.c (vect_analyze_stmt): ... here. Guard + live operation processing in the SLP case properly. + +2017-06-30 Richard Biener <rguenther@suse.de> + + * graph.c (draw_cfg_node_succ_edges): Fix broken dot syntax. + +2017-06-30 Martin Liska <mliska@suse.cz> + + PR sanitizer/81021 + * tree-eh.c (lower_resx): Call BUILT_IN_ASAN_HANDLE_NO_RETURN + before BUILT_IN_UNWIND_RESUME when ASAN is used. + +2017-06-30 Yvan Roux <yvan.roux@linaro.org> + + * doc/invoke.texi (AArch64): Add missing options and remove redundant + ones. + +2017-06-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81249 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Convert + condition reduction result to original scalar type. + +2017-06-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * profile-count.h (enum profile_quality): Fix typos and whitespace + issues. + +2017-06-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * config/s390/s390.c (s390_expand_setmem): Adjust to the new data + type for branch probabilities. + +2017-06-29 Julian Brown <julian@codesourcery.com> + Naveen H.S <Naveen.Hurugalawadi@cavium.com> + + * config/aarch64/aarch64-fusion-pairs.def: Add ALU_BRANCH entry. + * config/aarch64/aarch64.c (AARCH64_FUSE_ALU_BRANCH): New fusion type. + (thunderx2t99_tunings): Set AARCH64_FUSE_ALU_BRANCH flag. + (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_ALU_BRANCH. + +2017-06-29 Naveen H.S <Naveen.Hurugalawadi@cavium.com> + + * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Push the + check for CC usage into AARCH64_FUSE_CMP_BRANCH. + * config/i386/i386.c (ix86_macro_fusion_pair_p): Push the check for + CC usage from generic code to here. + * sched-deps.c (sched_macro_fuse_insns): Move the condition for + CC usage into the target macros. + +2017-06-29 Maya Rashish <coypu@sdf.org> + + * config/netbsd.h (NETBSD_LIB_SPEC): Add -lc when creating shared + objects. + +2017-06-29 Jan Hubicka <hubicka@ucw.cz> + + * arm/arm-builtins.c: Include profile-count.h + * except.c (sjlj_emit_function_enter): Use + profile_probability::unlikely. + +2017-06-29 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (toc_relative_expr_p): Make tocrel_base + and tocrel_offset be pointer args rather than implicitly using + static versions. + (legitimate_constant_pool_address_p, rs6000_emit_move, + const_load_sequence_p, adjust_vperm): Add local tocrel_base and + tocrel_offset and use in toc_relative_expr_p call. + (print_operand, print_operand_address): Use static tocrel_base_oac + and tocrel_offset_oac. + (rs6000_output_addr_const_extra): Use static tocrel_base_oac and + tocrel_offset_oac. + +2017-06-29 Maya Rashish <coypu@sdf.org> + + * config/vax/builtins.md (ffssi2_internal): Correct constraint. + +2017-06-29 Eric Botcazou <ebotcazou@adacore.com> + + * expr.c (expand_expr) <normal_inner_ref>: When testing for unaligned + objects, take into account only the alignment of 'op0' and 'mode1' if + 'op0' is a MEM. + +2017-06-29 Steve Ellcey <sellcey@cavium.com> + + * ccmp.c (ccmp_tree_comparison_p): New function. + (ccmp_candidate_p): Update to use above function. + (get_compare_parts): New function. + (expand_ccmp_next): Update to use new functions. + (expand_ccmp_expr_1): Take tree arg instead of gimple, update to use + new functions. + (expand_ccmp_expr): Pass tree instead of gimple to expand_ccmp_expr_1, + take mode as argument. + * ccmp.h (expand_ccmp_expr): Add mode as argument. + * expr.c (expand_expr_real_1): Pass mode as argument. + +2017-06-29 Segher Boessenkool <segher@kernel.crashing.org> + + * combine.c (combine_instructions): Print insns to dump_file, together + with their costs. + +2017-06-29 Jan Hubicka <hubicka@ucw.cz> + + * asan.c (asan_emit_stack_protection): Update. + (create_cond_insert_point): Update. + * auto-profile.c (afdo_propagate_circuit): Update. + * basic-block.h (struct edge_def): Turn probability to + profile_probability. + (EDGE_FREQUENCY): Update. + * bb-reorder.c (find_traces_1_round): Update. + (better_edge_p): Update. + (sanitize_hot_paths): Update. + * cfg.c (unchecked_make_edge): Initialize probability to uninitialized. + (make_single_succ_edge): Update. + (check_bb_profile): Update. + (dump_edge_info): Update. + (update_bb_profile_for_threading): Update. + * cfganal.c (connect_infinite_loops_to_exit): Initialize new edge + probabilitycount to 0. + * cfgbuild.c (compute_outgoing_frequencies): Update. + * cfgcleanup.c (try_forward_edges): Update. + (outgoing_edges_match): Update. + (try_crossjump_to_edge): Update. + * cfgexpand.c (expand_gimple_cond): Update make_single_succ_edge. + (expand_gimple_tailcall): Update. + (construct_init_block): Use make_single_succ_edge. + (construct_exit_block): Use make_single_succ_edge. + * cfghooks.c (verify_flow_info): Update. + (redirect_edge_succ_nodup): Update. + (split_edge): Update. + (account_profile_record): Update. + * cfgloopanal.c (single_likely_exit): Update. + * cfgloopmanip.c (scale_loop_profile): Update. + (set_zero_probability): Remove. + (duplicate_loop_to_header_edge): Update. + * cfgloopmanip.h (loop_version): Update prototype. + * cfgrtl.c (try_redirect_by_replacing_jump): Update. + (force_nonfallthru_and_redirect): Update. + (update_br_prob_note): Update. + (rtl_verify_edges): Update. + (purge_dead_edges): Update. + (rtl_lv_add_condition_to_bb): Update. + * cgraph.c: (cgraph_edge::redirect_call_stmt_to_calle): Update. + * cgraphunit.c (init_lowered_empty_function): Update. + (cgraph_node::expand_thunk): Update. + * cilk-common.c: Include profile-count.h + * dojump.c (inv): Remove. + (jumpifnot): Update. + (jumpifnot_1): Update. + (do_jump_1): Update. + (do_jump): Update. + (do_jump_by_parts_greater_rtx): Update. + (do_compare_rtx_and_jump): Update. + * dojump.h (jumpifnot, jumpifnot_1, jumpif_1, jumpif, do_jump, + do_jump_1. do_compare_rtx_and_jump): Update prototype. + * dwarf2cfi.c: Include profile-count.h + * except.c (dw2_build_landing_pads): Use make_single_succ_edge. + (sjlj_emit_dispatch_table): Likewise. + * explow.c: Include profile-count.h + * expmed.c (emit_store_flag_force): Update. + (do_cmp_and_jump): Update. + * expr.c (compare_by_pieces_d::generate): Update. + (compare_by_pieces_d::finish_mode): Update. + (emit_block_move_via_loop): Update. + (store_expr_with_bounds): Update. + (store_constructor): Update. + (expand_expr_real_2): Update. + (expand_expr_real_1): Update. + * expr.h (try_casesi, try_tablejump): Update prototypes. + * gimple-pretty-print.c (dump_probability): Update. + (dump_profile): New. + (dump_gimple_label): Update. + (dump_gimple_bb_header): Update. + * graph.c (draw_cfg_node_succ_edges): Update. + * hsa-gen.c (convert_switch_statements): Update. + * ifcvt.c (cheap_bb_rtx_cost_p): Update. + (find_if_case_1): Update. + (find_if_case_2): Update. + * internal-fn.c (expand_arith_overflow_result_store): Update. + (expand_addsub_overflow): Update. + (expand_neg_overflow): Update. + (expand_mul_overflow): Update. + (expand_vector_ubsan_overflow): Update. + * ipa-cp.c (good_cloning_opportunity_p): Update. + * ipa-split.c (split_function): Use make_single_succ_edge. + * ipa-utils.c (ipa_merge_profiles): Update. + * loop-doloop.c (add_test): Update. + (doloop_modify): Update. + * loop-unroll.c (compare_and_jump_seq): Update. + (unroll_loop_runtime_iterations): Update. + * lra-constraints.c (lra_inheritance): Update. + * lto-streamer-in.c (input_cfg): Update. + * lto-streamer-out.c (output_cfg): Update. + * mcf.c (adjust_cfg_counts): Update. + * modulo-sched.c (sms_schedule): Update. + * omp-expand.c (expand_omp_for_init_counts): Update. + (extract_omp_for_update_vars): Update. + (expand_omp_ordered_sink): Update. + (expand_omp_for_ordered_loops): Update. + (expand_omp_for_generic): Update. + (expand_omp_for_static_nochunk): Update. + (expand_omp_for_static_chunk): Update. + (expand_cilk_for): Update. + (expand_omp_simd): Update. + (expand_omp_taskloop_for_outer): Update. + (expand_omp_taskloop_for_inner): Update. + * omp-simd-clone.c (simd_clone_adjust): Update. + * optabs.c (expand_doubleword_shift): Update. + (expand_abs): Update. + (emit_cmp_and_jump_insn_1): Update. + (expand_compare_and_swap_loop): Update. + * optabs.h (emit_cmp_and_jump_insns): Update prototype. + * predict.c (predictable_edge_p): Update. + (edge_probability_reliable_p): Update. + (set_even_probabilities): Update. + (combine_predictions_for_insn): Update. + (combine_predictions_for_bb): Update. + (propagate_freq): Update. + (estimate_bb_frequencies): Update. + (force_edge_cold): Update. + * profile-count.c (profile_count::dump): Add missing space into dump. + (profile_count::debug): Add newline. + (profile_count::differs_from_p): Explicitly convert to unsigned. + (profile_count::stream_in): Update. + (profile_probability::dump): New member function. + (profile_probability::debug): New member function. + (profile_probability::differs_from_p): New member function. + (profile_probability::differs_lot_from_p): New member function. + (profile_probability::stream_in): New member function. + (profile_probability::stream_out): New member function. + * profile-count.h (profile_count_quality): Rename to ... + (profile_quality): ... this one. + (profile_probability): New. + (profile_count): Update. + * profile.c (compute_branch_probabilities): Update. + * recog.c (peep2_attempt): Update. + * sched-ebb.c (schedule_ebbs): Update. + * sched-rgn.c (find_single_block_region): Update. + (compute_dom_prob_ps): Update. + (schedule_region): Update. + * sel-sched-ir.c (compute_succs_info): Update. + * stmt.c (struct case_node): Update. + (do_jump_if_equal): Update. + (get_outgoing_edge_probs): Update. + (conditional_probability): Update. + (emit_case_dispatch_table): Update. + (expand_case): Update. + (expand_sjlj_dispatch_table): Update. + (emit_case_nodes): Update. + * targhooks.c: Update. + * tracer.c (better_p): Update. + (find_best_successor): Update. + * trans-mem.c (expand_transaction): Update. + * tree-call-cdce.c: Update. + * tree-cfg.c (gimple_split_edge): Upate. + (move_sese_region_to_fn): Upate. + * tree-cfgcleanup.c (cleanup_control_expr_graph): Upate. + * tree-eh.c (lower_resx): Upate. + (cleanup_empty_eh_move_lp): Upate. + * tree-if-conv.c (version_loop_for_if_conversion): Update. + * tree-inline.c (copy_edges_for_bb): Update. + (copy_cfg_body): Update. + * tree-parloops.c (gen_parallel_loop): Update. + * tree-profile.c (gimple_gen_ic_func_profiler): Update. + (gimple_gen_time_profiler): Update. + * tree-ssa-dce.c (remove_dead_stmt): Update. + * tree-ssa-ifcombine.c (update_profile_after_ifcombine): Update. + * tree-ssa-loop-im.c (execute_sm_if_changed): Update. + * tree-ssa-loop-ivcanon.c (remove_exits_and_undefined_stmts): Update. + (unloop_loops): Update. + (try_peel_loop): Update. + * tree-ssa-loop-manip.c (tree_transform_and_unroll_loop): Update. + * tree-ssa-loop-split.c (connect_loops): Update. + (split_loop): Update. + * tree-ssa-loop-unswitch.c (tree_unswitch_loop): Update. + (hoist_guard): Update. + * tree-ssa-phionlycprop.c (propagate_rhs_into_lhs): Update. + * tree-ssa-phiopt.c (replace_phi_edge_with_variable): Update. + (value_replacement): Update. + * tree-ssa-reassoc.c (branch_fixup): Update. + * tree-ssa-tail-merge.c (replace_block_by): Update. + * tree-ssa-threadupdate.c (remove_ctrl_stmt_and_useless_edges): Update. + (create_edge_and_update_destination_phis): Update. + (compute_path_counts): Update. + (recompute_probabilities): Update. + (update_joiner_offpath_counts): Update. + (freqs_to_counts_path): Update. + (duplicate_thread_path): Update. + * tree-switch-conversion.c (hoist_edge_and_branch_if_true): Update. + (struct switch_conv_info): Update. + (gen_inbound_check): Update. + * tree-vect-loop-manip.c (slpeel_add_loop_guard): Update. + (vect_do_peeling): Update. + (vect_loop_versioning): Update. + * tree-vect-loop.c (scale_profile_for_vect_loop): Update. + (optimize_mask_stores): Update. + * ubsan.c (ubsan_expand_null_ifn): Update. + * value-prof.c (gimple_divmod_fixed_value): Update. + (gimple_divmod_fixed_value_transform): Update. + (gimple_mod_pow2): Update. + (gimple_mod_pow2_value_transform): Update. + (gimple_mod_subtract): Update. + (gimple_mod_subtract_transform): Update. + (gimple_ic): Update. + (gimple_stringop_fixed_value): Update. + (gimple_stringops_transform): Update. + * value-prof.h: Update. + +2017-06-29 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for built-in functions + vector signed int vec_signed (vector float); + vector signed long long vec_signed (vector double); + vector signed int vec_signed2 (vector double, vector double); + vector signed int vec_signede (vector double); + vector signed int vec_signedo (vector double); + * config/rs6000/rs6000.c (rs6000_generate_vsigned2_code): Add + instruction generator. + * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPSXWS, UNSPEC_VSX_XVCVSPSXDS, + UNSPEC_VSX_VSIGNED2): Add UNSPECS. + (vsx_xvcvspsxws, vsx_xvcvdpuxds_scale, vsx_xvcvspuxws, vsigned2_v2df): + Add define_insn. + (vsignedo_v2df, vsignede_v2df, vunsigned2_v2df, vunsignedo_v2df, + vunsignede_v2df): Add define_expands. + * config/rs6000/rs6000-builtin.def (VEC_SIGNED, VEC_UNSIGNED, + VEC_SIGNED2, VEC_UNSIGNED2, VEC_SIGNEDE, VEC_UNSIGNEDE, VEC_SIGNEDO, + VEC_UNSIGNEDO): Add definitions. + * config/vsx.md (UNSPEC_VSX_XVCVSPSXWS, UNSPEC_VSX_XVCVSPSXDS, + UNSPEC_VSX_VSIGNED2): Add UNSPECs. + (vsx_xvcvspsxws, vsx_xvcvspuxws): Add define_insn. + (vsigned2_v2df, vsigendo_v2df, vsignede_v2df, + vunsigned2_v2df, vunsignedo_v2df, vunsignede_v2df): Add define_expands. + * config/rs6000/altivec.h (vec_signed, vec_signed2, + vec_signede and vec_signedo, vec_unsigned, vec_unsigned2, + vec_unsignede, vec_unsignedo): Add builtin defines. + * config/rs6000-protos.h (rs6000_generate_vsigned2_code): Add extern + declaration. + * doc/extend.texi: Update the built-in documentation file for the + new built-in functions. + +2017-06-29 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.c (vect_analyze_scalar_cycles_1): Do not add + reduction chains to LOOP_VINFO_REDUCTIONS. + * tree-vect-slp.c (vect_analyze_slp): Continue looking for + SLP reductions after processing reduction chains. + +2017-06-29 Nathan Sidwell <nathan@acm.org> + + * builtins.c (fold_builtin_FUNCTION): Use + lang_hooks.decl_printable_name. + +2017-06-29 Peter Bergner <bergner@vnet.ibm.com> + + PR middle-end/81194 + * cfgexpand.c (expand_gimple_stmt_1): Handle switch statements + with only one label. + * stmt.c (expand_case): Assert NCASES is greater than one. + +2017-06-29 Richard Biener <rguenther@suse.de> + + * tree-cfg.c (group_case_labels_stmt): Return whether we changed + anything. + (group_case_labels): Likewise. + (find_taken_edge): Push sanity checking on val to workers... + (find_taken_edge_cond_expr): ... here + (find_taken_edge_switch_expr): ... and here, handle cases + with just a default label. + * tree-cfg.h (group_case_labels_stmt): Adjust prototype. + (group_case_labels): Likewise. + * tree-cfgcleanup.c (execute_cleanup_cfg_post_optimizing): When + group_case_labels does anything cleanup the CFG again. + +2017-06-29 Bin Cheng <bin.cheng@arm.com> + + PR tree-optimization/81196 + * tree-ssa-loop-niter.c (number_of_iterations_cond): Handle loop + exit condition comparing two IVs. + +2017-06-29 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/parsecpu.awk (gen_comm_data): Add initializer for + profile to the dummy entry at the end of the list of architectures. + * config/arm/arm-cpu-cdata.h: Regenerated. + +2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + Michael Collison <michael.collison@arm.com> + + PR target/70119 + * config/aarch64/aarch64.md (*aarch64_<optab>_reg_<mode>3_mask1): + New pattern. + (*aarch64_reg_<mode>3_neg_mask2): New pattern. + (*aarch64_reg_<mode>3_minus_mask): New pattern. + (*aarch64_<optab>_reg_di3_mask2): New pattern. + * config/aarch64/aarch64.c (aarch64_rtx_costs): Account for cost + of shift when the shift amount is masked with constant equal to + the size of the mode. + * config/aarch64/predicates.md (subreg_lowpart_operator): New + predicate. + +2017-06-29 Martin Liska <mliska@suse.cz> + + * config/i386/i386.opt: Change range from [1,5] to [0,5]. + +2017-06-29 Yury Gribov <tetra2005@gmail.com> + + PR bootstrap/80565 + * ipa-cp.c (allocate_and_init_ipcp_value): Add initialization + code. + * ipa-inline.h + (edge_growth_cache_entry::edge_growth_cache_entry): New + function. + (reset_edge_growth_cache): Update to use constructor. + +2017-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * config/aarch64/aarch64.h (AARCH64_EXPAND_ALIGNMENT): New. + (DATA_ALIGNMENT): Update to use AARCH64_EXPAND_ALIGNMENT. + (LOCAL_ALIGNMENT): Update to use AARCH64_EXPAND_ALIGNMENT. + +2017-06-28 Sebastian Peryt <sebastian.peryt@intel.com> + + * config/i386/avx512vlintrin.h (_mm256_permutexvar_epi64) + (_mm256_permutexvar_epi32, _mm256_permutex_epi64): New intrinsics. + +2017-06-28 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * config.gcc (*-linux-musl*): Add t-musl tmake_file. + (*-linux-uclibc*): Add t-uclibc tmake_file. + * config/t-musl: New. + * config/t-uclibc: New. + +2017-06-28 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/parsecpu.awk (profile): Parse new keyword in an arch + context. + (gen_comm_data): Emit architectural setting of arch_prof. + * config/arm/arm-cpus.in (armv6-m, armv6s-m, armv7-a, armv7ve): Set the + profile. + (armv7-r, armv7-m, armv7e-m, armv8-a, armv8.1-a, armv8.2-a): Likewise. + (armv8-m.base, armv8-m.main): Likewise. + * arm-protos.h (arm_build_target): Add profile field. + (arch_option): Likewise. + * config/arm/arm.c (arm_configure_build_target): Copy the profile to + the active target. + * config/arm/arm.h (TARGET_ARM_ARCH_PROFILE): Use + arm_active_target.profile. + +2017-06-28 Richard Biener <rguenther@suse.de> + + PR middle-end/81227 + * fold-const.c (negate_expr_p): Use TYPE_UNSIGNED, not + TYPE_OVERFLOW_WRAPS. + * match.pd (negate_expr_p): Likewise. + * tree-ssa-reassoc.c (optimize_range_tests_diff): Use + fold_build2, not fold_binary. + +2017-06-28 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64 (aarch64_expand_mov_immediate): + Convert memory address to Pmode. + (aarch64_print_operand): Assert MEM operands are always Pmode. + +2017-06-28 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/79665 + * config/arm/aarch-common.c (arm_no_early_alu_shift_dep): + Remove redundant if. + (aarch_forward_to_shift_is_not_shifted_reg): Remove. + * config/arm/aarch-common-protos.h + (aarch_forward_to_shift_is_not_shifted_re): Remove. + * config/arm/cortex-a53.md: Use arm_no_early_alu_shift_dep in bypass. + +2017-06-28 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR ipa/81238 + * multiple_target.c (create_dispatcher_calls): Set the default + clone to be static, not public. + +2017-06-28 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.c (vectorizable_reduction): Move special + cond reduction IV var creation ... + (vect_create_epilog_for_reduction): ... here. Remove induction_index + parameter. Use STMT_VINFO_VECTYPE. + * tree-vect-slp.c (vect_get_constant_vectors): Properly reset + constant_p. + +2017-06-28 Martin Liska <mliska@suse.cz> + + PR ipa/81128 + * ipa-visibility.c (non_local_p): Handle visibility. + +2017-06-28 Martin Liska <mliska@suse.cz> + + PR driver/79659 + * common.opt: Add IntegerRange to various options. + * opt-functions.awk (integer_range_info): New function. + * optc-gen.awk: Add integer_range_info to cl_options struct. + * opts-common.c (decode_cmdline_option): Handle + CL_ERR_INT_RANGE_ARG. + (cmdline_handle_error): Likewise. + * opts.c (print_filtered_help): Show valid interval in + when --help is provided. + * opts.h (struct cl_option): Add range_min and range_max fields. + * config/i386/i386.opt: Add IntegerRange for -mbranch-cost. + +2017-06-28 Marc Glisse <marc.glisse@inria.fr> + + * match.pd ((X & ~Y) | (~X & Y)): Generalize to + and ^. + (x * C EQ/NE y * C): New transformation. + +2017-06-28 Christophe Lyon <christophe.lyon@linaro.org> + + * genmultilib (combination_space): Accept '+' in option names. + +2017-06-28 Martin Liska <mliska@suse.cz> + + PR sanitizer/81224 + * asan.c (instrument_derefs): Bail out inner references + that are hard register variables. + +2017-06-28 Jakub Jelinek <jakub@redhat.com> + + PR target/81175 + * config/i386/i386.c (ix86_init_mmx_sse_builtins): Use def_builtin + rather than def_builtin_pure for __builtin_ia32_gatherpf*. + +2017-06-28 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_get_vec_defs): Remove. + (vect_get_slp_defs): Adjust. + * tree-vect-loop.c (get_initial_defs_for_reduction): Split + out from ... + * tree-vect-slp.c (vect_get_constant_vectors): ... here and + simplify. + * tree-vect-loop.c (vect_create_epilog_for_reduction): Use + get_initial_defs_for_reduction instead of vect_get_vec_defs. + (vectorizable_reduction): Adjust. + * tree-vect-slp.c (vect_get_constant_vectors): Remove reduction + handling. + (vect_get_slp_defs): Likewise. + * tree-vect-stmts.c (vect_get_vec_defs): Make static and adjust. + (vectorizable_bswap): Adjust. + (vectorizable_call): Likewise. + (vectorizable_conversion): Likewise. + (vectorizable_assignment): Likewise. + (vectorizable_shift): Likewise. + (vectorizable_operation): Likewise. + (vectorizable_store): Likewise. + (vectorizable_condition): Likewise. + (vectorizable_comparison): Likewise. + +2017-06-28 Michael Collison <michael.collison@arm.com> + + PR target/68535 + * config/arm/arm.c (gen_ldm_seq): Remove last unnecessary + set of base_reg + (arm_gen_movmemqi): Removed unused variable 'i'. + Convert 'for' loop into 'while' loop. + (arm_expand_prologue): Remove last unnecessary set of insn. + (thumb_pop): Remove unused variable 'pushed_words'. + (thumb_exit): Remove last unnecessary set of regs_to_pop. + +2017-06-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * config/s390/predicates.md: Use s390_rel_address_ok_p. + * config/s390/s390-protos.h: Add prototype of + s390_rel_address_ok_p. + * config/s390/s390.c (s390_got_symbol): New function. + (s390_rel_address_ok_p): New function. + (legitimize_pic_address): Use s390_rel_address_ok_p. + (s390_load_got): Use s390_got_symbol. + (s390_option_override): Issue error if + -mno-pic-data-is-text-relative is used without -fpic/-fPIC. + * config/s390/s390.h (TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE): + New macro. + * config/s390/s390.opt: New option mpic-data-is-text-relative. + +2017-06-27 Andrew Pinski <apinski@cavium.com> + + * match.pd (X >/>=/</<= 0 ? 1.0 : -1.0): New patterns. + (X * copysign (1.0, X)): New pattern. + (X * copysign (1.0, -X)): New pattern. + (copysign (-1.0, CST)): New pattern. + +2017-06-27 Joseph Myers <joseph@codesourcery.com> + + * genmultilib (combination_space): Remove variable. + Validate reuse rules against regular expression for any sequence + of multilib options in any order. + +2017-06-27 Michael Collison <michael.collison@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly + call aarch64_split_simd_combine. + * (aarch64_combine_internal<mode>): Delete pattern. + * config/aarch64/aarch64.c (aarch64_split_simd_combine): + Allow register and subreg operands. + +2017-06-27 Jerome Lambourg <lambourg@adacore.com> + + * config/i386/vxworks.h (ASM_SPEC): Remove definition. No target + specific need, just fallback on defaults. + (ASM_OUTPUT_ALIGNED_BSS): Add #undef before #define. + +2017-06-27 Jerome Lambourg <lambourg@adacore.com> + Olivier Hainque <hainque@adacore.com> + + * config/i386/vxworks.h (DBX_REGISTER_NUMBER): Pick distinct + map for 64bits. + (TARGET_OS_CPP_BUILTINS): builtin_define CPU to X86_64 for 64bit + targets. Pick a default if no particular attempt applied. + (STACK_CHECK_PROTECT): Double for 64bit targets, which have + larger contexts. + +2017-06-27 Jerome Lambourg <lambourg@adacore.com> + + * config.gcc (i*86-wrs-vxworks7): Handle new acceptable triplet. + (x86_64-wrs-vxworks7): Likewise. + +2017-06-27 Marek Polacek <polacek@redhat.com> + + PR sanitizer/81223 + * ubsan.c (instrument_null): Check get_base_address's result for null. + +2017-06-27 Marc Glisse <marc.glisse@inria.fr> + + * match.pd ((A+-B)+(C-A), (A+B)-(A-C)): New transformations. + +2017-06-27 Marc Glisse <marc.glisse@inria.fr> + + * builtin-types.def (BT_FENV_T_PTR, BT_CONST_FENV_T_PTR, + BT_FEXCEPT_T_PTR, BT_CONST_FEXCEPT_T_PTR): New primitive types. + (BT_FN_INT_FENV_T_PTR, BT_FN_INT_CONST_FENV_T_PTR, + BT_FN_INT_FEXCEPT_T_PTR_INT, BT_FN_INT_CONST_FEXCEPT_T_PTR_INT): + New function types. + * builtins.def (BUILT_IN_FECLEAREXCEPT, BUILT_IN_FEGETENV, + BUILT_IN_FEGETEXCEPTFLAG, BUILT_IN_FEGETROUND, + BUILT_IN_FEHOLDEXCEPT, BUILT_IN_FERAISEEXCEPT, + BUILT_IN_FESETENV, BUILT_IN_FESETEXCEPTFLAG, + BUILT_IN_FESETROUND, BUILT_IN_FETESTEXCEPT, + BUILT_IN_FEUPDATEENV): New builtins. + * tree-core.h (TI_FENV_T_PTR_TYPE, TI_CONST_FENV_T_PTR_TYPE, + TI_FEXCEPT_T_PTR_TYPE, TI_CONST_FEXCEPT_T_PTR_TYPE): New entries. + * tree.h (fenv_t_ptr_type_node, const_fenv_t_ptr_type_node, + fexcept_t_ptr_type_node, const_fexcept_t_ptr_type_node): New + macros. + (builtin_structptr_types): Adjust size. + * tree.c (builtin_structptr_types): Add four entries. + +2017-06-27 Jerome Lambourg <lambourg@adacore.com> + Olivier Hainque <hainque@adacore.com> + + * config/vxworks.h (VXWORKS_LIB_SPEC): Incorporate ... + (TLS_SYM): New local macro, forcing reference to __tls__ on + link command lines for VxWorks 7 RTPs, triggering initialization + of tlsLib. + (VXWORKS_HAVE_TLS): New macro. State whether the target VxWorks + OS features TLS support, true for RTPs on VxWorks 7. + * config/vxworks.c (vxworks_override_options): Setup emutls + accordingly. + +2017-06-27 Jakub Jelinek <jakub@redhat.com> + + * predict.c (test_prediction_value_range): Use -1U instead of -1 + to avoid narrowing conversion warning. + * dumpfile.c (dump_options): Wrap all value into dump_flags_t cast + to avoid narrowing conversion warning. + * opt-functions.awk (var_ref): Return (unsigned short) -1 instead of + -1. + * optc-gen.awk (END): Expect (unsigned short) -1 instead of -1. + +2017-06-27 Jerome Lambourg <lambourg@adacore.com> + + * config/vxworks.h (VXWORKS_LIBS_RTP): Alternative definition for + 64bit configurations. + (PTR_DIFF_TYPE): Alternative definition for TARGET_LP64. + (SIZE_TYPE): Likewise. + * config/vxworks.c (vxworks_emutls_var_fields): Use + long_unsigned_type_node instead of unsigned_type_node as the offset + field type, which is "pointer" mode in emutls.c. + +2017-06-27 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/81209 + * ubsan.c (ubsan_encode_value): Initialize DECL_CONTEXT on var. + + PR middle-end/81207 + * gimple-fold.c (replace_call_with_call_and_fold): Handle + gimple_vuse copying separately from gimple_vdef copying. + +2017-06-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * value-prof.c (free_hist): Remove call to memset and the enclosing if + condition. + +2017-06-26 Jerome Lambourg <lambourg@adacore.com> + Olivier Hainque <hainque@adacore.com> + + * config.gcc (*-*-vxworks*): Add TARGET_VXWORKS7=1 to tm_defines + for all vxworks7 targets. + * config/vxworks.h (TARGET_VXWORKS7): If not defined, define to 0. + (VXWORKS_ADDITIONAL_CPP_SPEC): Alternative definition for VXWORKS7. + (VXWORKS_LIBS_RTP, VXWORKS_LIBS_RTP_DIR): New macros, allowing + variations for VX6/VX7 and 32/64bits later on in ... + (VXWORKS_LIB_SPEC): Leverage new macros. + (VXWORKS_OS_CPP_BUILTINS): Define _VSB_CONFIG_FILE for VXWORKS7, + as well as _ALLOW_KEYWORD_MACROS when "inline" is not a keyword. + +2017-06-26 Jerome Lambourg <lambourg@adacore.com> + + * config/vxworks.h (VXWORKS_OS_CPP_BUILTINS): builtin_define + _VX_TOOL_FAMILY and _VX_TOOL to gnu. + +2017-06-26 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000-c.c: Add support for built-in functions + vector bool char vec_reve (vector bool char); + vector signed char vec_reve (vector signed char); + vector unsigned char vec_reve (vector unsigned char); + vector bool int vec_reve (vector bool int); + vector signed int vec_reve (vector signed int); + vector unsigned int vec_reve (vector unsigned int); + vector bool long long vec_reve (vector bool long long); + vector signed long long vec_reve (vector signed long long); + vector unsigned long long vec_reve (vector unsigned long long); + vector bool short vec_reve (vector bool short); + vector signed short vec_reve (vector signed short); + vector double vec_reve (vector double); + vector float vec_reve (vector float); + * config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI, + VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New builtin. + * config/rs6000/altivec.md (UNSPEC_VREVEV): New UNSPEC. + (altivec_vreve): New pattern. + * config/rs6000/altivec.h (vec_reve): New define. + * doc/extend.texi (vec_rev): Update the built-in documentation file + for the new built-in functions. + +2016-06-26 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR tree-optimization/71815 + * gimple-ssa-strength-reduction.c (uses_consumed_by_stmt): New + function. + (find_basis_for_candidate): Call uses_consumed_by_stmt rather than + has_single_use. + (slsr_process_phi): Likewise. + (replace_uncond_cands_and_profitable_phis): Don't replace a + multiply candidate with a stride of 1 (copy or cast). + (phi_incr_cost): Call uses_consumed_by_stmt rather than + has_single_use. + (lowest_cost_path): Likewise. + (total_savings): Likewise. + +2017-06-26 Richard Biener <rguenther@suse.de> + + PR target/81175 + * config/i386/i386.c (ix86_init_mmx_sse_builtins): + Use def_builtin_pure for all gather builtins. + +2017-06-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/81203 + * tree-tailcall.c (find_tail_calls): Do not move stmts into + non-dominating BBs. + +2017-06-26 Marek Polacek <polacek@redhat.com> + + PR c/80116 + * doc/invoke.texi: Document -Wmultistatement-macros. + +2017-06-26 Christophe Lyon <christophe.lyon@linaro.org> + + * doc/sourcebuild.texi (ARM-specific attributes): Document new + arm_neon_ok_no_float_abi effective target. + 2017-06-26 Richard Biener <rguenther@suse.de> PR tree-optimization/80928 @@ -285,7 +4898,7 @@ attribute type list for neon_multiply. * config/arm/types.md (crypto_pmull): Add. * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to - attribute type list. + attribute type list. 2017-06-20 Andreas Tobler <andreast@gcc.gnu.org> @@ -541,9 +5154,9 @@ 2017-06-16 Richard Earnshaw <rearnsha@arm.com> * config/arm/t-linux-eabi (MULTILIB_EXCEPTIONS): Set to empty. - (MULTILIB_RESUE): Likewise. - (MULTILIB_MATCHES): Likewise. - (MULTLIB_REQUIRED): Likewise. + (MULTILIB_RESUE): Likewise. + (MULTILIB_MATCHES): Likewise. + (MULTLIB_REQUIRED): Likewise. 2017-06-16 Richard Earnshaw <rearnsha@arm.com> @@ -916,28 +5529,28 @@ 2017-06-16 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org> - * config/aarch64/aarch64.c (qdf24xx_prefetch_tune): Update - prefetch settings, and enable prefetching by default at -O3. + * config/aarch64/aarch64.c (qdf24xx_prefetch_tune): Update + prefetch settings, and enable prefetching by default at -O3. 2017-06-16 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org> - * config/aarch64/aarch64.c (aarch64_override_options_internal): - Set flag_prefetch_loop_arrays according to tuning data. + * config/aarch64/aarch64.c (aarch64_override_options_internal): + Set flag_prefetch_loop_arrays according to tuning data. 2017-06-16 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org> - * config/aarch64/aarch64-protos.h (struct cpu_prefetch_tune): - New tune structure. - (struct tune_params): Use cpu_prefetch_tune instead of cache_line_size. - [Unrelated to main purpose of the patch] Place the pointer field last - to enable type checking errors when tune structure are wrongly merged. - * config/aarch64/aarch64.c (generic_prefetch_tune,) - (exynosm1_prefetch_tune, qdf24xx_prefetch_tune,) - (thunderx2t99_prefetch_tune): New tune constants. - (tune_params *_tunings): Update all tunings (no functional change). - (aarch64_override_options_internal): Set PARAM_SIMULTANEOUS_PREFETCHES, - PARAM_L1_CACHE_SIZE, PARAM_L1_CACHE_LINE_SIZE, and PARAM_L2_CACHE_SIZE - from tunings structures. + * config/aarch64/aarch64-protos.h (struct cpu_prefetch_tune): + New tune structure. + (struct tune_params): Use cpu_prefetch_tune instead of cache_line_size. + [Unrelated to main purpose of the patch] Place the pointer field last + to enable type checking errors when tune structure are wrongly merged. + * config/aarch64/aarch64.c (generic_prefetch_tune,) + (exynosm1_prefetch_tune, qdf24xx_prefetch_tune,) + (thunderx2t99_prefetch_tune): New tune constants. + (tune_params *_tunings): Update all tunings (no functional change). + (aarch64_override_options_internal): Set PARAM_SIMULTANEOUS_PREFETCHES, + PARAM_L1_CACHE_SIZE, PARAM_L1_CACHE_LINE_SIZE, and PARAM_L2_CACHE_SIZE + from tunings structures. 2017-06-16 Jakub Jelinek <jakub@redhat.com> @@ -1069,7 +5682,7 @@ PR target/71663 * config/aarch64/aarch64.c (aarch64_expand_vector_init): - Improve vector initialization code gen for only variable case. + Improve vector initialization code gen for only variable case. 2017-06-14 Eric Botcazou <ebotcazou@adacore.com> @@ -1913,7 +6526,7 @@ PR sanitizer/80932 * fold-const.c (extract_muldiv_1) <case MINUS_EXPR>: Add - TYPE_OVERFLOW_WRAPS check. + TYPE_OVERFLOW_WRAPS check. 2017-06-07 Bin Cheng <bin.cheng@arm.com> @@ -1956,12 +6569,13 @@ 2017-06-07 Tamar Christina <tamar.christina@arm.com> - * config/aarch64/aarch64.c (aarch64_rtx_costs): Make sdiv more expensive than udiv. - Remove floating point cases from mod. + * config/aarch64/aarch64.c (aarch64_rtx_costs): Make sdiv more + expensive than udiv. Remove floating point cases from mod. 2017-06-07 Tamar Christina <tamar.christina@arm.com> - * config/arm/aarch-cost-tables.h (cortexa53_extra_cost): Increase idiv cost. + * config/arm/aarch-cost-tables.h (cortexa53_extra_cost): + Increase idiv cost. 2017-06-07 Tamar Christina <tamar.christina@arm.com> @@ -5671,7 +10285,7 @@ 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com> - * gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename + * config/arm/arm-builtins.c (arm_init_builtins): Rename __builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename __builtin_arm_stfscr to __builtin_arm_set_fpscr. @@ -11632,7 +16246,7 @@ 2017-02-06 Palmer Dabbelt <palmer@dabbelt.com> * config/riscv/riscv.c: New file. - * gcc/common/config/riscv/riscv-common.c: Likewise. + * common/config/riscv/riscv-common.c: Likewise. * config.gcc: Likewise. * config/riscv/constraints.md: Likewise. * config/riscv/elf.h: Likewise. @@ -12895,7 +17509,7 @@ * config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. - * gcc/config/i386/i386.c: Handle new builtins. + * config/i386/i386.c: Handle new builtins. * config/i386/i386-builtin.def: Add new builtins. * config/i386/sse.md (ktest<mode>, kortest<mode>): New. (UNSPEC_KORTEST, UNSPEC_KTEST): New. @@ -13076,7 +17690,7 @@ * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/i386-builtin-types.def: Add new types. - * gcc/config/i386/i386.c: Handle new types. + * config/i386/i386.c: Handle new types. * config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi) (__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi) (__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi) @@ -13099,14 +17713,14 @@ (with_madd4): Add validation. (all_defaults): Add madd4. * config/mips/mips.opt (mmadd4): New option. - * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for + * config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mmadd4. (TARGET_CPU_CPP_BUILTINS): Add builtin_define for __mips_no_madd4. (ISA_HAS_UNFUSED_MADD4): Gate with mips_madd4. (ISA_HAS_FUSED_MADD4): Likewise. - * gcc/doc/invoke.texi (-mmadd4): Document the new option. - * gcc/doc/install.texi (--with-madd4): Document the new option. + * doc/invoke.texi (-mmadd4): Document the new option. + * doc/install.texi (--with-madd4): Document the new option. 2017-01-19 Jiong Wang <jiong.wang@arm.com> @@ -13244,12 +17858,12 @@ (with_lxc1_sxc1): Add validation. (all_defaults): Add lxc1-sxc1. * config/mips/mips.opt (mlxc1-sxc1): New option. - * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for + * config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mlxc1-sxc1. (TARGET_CPU_CPP_BUILTINS): Add builtin_define for __mips_no_lxc1_sxc1. (ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1. - * gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option. + * doc/invoke.texi (-mlxc1-sxc1): Document the new option. * doc/install.texi (--with-lxc1-sxc1): Document the new option. 2017-01-19 Richard Biener <rguenther@suse.de> @@ -14666,8 +19280,8 @@ 'arm_const_bounds'. * config/arm/types.md (coproc): New. * config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New. - * gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics. - * gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok, + * doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics. + * doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok, arm_coproc3_ok, arm_coproc4_ok): Document new effective targets. 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> |