diff options
| author | eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-12-05 17:27:05 +0000 |
|---|---|---|
| committer | eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-12-05 17:27:05 +0000 |
| commit | 41f7ed9c919b6db73b6751f2d8388cd4820105e3 (patch) | |
| tree | 44c0b79d8f1812e76e90d0b41b6c9da314d6fd67 /gcc | |
| parent | 3adeccb3103059604d4a1d4ebe26c8d17c2e5942 (diff) | |
| download | gcc-41f7ed9c919b6db73b6751f2d8388cd4820105e3.tar.gz | |
PR rtl-optimization/54739
* config/microblaze/microblaze.md: (anddi3, iordi3, xordi3): Delete patterns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@194226 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/microblaze/microblaze.md | 81 |
2 files changed, 6 insertions, 81 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0ba2ae1822d..c261541e6ee 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2012-12-05 Michael Eager <eager@eagercon.com> + + PR rtl-optimization/54739 + * config/microblaze/microblaze.md: (anddi3, iordi3, xordi3): Delete + patterns. + 2012-12-05 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add new builtins. diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 18221b58156..8480b43f2c0 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -722,32 +722,6 @@ (set_attr "length" "4,8,8,8")]) -(define_insn "anddi3" - [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] - "" - "and\t%M0,%M1,%M2\;and\t%L0,%L1,%L2" - [(set_attr "type" "darith") - (set_attr "mode" "DI") - (set_attr "length" "8")]) - - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (and:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" "")))] - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) - && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" - - [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) - (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) - (subreg:SI (match_dup 2) 4)))] - "") - (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") @@ -762,34 +736,6 @@ (set_attr "mode" "SI,SI,SI,SI") (set_attr "length" "4,8,8,8")]) - -(define_insn "iordi3" - [(set (match_operand:DI 0 "register_operand" "=d") - (ior:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] - "" - "or\t%M0,%M1,%M2\;or\t%L0,%L1,%L2" - [(set_attr "type" "darith") - (set_attr "mode" "DI") - (set_attr "length" "8")] -) - - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ior:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" "")))] - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) - && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" - - [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) - (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) - (subreg:SI (match_dup 2) 4)))] - "") - (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d") (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") @@ -803,33 +749,6 @@ (set_attr "mode" "SI,SI,SI") (set_attr "length" "4,8,8")]) -(define_insn "xordi3" - [(set (match_operand:DI 0 "register_operand" "=d") - (xor:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] - "" - "xor\t%M0,%M1,%M2\;xor\t%L0,%L1,%L2" - [(set_attr "type" "darith") - (set_attr "mode" "DI") - (set_attr "length" "8")] -) - - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (xor:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" "")))] - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) - && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" - - [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) - (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) - (subreg:SI (match_dup 2) 4)))] - "") - ;;---------------------------------------------------------------- ;; Zero extension ;;---------------------------------------------------------------- |