invoke.texi: Document -mbitops for SH.

	* doc/invoke.texi: Document -mbitops for SH.
	* config/sh/constraints.md (K03, K12, Sbv, Sbw): New constraints.
	* config/sh/predicates.md (bitwise_memory_operand): New	predicate.
	* config/sh/sh.c (print_operand): Add %t operand code.
	* config/sh/sh.h (GO_IF_LEGITIMATE_INDEX): Add condition for SH2A.
	* config/sh/sh.md (*iorsi3_compact): Fix condition for SH2A.
	(extendqisi2_compact): Add the alternative for SH2A 4-byte mov.b.
	(extendqihi2): Likewise.
	(movqi_i): Likewise.
	(insv): Use bset, bclr and bst instructions for SH2A if	possible.
	(extv): Use bld instruction for SH2A if possible.
	(extzv): Likewise.
	(bclr_m2a, bclrmem_m2a, bset_m2a, bsetmem_m2a, bst_m2a, bld_m2a,
	bldsign_m2a, bld_reg, *bld_regqi, band_m2a, bandreg_m2a,
	bor_m2a, borreg_m2a, bxor_m2a, bxorreg_m2a): New insns.
	(bset.b, bclr.b): Define peepholes.
	* config/sh/sh.opt (mbitops): New option.

	* gcc.target/sh/sh2a-band.c: New test.
	* gcc.target/sh/sh2a-bclrmem.c: New test.
	* gcc.target/sh/sh2a-bld.c: New test.
	* gcc.target/sh/sh2a-bor.c: New test.
	* gcc.target/sh/sh2a-bsetmem.c: New test.
	* gcc.target/sh/sh2a-bxor.c: New test.

From-SVN: r133919

7 files changed, 435 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7b2bbe20e41..08e354548bb 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2008-04-04  Naveen.H.S  <naveen.hs@kpitcummins.com>
+
+	* gcc.target/sh/sh2a-band.c: New test.
+	* gcc.target/sh/sh2a-bclrmem.c: New test.
+	* gcc.target/sh/sh2a-bld.c: New test.
+	* gcc.target/sh/sh2a-bor.c: New test.
+	* gcc.target/sh/sh2a-bsetmem.c: New test.
+	* gcc.target/sh/sh2a-bxor.c: New test.
+
 2008-04-04  Janis Johnson  <janis187@us.ibm.com>
 
 	* g++.dg/other/anon5.C: Don't depend on line number for error message.
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-band.c b/gcc/testsuite/gcc.target/sh/sh2a-band.c
new file mode 100644
index 00000000000..34862b7256d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-band.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BAND.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "band.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BAND.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 & USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 & USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 & USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 & USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  &  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 &  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 &  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 &= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  &= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  &= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
new file mode 100644
index 00000000000..41cb3bdfedd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BCLR #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+/* { dg-final { scan-assembler "bclr.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 0;
+  PADDR.BIT.B3 = 0;
+  PADDR.BIT.B6 = 0;
+
+  PADDR.BIT.B1 &= 0;
+  PADDR.BIT.B4 &= 0;
+  PADDR.BIT.B7 &= 0;
+
+  PADDR.BIT.B10 = 0;
+  PADDR.BIT.B13 = 0;
+  PADDR.BIT.B15 = 0;
+
+  PADDR.BIT.B9 &= 0;
+  PADDR.BIT.B12 &= 0;
+  PADDR.BIT.B14 &= 0;
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bld.c b/gcc/testsuite/gcc.target/sh/sh2a-bld.c
new file mode 100644
index 00000000000..1cf56fe2714
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-bld.c
@@ -0,0 +1,43 @@
+/* A testcase to check generation of the following SH2A specific
+   instructions.
+
+    BLD #imm3, Rn
+    BLD.B #imm3, @(disp12, Rn)
+ */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-Os -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bld"} }  */
+/* { dg-final { scan-assembler "bld.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+int
+main ()
+{
+  volatile unsigned char a, b, c;
+  USRSTR.ICR0.BIT.BIT6 &= a;
+  USRSTR.ICR0.BIT.BIT5 |= b;
+  USRSTR.ICR0.BIT.BIT4 ^= c;
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bor.c b/gcc/testsuite/gcc.target/sh/sh2a-bor.c
new file mode 100644
index 00000000000..c3803c6b9ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-bor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 | USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 | USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 | USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  |  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 |  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 |  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 |= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  |= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  |= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
new file mode 100644
index 00000000000..b0ebf0851dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BSET #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+/* { dg-final { scan-assembler "bset.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 1;
+  PADDR.BIT.B3 = 1;
+  PADDR.BIT.B6 = 1;
+
+  PADDR.BIT.B1 |= 1;
+  PADDR.BIT.B4 |= 1;
+  PADDR.BIT.B7 |= 1;
+
+  PADDR.BIT.B10 = 1;
+  PADDR.BIT.B13 = 1;
+  PADDR.BIT.B15 = 1;
+
+  PADDR.BIT.B9  |= 1;
+  PADDR.BIT.B12 |= 1;
+  PADDR.BIT.B14 |= 1;
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bxor.c b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
new file mode 100644
index 00000000000..afe0a5ec979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BXOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bxor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BXOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 ^ USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 ^ USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 ^ USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 ^ USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  ^  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 ^  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 ^  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 ^= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  ^= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  ^= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a ^ USRSTR.ICR0.BIT.BIT1;
+  a = a ^ USRSTR.ICR0.BIT.BIT4;
+  a = a ^ USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}