Merge from trunk revision 257954.gccgo

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gccgo@257955 138bc75d-0d04-0410-961f-82ee72b054a4

56 files changed, 1226 insertions, 186 deletions

diff --git a/gcc/testsuite/gcc.target/aarch64/asm-2.c b/gcc/testsuite/gcc.target/aarch64/asm-2.c
index 3f978f5b234..65b3a84cfa1 100644
--- a/gcc/testsuite/gcc.target/aarch64/asm-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-2.c
@@ -6,5 +6,5 @@ int x;
 void
 f (void)
 {
-  asm volatile ("%a0" :: "X" (&x));
+  asm volatile ("%a0" :: "X" (&x)); /* { dg-error "invalid address mode" "" { target ilp32 } } */
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-4.c b/gcc/testsuite/gcc.target/aarch64/asm-4.c
new file mode 100644
index 00000000000..abe2af5f1d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+int x;
+
+void
+f (void)
+{
+  asm volatile ("%a0" :: "X" (__builtin_extend_pointer (&x)));
+}
diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp
index c54bca85fd9..04da2b0a20e 100644
--- a/gcc/testsuite/gcc.target/arm/multilib.exp
+++ b/gcc/testsuite/gcc.target/arm/multilib.exp
@@ -422,6 +422,7 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.base/nofp"
 	{-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp"
+	{-mcpu=cortex-r52 -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
 	{-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp"
@@ -466,6 +467,7 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard"
 	{-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
+	{-mcpu=cortex-r52 -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard"
 	{-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
 	{-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
 	{-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard"
@@ -494,6 +496,7 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.base/nofp"
 	{-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp"
 	{-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp"
+	{-mcpu=cortex-r52 -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp"
 	{-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp"
 	{-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp"
@@ -545,6 +548,12 @@ if {[multilib_config "rmprofile"] } {
 	{-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
+	{-march=armv8-r -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
+	{-march=armv8-r+crc -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
+	{-march=armv8-r+simd -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
+	{-march=armv8-r+crc+simd -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
+	{-march=armv8-r+crypto -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
+	{-march=armv8-r+crc+crypto -mfpu=auto -mfloat-abi=soft} "thumb/v7/nofp"
 	{-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp"
 	{-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp"
 	{-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp"
@@ -606,6 +615,10 @@ if {[multilib_config "rmprofile"] } {
 	{-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
 	{-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard"
 	{-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard"
+	{-march=armv8-r+simd -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard"
+	{-march=armv8-r+crc+simd -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard"
+	{-march=armv8-r+crypto -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard"
+	{-march=armv8-r+crc+crypto -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard"
 	{-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
 	{-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard"
 	{-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard"
@@ -657,6 +670,12 @@ if {[multilib_config "rmprofile"] } {
 	{-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
 	{-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp"
 	{-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp"
+	{-march=armv8-r -mfpu=auto -mfloat-abi=softfp} "thumb/v7/nofp"
+	{-march=armv8-r+crc -mfpu=auto -mfloat-abi=softfp} "thumb/v7/nofp"
+	{-march=armv8-r+simd -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp"
+	{-march=armv8-r+crc+simd -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp"
+	{-march=armv8-r+crypto -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp"
+	{-march=armv8-r+crc+crypto -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp"
 	{-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp"
 	{-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp"
 	{-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp"
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
index d9b861221f7..e5a8473abd4 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -mtune=generic -save-temps" } */
 /* { dg-require-effective-target avx2 } */
 
 
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
index 6f3ce1f0db9..3843932f4f7 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -mtune=generic -save-temps" } */
 /* { dg-require-effective-target avx2 } */
 
 
diff --git a/gcc/testsuite/gcc.target/i386/cet-intrin-3.c b/gcc/testsuite/gcc.target/i386/cet-intrin-3.c
index bcd7203fdb4..b98c1e928d5 100644
--- a/gcc/testsuite/gcc.target/i386/cet-intrin-3.c
+++ b/gcc/testsuite/gcc.target/i386/cet-intrin-3.c
@@ -10,24 +10,22 @@
 
 unsigned int f1 ()
 {
-  unsigned int x = 0;
-  return _rdsspd (x);
+  return _get_ssp ();
 }
 
 void f3 (unsigned int _a)
 {
-  _incsspd (_a);
+  _inc_ssp (_a);
 }
 
 #ifdef __x86_64__
 unsigned long long f2 ()
 {
-  unsigned long long x = 0;
-  return _rdsspq (x);
+  return _get_ssp ();
 }
 
 void f4 (unsigned int _a)
 {
-  _incsspq (_a);
+  _inc_ssp (_a);
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/i386/cet-intrin-4.c b/gcc/testsuite/gcc.target/i386/cet-intrin-4.c
index 437a4cd690c..86957b2eebe 100644
--- a/gcc/testsuite/gcc.target/i386/cet-intrin-4.c
+++ b/gcc/testsuite/gcc.target/i386/cet-intrin-4.c
@@ -5,27 +5,4 @@
 /* { dg-final { scan-assembler "incssp\[dq]\[ \t]+(%|)\[re]di" { target { ! ia32 } } } } */
 
 #include <immintrin.h>
-
-unsigned int f1 ()
-{
-  unsigned int x = 0;
-  return _rdsspd (x);
-}
-
-void f3 (unsigned int _a)
-{
-  _incsspd (_a);
-}
-
-#ifdef __x86_64__
-unsigned long long f2 ()
-{
-  unsigned long long x = 0;
-  return _rdsspq (x);
-}
-
-void f4 (unsigned int _a)
-{
-  _incsspq (_a);
-}
-#endif
+#include "cet-intrin-3.c"
diff --git a/gcc/testsuite/gcc.target/i386/cet-rdssp-1.c b/gcc/testsuite/gcc.target/i386/cet-rdssp-1.c
index fb50ff43504..6cd24f63384 100644
--- a/gcc/testsuite/gcc.target/i386/cet-rdssp-1.c
+++ b/gcc/testsuite/gcc.target/i386/cet-rdssp-1.c
@@ -5,18 +5,18 @@ void _exit(int status) __attribute__ ((__noreturn__));
 
 #ifdef __x86_64__
 # define incssp(x) __builtin_ia32_incsspq (x)
-# define rdssp(x) __builtin_ia32_rdsspq (x)
+# define rdssp() __builtin_ia32_rdsspq ()
 #else
 # define incssp(x) __builtin_ia32_incsspd (x)
-# define rdssp(x) __builtin_ia32_rdsspd (x)
+# define rdssp() __builtin_ia32_rdsspd ()
 #endif
 
 static void
 __attribute__ ((noinline, noclone))
 test (unsigned long frames)
 {
-  unsigned long ssp = 0;
-  ssp = rdssp (ssp);
+  unsigned long ssp;
+  ssp = rdssp ();
   if (ssp != 0)
     {
       unsigned long tmp = frames;
diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-17.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-17.c
index 1be4922fd53..faf304c3303 100644
--- a/gcc/testsuite/gcc.target/i386/chkp-stropt-17.c
+++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-17.c
@@ -51,7 +51,7 @@ void test_strcpy (void)
 
 void test_strcat (int n)
 {
-  strcat (a, a + 3);   /* { dg-warning ".strcat\.chkp. accessing 0 or more bytes at offsets 0 and 3 may overlap 1 byte" } */
+  strcat (a, a + 3);   /* { dg-warning ".strcat\.chkp. accessing 4 or more bytes at offsets 0 and 3 may overlap 1 byte at offset 3" } */
 }
 
 void test_strncat (int n)
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-11.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-11.c
new file mode 100644
index 00000000000..afa89ff227b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-11.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target { ! x32 } } } */
+/* { dg-options "-O2 -mindirect-branch=thunk-extern -fcf-protection -mcet -fcheck-pointer-bounds -mmpx" } */
+
+void
+bar (void)
+{ /* { dg-error "'-mindirect-branch=thunk-extern', '-fcf-protection=branch' and '-fcheck-pointer-bounds' are not compatible" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-12.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-12.c
new file mode 100644
index 00000000000..d456973ee6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-12.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target { ! x32 } } } */
+/* { dg-options "-O2 -mindirect-branch=thunk -fcf-protection -mcet -fcheck-pointer-bounds -mmpx" } */
+
+void
+bar (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-12.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-12.c
new file mode 100644
index 00000000000..24a1a08a3ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-12.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! x32 } } } */
+/* { dg-options "-O2 -mindirect-branch=keep -fcf-protection -mcet -fcheck-pointer-bounds -mmpx" } */
+
+__attribute__ ((indirect_branch("thunk-extern")))
+void
+bar (void)
+{ /* { dg-error "'-mindirect-branch=thunk-extern', '-fcf-protection=branch' and '-fcheck-pointer-bounds' are not compatible" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-13.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-13.c
new file mode 100644
index 00000000000..ff2fccae935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-13.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! x32 } } } */
+/* { dg-options "-O2 -mindirect-branch=keep -fcf-protection -mcet -fcheck-pointer-bounds -mmpx" } */
+
+__attribute__ ((indirect_branch("thunk-inline")))
+void
+bar (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-14.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-14.c
new file mode 100644
index 00000000000..669e56d7726
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-14.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=keep -fcf-protection -mcet" } */
+
+extern void (*bar) (void);
+
+__attribute__ ((indirect_branch("thunk-extern")))
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_indirect_thunk_nt" } } */
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-15.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-15.c
new file mode 100644
index 00000000000..c033fb23879
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-15.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mindirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=keep -fcf-protection -mcet" } */
+
+extern void (*bar) (void);
+
+__attribute__ ((indirect_branch("thunk-extern")))
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_indirect_thunk_nt" } } */
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-16.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-16.c
new file mode 100644
index 00000000000..0244edf53b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-16.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mindirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=keep -fcf-protection -mcet" } */
+
+extern void (*bar) (void) __attribute__((nocf_check));
+
+__attribute__ ((indirect_branch("thunk-extern")))
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_nt_(r|e)" } } */
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-10.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-10.c
new file mode 100644
index 00000000000..2a982ab69f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-10.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mindirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=thunk-extern -fcf-protection -mcet" } */
+
+extern void (*bar) (void) __attribute__((nocf_check));
+
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_nt_(r|e)" } } */
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-8.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-8.c
new file mode 100644
index 00000000000..30d12cc0711
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-8.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=thunk-extern -fcf-protection -mcet" } */
+
+extern void (*bar) (void);
+
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_indirect_thunk_nt" } } */
diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-9.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-9.c
new file mode 100644
index 00000000000..d714b0155df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-9.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mindirect-branch-register -mfunction-return=keep -fno-pic -fplt -mindirect-branch=thunk-extern -fcf-protection -mcet" } */
+
+extern void (*bar) (void);
+
+void
+foo (void)
+{
+  bar ();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_indirect_thunk_nt" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr57193.c b/gcc/testsuite/gcc.target/i386/pr57193.c
index ef209c9d211..5c6d7e495de 100644
--- a/gcc/testsuite/gcc.target/i386/pr57193.c
+++ b/gcc/testsuite/gcc.target/i386/pr57193.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -march=x86-64" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-sse3 -mtune=generic" } */
 /* { dg-final { scan-assembler-times "movdqa" 2 } } */
 
 #include <emmintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/pr70023.c b/gcc/testsuite/gcc.target/i386/pr70023.c
new file mode 100644
index 00000000000..5f6d138f28a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70023.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O -fno-sched-critical-path-heuristic -fschedule-insns -mavx -m8bit-idiv" } */
+
+typedef int v8si __attribute__ ((vector_size (32)));
+typedef __int128 i128;
+
+i128
+foo(int u16_0, int u64_0, i128 u128_0, i128 u128_1, v8si v32u32_0, v8si v32u32_1, v8si v32u64_1)
+{
+  v32u32_0[6] <<= u128_1 & 31;
+  v32u32_0 &= (v8si){v32u64_1[2], v32u32_1[6], 0xc5a661b, 0, 2};
+  u128_1 += 0x16fe7853d732;
+  v32u32_1 /= (v8si){v32u32_0[5], u128_1, 0x92d} | 1;
+  return u128_0 + v32u32_1[1];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr84146.c b/gcc/testsuite/gcc.target/i386/pr84146.c
index ba9b6336c0d..a14baa47532 100644
--- a/gcc/testsuite/gcc.target/i386/pr84146.c
+++ b/gcc/testsuite/gcc.target/i386/pr84146.c
@@ -1,6 +1,6 @@
 /* PR target/84146 */
 /* { dg-do compile } */
-/* { dg-options "-O2 -g -mcet -fcf-protection=full" } */
+/* { dg-options "-O2 -g -mcet -fcf-protection=full -fcompare-debug" } */
 
 int __setjmp (void **);
 void *buf[64];
diff --git a/gcc/testsuite/gcc.target/i386/pr84310-2.c b/gcc/testsuite/gcc.target/i386/pr84310-2.c
new file mode 100644
index 00000000000..e39a421e8d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr84310-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -malign-loops=16" } */
+/* { dg-warning "is obsolete" "" { target *-*-* } 0 } */
+
+void
+c (void)
+{  
+  for (;;)
+    ;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr84310.c b/gcc/testsuite/gcc.target/i386/pr84310.c
new file mode 100644
index 00000000000..f82327e45f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr84310.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -falign-functions=100000" } */
+/* { dg-error "is not between 0 and 65536" "" { target *-*-* } 0 } */
+
+void
+test_func (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/msp430/pr79242.c b/gcc/testsuite/gcc.target/msp430/pr79242.c
new file mode 100644
index 00000000000..d7ff8d38a3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/msp430/pr79242.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { "*-*-*" } { "-mcpu=msp430" "-msmall" } { "" } } */
+/* { dg-options "-mcpu=msp430x" } */
+
+typedef _Complex __int20 C;
+
+C
+foo (C x, C y)
+{
+  return x + y;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
index a1549118870..6f895336407 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
@@ -22,7 +22,7 @@
 /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
 /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
 /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times "lxvd2x" 36 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 36 } } */
 /* { dg-final { scan-assembler-times "lvewx" 2 } } */
 /* { dg-final { scan-assembler-times "lvxl" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-consts.c b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
index 36cb60c32b7..d59f9b4cf1c 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
@@ -1,5 +1,5 @@
-/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
-/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-do run { target vmx_hw } } */
+/* { dg-do compile } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-options "-maltivec -mabi=altivec -O2" } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
index 83d538b2cf3..a58680554d4 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8" } */
+/* { dg-options "-maltivec -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
index 24589b55639..3b67e5370a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 #include <altivec.h> // vector
 
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
index 9dc53da58ad..146f8b73c98 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mcpu=power9 -O1" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 
 #include <altivec.h>
 
@@ -47,6 +48,43 @@ test_vull_bperm_vull_vuc (vector unsigned long long x,
 	return vec_bperm (x, y);
 }
 
+vector signed char
+test_nabs_char (vector signed char x)
+{
+	return vec_nabs (x);
+}
+
+vector short
+test_nabs_short (vector short x)
+{
+  return vec_nabs (x);
+}
+
+vector int
+test_nabs_int (vector int x)
+{
+  return vec_nabs (x);
+}
+
+
+vector signed char
+test_neg_char (vector signed char x)
+{
+	return vec_neg (x);
+}
+
+vector short
+test_neg_short (vector short x)
+{
+	return vec_neg (x);
+}
+
+vector int
+test_neg_int (vector int x)
+{
+	return vec_neg (x);
+}
+
 /* Expected test results:
 
      test_ne_char              1 vcmpneb
@@ -57,6 +95,12 @@ test_vull_bperm_vull_vuc (vector unsigned long long x,
      test_vull_bperm_vull_vuc  1 vbpermd
      test_nabs_long_long (-O0) 1 xxspltib, 1 vsubudm, 1 vminsd
      test_nabs_long_long (-O1) 1 vnegd, vminsd
+     test_nabs_char (P9)       1 xxspltib, 1 vsububm, 1 vminsb
+     test_nabs_short (P9)      1 xxspltib, 1 vsubuhm, 1 vminsh
+     test_nabs_int (P9)        1 vnegw, 1 vminsw
+     test_neg_char (P9)        1 xxspltib, 1 vsububm
+     test_neg_short (P9)       1 xxspltib, 1 vsubuhm
+     test_neg_int (P9)         1 vnegw
 */
 
 /* { dg-final { scan-assembler-times "vcmpneb"  1 } } */
@@ -64,9 +108,16 @@ test_vull_bperm_vull_vuc (vector unsigned long long x,
 /* { dg-final { scan-assembler-times "vcmpnew"  1 } } */
 /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor"   1 } } */
-/* { dg-final { scan-assembler-times "xxspltib" 0 } } */
+/* { dg-final { scan-assembler-times "xxspltib" 4 } } */
 /* { dg-final { scan-assembler-times "vsubudm"  0 } } */
+/* { dg-final { scan-assembler-times "vsububm"  2 } } */
+/* { dg-final { scan-assembler-times "vsubuhm"  2 } } */
+/* { dg-final { scan-assembler-times "vsubuwm"  0 } } */
+/* { dg-final { scan-assembler-times "vminsb"   1 } } */
+/* { dg-final { scan-assembler-times "vminsh"   1 } } */
+/* { dg-final { scan-assembler-times "vminsw"   1 } } */
 /* { dg-final { scan-assembler-times "vminsd"   1 } } */
 /* { dg-final { scan-assembler-times "vnegd"    2 } } */
+/* { dg-final { scan-assembler-times "vnegw"    2 } } */
 /* { dg-final { scan-assembler-times "vbpermd"  1 } } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c
new file mode 100644
index 00000000000..104ae5587fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c
@@ -0,0 +1,162 @@
+/* { dg-do run { target { powerpc*-*-linux* && { p8vector_hw } } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=power8" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h> // vector
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#define ALL  1
+#define EVEN 2
+#define ODD  3
+
+void abort (void);
+
+void test_int_result(int check, vector int vec_result, vector int vec_expected)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		switch (check) {
+		case ALL:
+			break;
+		case EVEN:
+			if (i%2 == 0)
+				break;
+			else
+				continue;
+		case ODD:
+			if (i%2 != 0)
+				break;
+			else
+				continue;
+		}
+
+		if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+			printf("Test_int_result: ");
+			printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n",
+			       i, vec_result[i], i, vec_expected[i]);
+#else
+			abort();
+#endif
+		}
+	}
+}
+
+void test_unsigned_int_result(int check, vector unsigned int vec_result,
+			      vector unsigned int vec_expected)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		switch (check) {
+		case ALL:
+			break;
+		case EVEN:
+			if (i%2 == 0)
+				break;
+			else
+				continue;
+		case ODD:
+			if (i%2 != 0)
+				break;
+			else
+				continue;
+		}
+
+		if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+			printf("Test_unsigned int_result: ");
+			printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n",
+			       i, vec_result[i], i, vec_expected[i]);
+#else
+			abort();
+#endif
+		}
+
+	}
+}
+
+void test_result_sp(int check, vector float vec_result,
+		    vector float vec_expected)
+{
+	int i;
+	for(i = 0; i<4; i++) {
+
+		switch (check) {
+		case ALL:
+			break;
+		case EVEN:
+			if (i%2 == 0)
+				break;
+			else
+				continue;
+		case ODD:
+			if (i%2 != 0)
+				break;
+			else
+				continue;
+		}
+
+		if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+			printf("Test_result_sp: ");
+			printf("vec_result[%d] (%f) != vec_expected[%d] (%f)\n",
+			       i, vec_result[i], i, vec_expected[i]);
+#else
+			abort();
+#endif
+		}
+	}
+}
+
+int main()
+{
+	int i;
+	vector unsigned int vec_unint, vec_uns_int_expected, vec_uns_int_result;
+	vector signed int vec_int, vec_int_expected, vec_int_result;
+	vector float  vec_flt, vec_flt_result, vec_flt_expected;
+	vector long long int vec_ll_int0, vec_ll_int1;
+	vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1;
+	vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected;
+
+	vec_ll_int0 = (vector long long int){ -12, -12345678901234 };
+	vec_ll_int1 = (vector long long int){ 12, 9876543210 };
+	vec_ll_uns_int0 = (vector unsigned long long int){ 102, 9753108642 };
+	vec_ll_uns_int1 = (vector unsigned long long int){ 23, 29 };
+
+	/* Convert two double precision vector float to vector int */
+	vec_dble0 = (vector double){-124.930, 81234.49};
+	vec_dble1 = (vector double){-24.370, 8354.99};
+	vec_int_expected = (vector signed int){-124, 81234, -24, 8354};
+	vec_int_result = vec_signed2 (vec_dble0, vec_dble1);
+	test_int_result (ALL, vec_int_result, vec_int_expected);
+
+	/* Convert two double precision vector float to vector unsigned int */
+	vec_dble0 = (vector double){124.930, 8134.49};
+	vec_dble1 = (vector double){24.370, 834.99};
+	vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834};
+	vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1);
+	test_unsigned_int_result (ALL, vec_uns_int_result,
+				  vec_uns_int_expected);
+
+	/* conversion of two double precision vectors to single precision vector */
+	vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00};
+	vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1);
+	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+
+	vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00};
+	vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1);
+	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+
+	vec_dble0 = (vector double){ 34.0, 97.0 };
+	vec_dble1 = (vector double){ 214.0, -5.5 };
+	vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5};
+	vec_flt_result = vec_float2 (vec_dble0, vec_dble1);
+	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
index 15498173a34..325796c8b64 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
@@ -1,7 +1,6 @@
-/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-do run { target { vsx_hw } } } */
 /* { dg-require-effective-target vsx_hw } */
-/* { dg-options "-O2 -mvsx -mcpu=power8" } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=power8" } } */
+/* { dg-options "-maltivec -mvsx" } */
 
 #include <altivec.h> // vector
 
@@ -257,19 +256,6 @@ int main()
 	vec_flt_result = vec_float (vec_unint);
 	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
 
-	/* conversion of two double precision vectors to single precision vector */
-	vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00};
-	vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1);
-	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
-	vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00};
-	vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1);
-	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
-	vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5};
-	vec_flt_result = vec_float2 (vec_dble0, vec_dble1);
-	test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
 	/* conversion of even words in double precision vector to single precision vector */
 	vec_flt_expected = (vector float){-12.00, 00.00, -12345678901234.00, 0.00};
 	vec_flt_result = vec_floate (vec_ll_int0);
@@ -308,13 +294,6 @@ int main()
 	vec_ll_int_result = vec_signed (vec_dble0);
 	test_ll_int_result (vec_ll_int_result, vec_ll_int_expected);
 
-	/* Convert two double precision vector float to vector int */
-	vec_dble0 = (vector double){-124.930, 81234.49};
-	vec_dble1 = (vector double){-24.370, 8354.99};
-	vec_int_expected = (vector signed int){-124, 81234, -24, 8354};
-	vec_int_result = vec_signed2 (vec_dble0, vec_dble1);
-	test_int_result (ALL, vec_int_result, vec_int_expected);
-
 	/* Convert double precision vector float to vector int, even words */
 	vec_dble0 = (vector double){-124.930, 81234.49};
 	vec_int_expected = (vector signed int){-124, 0, 81234, 0};
@@ -334,14 +313,6 @@ int main()
 	test_ll_unsigned_int_result (vec_ll_uns_int_result,
 				     vec_ll_uns_int_expected);
 
-	/* Convert two double precision vector float to vector unsigned int */
-	vec_dble0 = (vector double){124.930, 8134.49};
-	vec_dble1 = (vector double){24.370, 834.99};
-	vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834};
-	vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1);
-	test_unsigned_int_result (ALL, vec_uns_int_result,
-				  vec_uns_int_expected);
-
 	/* Convert double precision vector float to vector unsigned int,
 	   even words */
 	vec_dble0 = (vector double){3124.930, 8234.49};
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c
index f7c3c3d9138..de378e09697 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c
@@ -1,5 +1,4 @@
-/* { dg-do run { target { powerpc*-*-linux* } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-do run { target { vsx_hw } } } */
 /* { dg-options "-O2 -mvsx -mcpu=power7" } */
 
 #include <altivec.h> // vector
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index 833116e597f..b8a6dcdbb33 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec -mvsx" } */
+/* { dg-options "-O2 -mvsx -mcpu=power6" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
index 162e26781a9..4f4e7a9ee5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run } */
 /* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target vsx_hw } */
-/* { dg-options "-maltivec -mvsx" } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mpower8-vector" } */
 
 #include <inttypes.h>
 #include <altivec.h> // vector
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-7-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-7-p9-runnable.c
new file mode 100644
index 00000000000..137b46b052a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-7-p9-runnable.c
@@ -0,0 +1,169 @@
+/* { dg-do run { target { powerpc*-*-* && p9vector_hw } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+#include <altivec.h>
+#define TRUE 1
+#define FALSE 0
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#define EXTRACT 0
+
+void abort (void);
+
+int result_wrong_ull (vector unsigned long long vec_expected,
+		      vector unsigned long long vec_actual)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    if (vec_expected[i] != vec_actual[i])
+      return TRUE;
+
+  return FALSE;
+}
+
+int result_wrong_uc (vector unsigned char vec_expected,
+		     vector unsigned char vec_actual)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (vec_expected[i] != vec_actual[i])
+      return TRUE;
+
+  return FALSE;
+}
+
+#ifdef DEBUG
+void print_ull (vector unsigned long long vec_expected,
+		vector unsigned long long vec_actual)
+{
+  int i;
+
+  printf("expected unsigned long long data\n");
+  for (i = 0; i < 2; i++)
+    printf(" %lld,", vec_expected[i]);
+
+  printf("\nactual signed char data\n");
+  for (i = 0; i < 2; i++)
+    printf(" %lld,", vec_actual[i]);
+  printf("\n");
+}
+
+void print_uc (vector unsigned char vec_expected,
+	       vector unsigned char vec_actual)
+{
+  int i;
+
+  printf("expected unsigned char data\n");
+  for (i = 0; i < 16; i++)
+    printf(" %d,", vec_expected[i]);
+
+  printf("\nactual unsigned char data\n");
+  for (i = 0; i < 16; i++)
+    printf(" %d,", vec_actual[i]);
+  printf("\n");
+}
+#endif
+
+#if EXTRACT
+vector unsigned long long
+vext (vector unsigned char *vc)
+{
+  return vextract_si_vchar (*vc, 5);
+}
+#endif
+
+int main()
+{
+   vector signed int vsi_arg;
+   vector unsigned char vec_uc_arg, vec_uc_result, vec_uc_expected;
+   vector unsigned long long vec_ull_result, vec_ull_expected;
+   unsigned long long ull_result, ull_expected;
+
+   vec_uc_arg = (vector unsigned char){1, 2, 3, 4,
+				       5, 6, 7, 8,
+				       9, 10, 11, 12,
+				       13, 14, 15, 16};
+
+   vsi_arg = (vector signed int){0xA, 0xB, 0xC, 0xD};
+
+   vec_uc_expected = (vector unsigned char){0xC, 0, 0, 0,
+					    5, 6, 7, 8,
+					    9, 10, 11, 12,
+					    13, 14, 15, 16};
+   /* Test vec_insert4b() */
+   /* Insert into char 0 location */
+   vec_uc_result = vec_insert4b (vsi_arg, vec_uc_arg, 0);
+
+   if (result_wrong_uc(vec_uc_expected, vec_uc_result))
+     {
+#ifdef DEBUG
+        printf("Error: vec_insert4b pos 0, result does not match expected result\n");
+	print_uc (vec_uc_expected, vec_uc_result);
+#else
+        abort();
+#endif
+      }
+
+   /* insert into char 4 location */
+   vec_uc_expected = (vector unsigned char){1, 2, 3, 4,
+					    0xC, 0, 0, 0,
+					    9, 10, 11, 12,
+					    13, 14, 15, 16};
+   vec_uc_result = vec_insert4b (vsi_arg, vec_uc_arg, 4);
+
+   if (result_wrong_uc(vec_uc_expected, vec_uc_result))
+     {
+#ifdef DEBUG
+        printf("Error: vec_insert4b pos 4, result does not match expected result\n");
+	print_uc (vec_uc_expected, vec_uc_result);
+#else
+        abort();
+#endif
+      }
+
+   /* Test vec_extract4b() */
+   /* Extract 4b, from char 0 location */
+   vec_uc_arg = (vector unsigned char){10, 0, 0, 0,
+				       20, 0, 0, 0,
+				       30, 0, 0, 0,
+				       40, 0, 0, 0};
+
+   vec_ull_expected = (vector unsigned long long){0, 10};
+   vec_ull_result = vec_extract4b(vec_uc_arg, 0);
+
+   if (result_wrong_ull(vec_ull_expected, vec_ull_result))
+     {
+#ifdef DEBUG
+        printf("Error: vec_extract4b pos 0, result does not match expected result\n");
+	print_ull (vec_ull_expected, vec_ull_result);
+#else
+        abort();
+#endif
+      }
+
+   /* Extract 4b, from char 12 location */
+   vec_uc_arg = (vector unsigned char){10, 0, 0, 0,
+				       20, 0, 0, 0,
+				       30, 0, 0, 0,
+				       40, 0, 0, 0};
+
+   vec_ull_expected = (vector unsigned long long){0, 40};
+   vec_ull_result = vec_extract4b(vec_uc_arg, 12);
+
+   if (result_wrong_ull(vec_ull_expected, vec_ull_result))
+     {
+#ifdef DEBUG
+        printf("Error: vec_extract4b pos 12, result does not match expected result\n");
+	print_ull (vec_ull_expected, vec_ull_result);
+#else
+        abort();
+#endif
+      }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
index 657188435d4..5d3d4aaf972 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
@@ -22,5 +22,5 @@ test2 (vector unsigned __int128 x, vector unsigned __int128 y)
   return vec_mul (x, y);
 }
 
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mmulld\M|\mmaddld\M} 6 } } */
 /* { dg-final { scan-assembler-times {\mmulhdu\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c
deleted file mode 100644
index 8e99de38271..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Verify that overloaded built-ins for vec_neg with int
-   inputs produce the right code when -mcpu=power7 is specified.  */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2 -mcpu=power7" } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-
-#include <altivec.h>
-
-vector signed int
-test1 (vector signed int x)
-{
-  return vec_neg (x);
-}
-
-/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c b/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c
index 15ec650c786..f48ef44e676 100644
--- a/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c
+++ b/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c
@@ -1,5 +1,5 @@
-/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
-/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-do run { target vmx_hw } } */
+/* { dg-do compile } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-options "-maltivec -mabi=altivec -O2" } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
index 71dd0a24ae1..6a7baf31b43 100644
--- a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
+++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
@@ -6,7 +6,7 @@
 /* { dg-options "-O0 -Wno-deprecated" } */
 /* { dg-final { scan-assembler-times "lvsl" 2 } } */
 /* { dg-final { scan-assembler-times "lvsr" 2 } } */
-/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
 /* { dg-final { scan-assembler-times "vperm" 2 } } */
 
 
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c b/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c
deleted file mode 100644
index fa1ba754705..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-1.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-#include <altivec.h>
-
-vector signed char
-vins_v4si (vector int *vi, vector signed char *vc)
-{
-  return vec_vinsert4b (*vi, *vc, 1);
-}
-
-vector unsigned char
-vins_di (long di, vector unsigned char *vc)
-{
-  return vec_vinsert4b (di, *vc, 2);
-}
-
-vector char
-vins_di2 (long *p_di, vector char *vc)
-{
-  return vec_vinsert4b (*p_di, *vc, 3);
-}
-
-vector unsigned char
-vins_di0 (vector unsigned char *vc)
-{
-  return vec_vinsert4b (0, *vc, 4);
-}
-
-long
-vext (vector signed char *vc)
-{
-  return vec_vextract4b (*vc, 5);
-}
-
-/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
-/* { dg-final { scan-assembler "xxinsertw" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c b/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c
deleted file mode 100644
index 3b5872ebec6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-#include <altivec.h>
-
-vector signed char
-ins_v4si (vector int vi, vector signed char vc)
-{
-  return vec_vinsert4b (vi, vc, 13);	/* { dg-error "vec_vinsert4b" } */
-}
-
-vector unsigned char
-ins_di (long di, vector unsigned char vc, long n)
-{
-  return vec_vinsert4b (di, vc, n);	/* { dg-error "vec_vinsert4b" } */
-}
-
-long
-vext1 (vector signed char vc)
-{
-  return vec_vextract4b (vc, 13);	/* { dg-error "vec_vextract4b" } */
-}
-
-long
-vextn (vector unsigned char vc, long n)
-{
-  return vec_vextract4b (vc, n);	/* { dg-error "vec_vextract4b" } */
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90 b/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90
index a1248bee044..91b961aebce 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90
@@ -25,11 +25,11 @@ program stream_test
     rewind(10)
     read(10,*) str1
     read(10,*) str2
-    if(str1 /= rec1 .or. str2 /= rec2) call abort()
+    if(str1 /= rec1 .or. str2 /= rec2) STOP 1
     rewind(10)
     read(10,'(a)') str1
     read(10,'(a)') str2
-    if(str1 /= rec1 .or. str2 /= rec2) call abort()
+    if(str1 /= rec1 .or. str2 /= rec2) STOP 2
     close(10)
 
     open(10,form='formatted',access='stream',&
@@ -40,7 +40,7 @@ program stream_test
     read(10,*) i,str1
     read(10,*) r
     if(i /= 123 .or. str1 /= rec1 .or. r /= 12345.6789) &
-      call abort()
+      STOP 3
     close(10)
 
     open(unit=10,form='unformatted',access='stream', &
@@ -49,5 +49,5 @@ program stream_test
     len = len_trim(rec1//new_line('a')//rec2)
     rewind(10)
     read(10) str1(1:len)
-    if(str1 /= rec1//new_line('a')//rec2) call abort()
+    if(str1 /= rec1//new_line('a')//rec2) STOP 4
 end program stream_test
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79439-1.c b/gcc/testsuite/gcc.target/powerpc/pr79439-1.c
new file mode 100644
index 00000000000..5732a236c8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr79439-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-options "-O2 -fpic -fno-reorder-blocks" } */
+
+/* On the Linux 64-bit ABIs, we eliminate NOP in the 'rec' call even if
+   -fpic is used.  The recursive call should call the local alias.  The
+   Linux 32-bit ABIs do not require NOPs after the BL instruction.  */
+
+int f (void);
+
+void
+g (void)
+{
+}
+
+int
+rec (int a)
+{
+  int ret = 0;
+  if (a > 10 && f ())
+    ret += rec (a - 1);
+  g ();
+  return a + ret;
+}
+
+/* { dg-final { scan-assembler-times {\mbl f\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mbl g\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mbl rec\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mnop\M}    2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79439.c b/gcc/testsuite/gcc.target/powerpc/pr79439-2.c
index 23c9a24fdc3..b53af445265 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79439.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79439-2.c
@@ -1,9 +1,9 @@
-/* { dg-do compile { target { powerpc64*-*-linux* && lp64 } } } */
-/* { dg-options "-O2 -fpic" } */
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-options "-O2 -fpic -fno-reorder-blocks" } */
 
 /* On the Linux 64-bit ABIs, we should not eliminate NOP in the 'rec' call if
-   -fpic is used because rec can be interposed at link time (since it is
-   external), and the recursive call should call the interposed function.  The
+   -fpic is used because rec can be interposed at link time (since it has an
+   alias), and the recursive call should call the interposed function.  The
    Linux 32-bit ABIs do not require NOPs after the BL instruction.  */
 
 int f (void);
@@ -23,6 +23,8 @@ rec (int a)
   return a + ret;
 }
 
+int rec_alias (int) __attribute__ ((alias ("rec")));
+
 /* { dg-final { scan-assembler-times {\mbl f\M}   1 } } */
 /* { dg-final { scan-assembler-times {\mbl g\M}   1 } } */
 /* { dg-final { scan-assembler-times {\mbl rec\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79439-3.c b/gcc/testsuite/gcc.target/powerpc/pr79439-3.c
new file mode 100644
index 00000000000..762ca44b177
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr79439-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { powerpc-*-linux* && ilp32 } } } */
+/* { dg-options "-O2 -fpic -fno-reorder-blocks" } */
+
+/* Analog of pr79439-1.c for 32-bit Linux.  */
+
+int f (void);
+
+void
+g (void)
+{
+}
+
+int
+rec (int a)
+{
+  int ret = 0;
+  if (a > 10 && f ())
+    ret += rec (a - 1);
+  g ();
+  return a + ret;
+}
+
+/* { dg-final { scan-assembler-times {\mbl f@plt\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mbl g@plt\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mbl rec@plt\M} 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c b/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c
index 165079a3a6c..b5d007e082f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile { target { powerpc_p8vector_ok } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
 /* { dg-require-effective-target vect_int } */
 /* { dg-options "-mcpu=power8 -O3 -fdump-tree-slp-details" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c b/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c
index a81f90ac3c4..302b1c5040f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile { target { powerpc_p9vector_ok } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target vect_int } */
 /* { dg-options "-mcpu=power9 -O3 -fdump-tree-slp-details" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr81572.c b/gcc/testsuite/gcc.target/powerpc/pr81572.c
new file mode 100644
index 00000000000..de00c187d62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr81572.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc64*-*-* } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-not "xxlor" } } */
+
+#include <altivec.h>
+
+typedef __vector unsigned char nvec_t;
+
+long testz_and(nvec_t a, nvec_t b)
+{
+  nvec_t c = vec_andc(a, b);
+  return vec_all_eq(a, c);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c
new file mode 100644
index 00000000000..2536fc30b98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c
@@ -0,0 +1,97 @@
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sld() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+typedef vector bool char vbc_t;
+typedef vector signed char vsc_t;
+typedef vector unsigned char vuc_t;
+typedef vector bool int vbi_t;
+typedef vector signed int vsi_t;
+typedef vector unsigned int vui_t;
+typedef vector pixel vp_t;
+typedef vector bool short vbs_t;
+typedef vector signed short vss_t;
+typedef vector unsigned short vus_t;
+typedef vector float vf_t;
+
+void 
+test_vbc ( vbc_t v1, vbc_t v2, vbc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vbi ( vbi_t v1, vbi_t v2, vbi_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vui ( vui_t v1, vui_t v2, vui_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vp ( vp_t v1, vp_t v2, vp_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vbs ( vbs_t v1, vbs_t v2, vbs_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vss ( vss_t v1, vss_t v2, vss_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vus ( vus_t v1, vus_t v2, vus_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vf ( vf_t v1, vf_t v2, vf_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c
new file mode 100644
index 00000000000..5e973e01aa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c
@@ -0,0 +1,41 @@
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sld() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector" } */
+
+#include <altivec.h>
+
+typedef  vector  bool long long vbl_t;
+typedef  vector  signed long long vsl_t;
+typedef  vector  unsigned long long vul_t;
+typedef  vector  double vd_t;
+
+void 
+test_vbl ( vbl_t v1, vbl_t v2, vbl_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vul ( vul_t v1, vul_t v2, vul_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vd ( vd_t v1, vd_t v2, vd_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c
new file mode 100644
index 00000000000..a3b4be6686b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c
@@ -0,0 +1,80 @@
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sldw() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+#include <altivec.h>
+
+typedef  vector bool char vbc_t;
+typedef  vector  signed char vsc_t;
+typedef  vector  unsigned char vuc_t;
+typedef  vector  bool int vbi_t;
+typedef  vector  signed int vsi_t;
+typedef  vector  unsigned int vui_t;
+typedef  vector  pixel vp_t;
+typedef  vector  bool short vbs_t;
+typedef  vector  signed short vss_t;
+typedef  vector  unsigned short vus_t;
+typedef  vector  float vf_t;
+typedef  vector  bool long long vbl_t;
+typedef  vector  signed long long vsl_t;
+typedef  vector  unsigned long long vul_t;
+typedef  vector  double vd_t;
+
+void 
+test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vui ( vui_t v1, vui_t v2, vui_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vul ( vul_t v1, vul_t v2, vul_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vss ( vss_t v1, vss_t v2, vss_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vus ( vus_t v1, vus_t v2, vus_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
new file mode 100644
index 00000000000..8a802eb337e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
@@ -0,0 +1,100 @@
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling vec_xxpermdi() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#include <altivec.h>
+void abort (void);
+
+vector double vdx = { 0.0, 1.0 };
+vector double vdy = { 2.0, 3.0 };
+vector double vdz;
+
+vector signed long long vsllx = { 0, 1 };
+vector signed long long vslly = { 2, 3 };
+vector signed long long vsllz;
+
+vector unsigned long long vullx = { 0, 1 };
+vector unsigned long long vully = { 2, 3 };
+vector unsigned long long vullz;
+
+vector float vfx = { 0.0, 1.0, 2.0, 3.0 };
+vector float vfy = { 4.0, 5.0, 6.0, 7.0 };
+vector float vfz;
+
+vector signed int vsix = { 0, 1, 2, 3 };
+vector signed int vsiy = { 4, 5, 6, 7 };
+vector signed int vsiz;
+
+vector unsigned int vuix = { 0, 1, 2, 3 };
+vector unsigned int vuiy = { 4, 5, 6, 7 };
+vector unsigned int vuiz;
+
+vector signed short vssx = { 0, 1, 2, 3, 4, 5, 6, 7 };
+vector signed short vssy = { 8, 9, 10, 11, 12, 13, 14, 15 };
+vector signed short vssz;
+
+vector unsigned short vusx = { 0, 1, 2, 3, 4, 5, 6, 7 };
+vector unsigned short vusy = { 8, 9, 10, 11, 12, 13, 14, 15 };
+vector unsigned short vusz;
+
+vector signed char vscx = { 0, 1, 2, 3, 4, 5, 6, 7,
+			    8, 9, 10, 11, 12, 13, 14, 15 };
+vector signed char vscy = { 16, 17, 18, 19, 20, 21, 22, 23,
+			    24, 25, 26, 27, 28, 29, 30, 31 };
+vector signed char vscz;
+
+vector unsigned char vucx = { 0, 1, 2, 3, 4, 5, 6, 7,
+			    8, 9, 10, 11, 12, 13, 14, 15 };
+vector unsigned char vucy = { 16, 17, 18, 19, 20, 21, 22, 23,
+			    24, 25, 26, 27, 28, 29, 30, 31 };
+vector unsigned char vucz;
+
+int
+main ()
+{
+  vdz = vec_xxpermdi (vdx, vdy, 0b01);
+  if (vdz[0] != 0.0 || vdz[1] != 3.0)
+    abort ();
+  vdz = vec_xxpermdi (vdx, vdy, vscx); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vsllz = vec_xxpermdi (vsllx, vslly, 0b10);
+  vsllz = vec_xxpermdi (vsllx, vslly, vslly); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vullz = vec_xxpermdi (vullx, vully, 0b10);
+  vullz = vec_xxpermdi (vullx, vully, vully); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vsllz[0] != 1 || vsllz[1] != 2)
+    abort ();
+
+  vfz = vec_xxpermdi (vfx, vfy, 0b01);
+  vfz = vec_xxpermdi (vfx, vfy, vfy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vfz[0] != 0.0 || vfz[1] != 1.0 || vfz[2] != 6.0 || vfz[3] != 7.0)
+    abort ();
+
+  vsiz = vec_xxpermdi (vsix, vsiy, 0b10);
+  vsiz = vec_xxpermdi (vsix, vsiy, vsiy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vuiz = vec_xxpermdi (vuix, vuiy, 0b10);
+  vuiz = vec_xxpermdi (vuix, vuiy, vuiy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vsiz[0] != 2 || vsiz[1] != 3 || vsiz[2] != 4 || vsiz[3] != 5)
+    abort ();
+
+  vssz = vec_xxpermdi (vssx, vssy, 0b00);
+  vssz = vec_xxpermdi (vssx, vssy, vssy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vusz = vec_xxpermdi (vusx, vusy, 0b00);
+  vusz = vec_xxpermdi (vusx, vusy, vusy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vssz[0] != 0 || vssz[1] != 1 || vssz[2] != 2 || vssz[3] != 3
+      || vssz[4] != 8 || vssz[5] != 9 || vssz[6] != 10 || vssz[7] != 11)
+    abort ();
+
+  vscz = vec_xxpermdi (vscx, vscy, 0b11);
+  vscz = vec_xxpermdi (vscx, vscy, vscy);/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vucz = vec_xxpermdi (vucx, vucy, 0b11);
+  vucz = vec_xxpermdi (vucx, vucy, vucy);/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vscz[0] != 8 || vscz[1] != 9 || vscz[2] != 10 || vscz[3] != 11
+      || vscz[4] != 12 || vscz[5] != 13 || vscz[6] != 14 || vscz[7] != 15
+      || vscz[8] != 24 || vscz[9] != 25 || vscz[10] != 26 || vscz[11] != 27
+      || vscz[12] != 28 || vscz[13] != 29 || vscz[14] != 30 || vscz[15] != 31)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c b/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c
new file mode 100644
index 00000000000..06e485dc45c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c
@@ -0,0 +1,151 @@
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling vec_xxsldwi() and vec_xxpermdi() with invalid parameters.  */
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+#include <altivec.h>
+
+vector double
+v2df_shift (vector double a, vector double b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector float
+v4sf_shift (vector float a, vector float b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector long long
+v2di_shift (vector long long a, vector long long b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_shift (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector int
+v4si_shift (vector int a, vector int b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_shift (vector unsigned int a, vector unsigned int b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector short
+v8hi_shift (vector short a, vector short b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_shift (vector unsigned short a, vector unsigned short b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector signed char
+v16qi_shift (vector signed char a, vector signed char b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_shift (vector unsigned char a, vector unsigned char b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector double
+v2df_permute (vector double a, vector double b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector float
+v4sf_permute (vector float a, vector float b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector long long
+v2di_permute (vector long long a, vector long long b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_permute (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector int
+v4si_permute (vector int a, vector int b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_permute (vector unsigned int a, vector unsigned int b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector short
+v8hi_permute (vector short a, vector short b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+;
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_permute (vector unsigned short a, vector unsigned short b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector signed char
+v16qi_permute (vector signed char a, vector signed char b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_permute (vector unsigned char a, vector unsigned char b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c b/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c
index 492cd2d76a2..691b378698f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c
@@ -1,6 +1,7 @@
 /* { dg-do run { target { powerpc64le*-*-linux* } } } */
 /* { dg-require-effective-target vsx_hw } */
-/* { dg-options "-O2 -mvsx -maltivec=be" } */
+/* Disable warnings to squelch deprecation message about -maltivec=be.  */
+/* { dg-options "-w -O2 -mvsx -maltivec=be" } */
 
 /* Test various ways of creating vectors with 2 double words and accessing the
    elements.  This test uses the long (on 64-bit systems) or long long datatype
diff --git a/gcc/testsuite/gcc.target/rx/pr83831.c b/gcc/testsuite/gcc.target/rx/pr83831.c
new file mode 100644
index 00000000000..27d4a89cff4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/pr83831.c
@@ -0,0 +1,79 @@
+/* { dg-do compile }  */
+/* { dg-options "-O1" }  */
+/* { dg-final { scan-assembler-times "bclr" 6 } }  */
+/* { dg-final { scan-assembler-times "bset" 7 } }  */
+/* { dg-final { scan-assembler-times "bnot" 7 } }  */
+
+void
+test_0 (char* x, unsigned int y)
+{
+  /* Expect 4x bclr here.  */
+  x[0] &= 0xFE;
+  x[1] = y & ~(1 << 1);
+  x[2] &= 0xFE;
+  x[65000] &= 0xFE;
+}
+
+unsigned int
+test_1 (unsigned int x, unsigned int y)
+{
+  /* Expect 1x bclr here.  */
+  return x & ~(1 << y);
+}
+
+unsigned int
+test_2 (unsigned int x)
+{
+  /* Expect 1x bclr here.  */
+  return x & ~(1 << 1);
+}
+
+void
+test_3 (char* x, unsigned int y, unsigned int z)
+{
+  /* Expect 5x bset here.  */
+  x[0] |= 0x10;
+  x[1] = y | (1 << 1);
+  x[2] |= 0x10;
+  x[65000] |= 0x10;
+  x[5] |= 1 << z;
+}
+
+unsigned int
+test_4 (unsigned int x, unsigned int y)
+{
+  /* Expect 1x bset here.  */
+  return x | (1 << y);
+}
+
+unsigned int
+test_5 (unsigned int x)
+{
+  /* Expect 1x bset here.  */
+  return x | (1 << 8);
+}
+
+void
+test_6 (char* x, unsigned int y, unsigned int z)
+{
+  /* Expect 5x bnot here.  */
+  x[0] ^= 0x10;
+  x[1] = y ^ (1 << 1);
+  x[2] ^= 0x10;
+  x[65000] ^= 0x10;
+  x[5] ^= 1 << z;
+}
+
+unsigned int
+test_7 (unsigned int x, unsigned int y)
+{
+  /* Expect 1x bnot here.  */
+  return x ^ (1 << y);
+}
+
+unsigned int
+test_8 (unsigned int x)
+{
+  /* Expect 1x bnot here.  */
+  return x ^ (1 << 8);
+}