RISC-V: Introduce rounding mode operand into fixed-point intrinsics

According to new comming fixed-point API:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

Introduce vxrm argument:
- vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vl);
+ vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vxrm, size_t vl);

This patch doesn't insert vxrm csrw configuration instruction yet.
Will support automatically insert csrw vxrm instruction in the next patch.

This patch does this following:
1. Only extend the vxrm argument.
2. Check vxrm argument is invalid immediate and report error message if it is invalid.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Introduce rounding mode.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
	(struct narrow_alu_def): Ditto.
	* config/riscv/riscv-vector-builtins.cc (function_builder::apply_predication): Ditto.
	(function_expander::use_exact_insn): Ditto.
	* config/riscv/riscv-vector-builtins.h (function_checker::arg_num): New function.
	(function_base::has_rounding_mode_operand_p): New function.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-11.C: Adapt testcase.
	* g++.target/riscv/rvv/base/bug-12.C: Ditto.
	* g++.target/riscv/rvv/base/bug-14.C: Ditto.
	* g++.target/riscv/rvv/base/bug-15.C: Ditto.
	* g++.target/riscv/rvv/base/bug-16.C: Ditto.
	* g++.target/riscv/rvv/base/bug-17.C: Ditto.
	* g++.target/riscv/rvv/base/bug-18.C: Ditto.
	* g++.target/riscv/rvv/base/bug-19.C: Ditto.
	* g++.target/riscv/rvv/base/bug-20.C: Ditto.
	* g++.target/riscv/rvv/base/bug-21.C: Ditto.
	* g++.target/riscv/rvv/base/bug-22.C: Ditto.
	* g++.target/riscv/rvv/base/bug-23.C: Ditto.
	* g++.target/riscv/rvv/base/bug-3.C: Ditto.
	* g++.target/riscv/rvv/base/bug-5.C: Ditto.
	* g++.target/riscv/rvv/base/bug-6.C: Ditto.
	* g++.target/riscv/rvv/base/bug-8.C: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: Ditto.
	* gcc.target/riscv/rvv/base/merge_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-7.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-2.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-3.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-4.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-5.c: New test.

1 files changed, 2 insertions, 2 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
index a3d08de06c4..b04e03b5894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
@@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
 {
   vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
   vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
-  vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4);
-  vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4);
+  vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 0, 4);
+  vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 0, 4);
   __riscv_vse64_v_u64m1 (out + 2, v4, 4);
 }