diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-10-06 08:59:14 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-10-06 08:59:14 +0000 |
| commit | 5a162b7ae6b7d344af6a033e922bc5e0e77eb6aa (patch) | |
| tree | 56aca246b6ab6aeda938b1018391b7f1c5d7df72 /gcc/config | |
| parent | f68b5712b23021c39d8c91b2c98130266b9504a3 (diff) | |
| download | gcc-5a162b7ae6b7d344af6a033e922bc5e0e77eb6aa.tar.gz | |
2010-10-06 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 165014
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@165017 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
99 files changed, 9333 insertions, 1016 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 49c86fd9310..46627e379a2 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -215,11 +215,6 @@ alpha_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - break; - case OPT_mfp_regs: if (value == 0) target_flags |= MASK_SOFT_FP; @@ -487,7 +482,7 @@ alpha_option_override (void) } /* Default the definition of "small data" to 8 bytes. */ - if (!g_switch_set) + if (!global_options_set.x_g_switch_value) g_switch_value = 8; /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */ @@ -775,7 +770,7 @@ alpha_in_small_data_p (const_tree exp) /* If this is an incomplete type with size 0, then we can't put it in sdata because it might be too big when completed. */ - if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) + if (size > 0 && size <= g_switch_value) return true; } @@ -6634,6 +6629,36 @@ static GTY(()) tree alpha_v8qi_s; static GTY(()) tree alpha_v4hi_u; static GTY(()) tree alpha_v4hi_s; +static GTY(()) tree alpha_builtins[(int) ALPHA_BUILTIN_max]; + +/* Return the alpha builtin for CODE. */ + +static tree +alpha_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (code >= ALPHA_BUILTIN_max) + return error_mark_node; + return alpha_builtins[code]; +} + +/* Helper function of alpha_init_builtins. Add the built-in specified + by NAME, TYPE, CODE, and ECF. */ + +static void +alpha_builtin_function (const char *name, tree ftype, + enum alpha_builtin code, unsigned ecf) +{ + tree decl = add_builtin_function (name, ftype, (int) code, + BUILT_IN_MD, NULL, NULL_TREE); + + if (ecf & ECF_CONST) + TREE_READONLY (decl) = 1; + if (ecf & ECF_NOTHROW) + TREE_NOTHROW (decl) = 1; + + alpha_builtins [(int) code] = decl; +} + /* Helper function of alpha_init_builtins. Add the COUNT built-in functions pointed to by P, with function type FTYPE. */ @@ -6641,26 +6666,19 @@ static void alpha_add_builtins (const struct alpha_builtin_def *p, size_t count, tree ftype) { - tree decl; size_t i; for (i = 0; i < count; ++i, ++p) if ((target_flags & p->target_mask) == p->target_mask) - { - decl = add_builtin_function (p->name, ftype, p->code, BUILT_IN_MD, - NULL, NULL); - if (p->is_const) - TREE_READONLY (decl) = 1; - TREE_NOTHROW (decl) = 1; - } + alpha_builtin_function (p->name, ftype, p->code, + (p->is_const ? ECF_CONST : 0) | ECF_NOTHROW); } - static void alpha_init_builtins (void) { tree dimode_integer_type_node; - tree ftype, decl; + tree ftype; dimode_integer_type_node = lang_hooks.types.type_for_mode (DImode, 0); @@ -6686,30 +6704,26 @@ alpha_init_builtins (void) ftype); ftype = build_function_type (ptr_type_node, void_list_node); - decl = add_builtin_function ("__builtin_thread_pointer", ftype, - ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD, - NULL, NULL); - TREE_NOTHROW (decl) = 1; + alpha_builtin_function ("__builtin_thread_pointer", ftype, + ALPHA_BUILTIN_THREAD_POINTER, ECF_NOTHROW); ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); - decl = add_builtin_function ("__builtin_set_thread_pointer", ftype, - ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD, - NULL, NULL); - TREE_NOTHROW (decl) = 1; + alpha_builtin_function ("__builtin_set_thread_pointer", ftype, + ALPHA_BUILTIN_SET_THREAD_POINTER, ECF_NOTHROW); if (TARGET_ABI_OPEN_VMS) { ftype = build_function_type_list (ptr_type_node, ptr_type_node, NULL_TREE); - add_builtin_function ("__builtin_establish_vms_condition_handler", ftype, - ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER, - BUILT_IN_MD, NULL, NULL_TREE); + alpha_builtin_function ("__builtin_establish_vms_condition_handler", + ftype, + ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER, + 0); ftype = build_function_type_list (ptr_type_node, void_type_node, NULL_TREE); - add_builtin_function ("__builtin_revert_vms_condition_handler", ftype, - ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER, - BUILT_IN_MD, NULL, NULL_TREE); + alpha_builtin_function ("__builtin_revert_vms_condition_handler", ftype, + ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER, 0); } alpha_v8qi_u = build_vector_type (unsigned_intQI_type_node, 8); @@ -11082,6 +11096,8 @@ alpha_init_libfuncs (void) #undef TARGET_HAVE_TLS #define TARGET_HAVE_TLS HAVE_AS_TLS +#undef TARGET_BUILTIN_DECL +#define TARGET_BUILTIN_DECL alpha_builtin_decl #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS alpha_init_builtins #undef TARGET_EXPAND_BUILTIN diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index be885c1235d..bdf31599d07 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -144,8 +144,6 @@ enum alpha_fp_trap_mode ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ }; -extern int target_flags; - extern enum alpha_trap_precision alpha_tp; extern enum alpha_fp_rounding_mode alpha_fprm; extern enum alpha_fp_trap_mode alpha_fptm; diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index bcf572f849f..579fa0154f2 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6588,15 +6588,17 @@ emit_insn (gen_subdi3 (want, stack_pointer_rtx, force_reg (Pmode, operands[1]))); - emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); if (!CONST_INT_P (operands[1])) { + rtx limit = GEN_INT (4096); out_label = gen_label_rtx (); - test = gen_rtx_GEU (VOIDmode, want, tmp); - emit_jump_insn (gen_cbranchdi4 (test, want, tmp, out_label)); + test = gen_rtx_LTU (VOIDmode, operands[1], limit); + emit_jump_insn + (gen_cbranchdi4 (test, operands[1], limit, out_label)); } + emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); emit_label (loop_label); memref = gen_rtx_MEM (DImode, tmp); MEM_VOLATILE_P (memref) = 1; diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h index 57ab91e2f3c..78b2858db56 100644 --- a/gcc/config/alpha/elf.h +++ b/gcc/config/alpha/elf.h @@ -121,7 +121,7 @@ do { \ #undef ASM_OUTPUT_ALIGNED_LOCAL #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ do { \ - if ((SIZE) <= g_switch_value) \ + if ((SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ switch_to_section (sbss_section); \ else \ switch_to_section (bss_section); \ diff --git a/gcc/config/alpha/gnu.h b/gcc/config/alpha/gnu.h index f98c3e72e90..ca719803906 100644 --- a/gcc/config/alpha/gnu.h +++ b/gcc/config/alpha/gnu.h @@ -1,6 +1,6 @@ /* Configuration for an Alpha running GNU with ELF as the target machine. -Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. +Copyright (C) 2002, 2003, 2004, 2010 Free Software Foundation, Inc. This file is part of GCC. @@ -29,7 +29,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #undef TARGET_OS_CPP_BUILTINS /* config.gcc includes alpha/linux.h. */ #define TARGET_OS_CPP_BUILTINS() \ do { \ - HURD_TARGET_OS_CPP_BUILTINS(); \ + LINUX_TARGET_OS_CPP_BUILTINS(); \ builtin_define ("_LONGLONG"); \ } while (0) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 44cbc8e1353..7a8155d2fbc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -193,12 +193,13 @@ static bool arm_align_anon_bitfield (void); static bool arm_return_in_msb (const_tree); static bool arm_must_pass_in_stack (enum machine_mode, const_tree); static bool arm_return_in_memory (const_tree, const_tree); -#ifdef TARGET_UNWIND_INFO +#if ARM_UNWIND_INFO static void arm_unwind_emit (FILE *, rtx); static bool arm_output_ttype (rtx); static void arm_asm_emit_except_personality (rtx); static void arm_asm_init_sections (void); #endif +static enum unwind_info_type arm_except_unwind_info (void); static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); static rtx arm_dwarf_register_span (rtx); @@ -241,6 +242,11 @@ static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); static unsigned int arm_units_per_simd_word (enum machine_mode); static bool arm_class_likely_spilled_p (reg_class_t); +static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); +static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, + const_tree type, + int misalignment, + bool is_packed); /* Table of machine attributes. */ @@ -461,7 +467,7 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_MUST_PASS_IN_STACK #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack -#ifdef TARGET_UNWIND_INFO +#if ARM_UNWIND_INFO #undef TARGET_ASM_UNWIND_EMIT #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit @@ -477,7 +483,10 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_ASM_INIT_SECTIONS #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections -#endif /* TARGET_UNWIND_INFO */ +#endif /* ARM_UNWIND_INFO */ + +#undef TARGET_EXCEPT_UNWIND_INFO +#define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec @@ -553,6 +562,14 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CLASS_LIKELY_SPILLED_P #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p +#undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE +#define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \ + arm_vector_alignment_reachable + +#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT +#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ + arm_builtin_support_vector_misalignment + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -2032,7 +2049,7 @@ arm_compute_func_type (void) if (optimize > 0 && (TREE_NOTHROW (current_function_decl) || !(flag_unwind_tables - || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) + || (flag_exceptions && arm_except_unwind_info () != UI_SJLJ))) && TREE_THIS_VOLATILE (current_function_decl)) type |= ARM_FT_VOLATILE; @@ -8830,7 +8847,8 @@ neon_vector_mem_operand (rtx op, int type) return arm_address_register_rtx_p (ind, 0); /* Allow post-increment with Neon registers. */ - if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) + if ((type != 1 && GET_CODE (ind) == POST_INC) + || (type == 0 && GET_CODE (ind) == PRE_DEC)) return arm_address_register_rtx_p (XEXP (ind, 0), 0); /* FIXME: vld1 allows register post-modify. */ @@ -15719,7 +15737,8 @@ arm_expand_prologue (void) using the EABI unwinder, to prevent faulting instructions from being swapped with a stack adjustment. */ if (crtl->profile || !TARGET_SCHED_PROLOG - || (ARM_EABI_UNWIND_TABLES && cfun->can_throw_non_call_exceptions)) + || (arm_except_unwind_info () == UI_TARGET + && cfun->can_throw_non_call_exceptions)) emit_insn (gen_blockage ()); /* If the link register is being kept alive, with the return address in it, @@ -16312,6 +16331,8 @@ arm_print_operand (FILE *stream, rtx x, int code) { rtx addr; bool postinc = FALSE; + unsigned align, modesize, align_bits; + gcc_assert (GET_CODE (x) == MEM); addr = XEXP (x, 0); if (GET_CODE (addr) == POST_INC) @@ -16319,7 +16340,29 @@ arm_print_operand (FILE *stream, rtx x, int code) postinc = 1; addr = XEXP (addr, 0); } - asm_fprintf (stream, "[%r]", REGNO (addr)); + asm_fprintf (stream, "[%r", REGNO (addr)); + + /* We know the alignment of this access, so we can emit a hint in the + instruction (for some alignments) as an aid to the memory subsystem + of the target. */ + align = MEM_ALIGN (x) >> 3; + modesize = GET_MODE_SIZE (GET_MODE (x)); + + /* Only certain alignment specifiers are supported by the hardware. */ + if (modesize == 16 && (align % 32) == 0) + align_bits = 256; + else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) + align_bits = 128; + else if ((align % 8) == 0) + align_bits = 64; + else + align_bits = 0; + + if (align_bits != 0) + asm_fprintf (stream, ":%d", align_bits); + + asm_fprintf (stream, "]"); + if (postinc) fputs("!", stream); } @@ -19575,7 +19618,7 @@ thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, return; } - if (ARM_EABI_UNWIND_TABLES && push) + if (push && arm_except_unwind_info () == UI_TARGET) { fprintf (f, "\t.save\t{"); for (regno = 0; regno < 15; regno++) @@ -20515,7 +20558,8 @@ thumb1_expand_prologue (void) using the EABI unwinder, to prevent faulting instructions from being swapped with a stack adjustment. */ if (crtl->profile || !TARGET_SCHED_PROLOG - || (ARM_EABI_UNWIND_TABLES && cfun->can_throw_non_call_exceptions)) + || (arm_except_unwind_info () == UI_TARGET + && cfun->can_throw_non_call_exceptions)) emit_insn (gen_blockage ()); cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); @@ -20628,7 +20672,7 @@ thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (crtl->args.pretend_args_size) { /* Output unwind directive for the stack adjustment. */ - if (ARM_EABI_UNWIND_TABLES) + if (arm_except_unwind_info () == UI_TARGET) fprintf (f, "\t.pad #%d\n", crtl->args.pretend_args_size); @@ -20698,7 +20742,7 @@ thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) work_register = thumb_find_work_register (live_regs_mask); - if (ARM_EABI_UNWIND_TABLES) + if (arm_except_unwind_info () == UI_TARGET) asm_fprintf (f, "\t.pad #16\n"); asm_fprintf @@ -22061,7 +22105,7 @@ arm_dwarf_register_span (rtx rtl) return p; } -#ifdef TARGET_UNWIND_INFO +#if ARM_UNWIND_INFO /* Emit unwind directives for a store-multiple instruction or stack pointer push during alignment. These should only ever be generated by the function prologue code, so @@ -22275,7 +22319,7 @@ arm_unwind_emit (FILE * asm_out_file, rtx insn) { rtx pat; - if (!ARM_EABI_UNWIND_TABLES) + if (arm_except_unwind_info () != UI_TARGET) return; if (!(flag_unwind_tables || crtl->uses_eh_lsda) @@ -22344,7 +22388,33 @@ arm_asm_init_sections (void) exception_section = get_unnamed_section (0, output_section_asm_op, "\t.handlerdata"); } -#endif /* TARGET_UNWIND_INFO */ +#endif /* ARM_UNWIND_INFO */ + +/* Implement TARGET_EXCEPT_UNWIND_INFO. */ + +static enum unwind_info_type +arm_except_unwind_info (void) +{ + /* Honor the --enable-sjlj-exceptions configure switch. */ +#ifdef CONFIG_SJLJ_EXCEPTIONS + if (CONFIG_SJLJ_EXCEPTIONS) + return UI_SJLJ; +#endif + + /* If not using ARM EABI unwind tables... */ + if (ARM_UNWIND_INFO) + { + /* For simplicity elsewhere in this file, indicate that all unwind + info is disabled if we're not emitting unwind tables. */ + if (!flag_exceptions && !flag_unwind_tables) + return UI_NONE; + else + return UI_TARGET; + } + + /* ... we use sjlj exceptions for backwards compatibility. */ + return UI_SJLJ; +} /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic @@ -22376,7 +22446,7 @@ arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) void arm_output_fn_unwind (FILE * f, bool prologue) { - if (!ARM_EABI_UNWIND_TABLES) + if (arm_except_unwind_info () != UI_TARGET) return; if (prologue) @@ -23113,4 +23183,43 @@ arm_expand_sync (enum machine_mode mode, } } +static bool +arm_vector_alignment_reachable (const_tree type, bool is_packed) +{ + /* Vectors which aren't in packed structures will not be less aligned than + the natural alignment of their element type, so this is safe. */ + if (TARGET_NEON && !BYTES_BIG_ENDIAN) + return !is_packed; + + return default_builtin_vector_alignment_reachable (type, is_packed); +} + +static bool +arm_builtin_support_vector_misalignment (enum machine_mode mode, + const_tree type, int misalignment, + bool is_packed) +{ + if (TARGET_NEON && !BYTES_BIG_ENDIAN) + { + HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type); + + if (is_packed) + return align == 1; + + /* If the misalignment is unknown, we should be able to handle the access + so long as it is not to a member of a packed data structure. */ + if (misalignment == -1) + return true; + + /* Return true if the misalignment is a multiple of the natural alignment + of the vector's element type. This is probably always going to be + true in practice, since we've already established that this isn't a + packed access. */ + return ((misalignment % align) == 0); + } + + return default_builtin_support_vector_misalignment (mode, type, misalignment, + is_packed); +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 9bd1c69e849..55442f55ad4 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -948,14 +948,11 @@ extern int arm_structure_size_boundary; #define FIRST_HI_REGNUM 8 #define LAST_HI_REGNUM 11 -#ifndef TARGET_UNWIND_INFO -/* We use sjlj exceptions for backwards compatibility. */ -#define MUST_USE_SJLJ_EXCEPTIONS 1 +/* Overridden by config/arm/bpabi.h. */ +#ifndef ARM_UNWIND_INFO +#define ARM_UNWIND_INFO 0 #endif -/* We can generate DWARF2 Unwind info, even though we don't use it. */ -#define DWARF2_UNWIND_INFO 1 - /* Use r0 and r1 to pass exception handling information. */ #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) @@ -992,6 +989,9 @@ extern int arm_structure_size_boundary; ? ARM_HARD_FRAME_POINTER_REGNUM \ : THUMB_HARD_FRAME_POINTER_REGNUM) +#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 +#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 + #define FP_REGNUM HARD_FRAME_POINTER_REGNUM /* Register to use for pushing function arguments. */ @@ -2033,13 +2033,6 @@ typedef struct #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) -#ifdef TARGET_UNWIND_INFO -#define ARM_EABI_UNWIND_TABLES \ - ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) -#else -#define ARM_EABI_UNWIND_TABLES 0 -#endif - /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index c6cdca4f0e3..9a59b47de07 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -26,7 +26,8 @@ #define TARGET_BPABI (TARGET_AAPCS_BASED) /* BPABI targets use EABI frame unwinding tables. */ -#define TARGET_UNWIND_INFO 1 +#undef ARM_UNWIND_INFO +#define ARM_UNWIND_INFO 1 /* Section 4.1 of the AAPCS requires the use of VFP format. */ #undef FPUTYPE_DEFAULT diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 3bb74a2d3ee..cd91573be10 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -141,6 +141,7 @@ (UNSPEC_VUZP2 202) (UNSPEC_VZIP1 203) (UNSPEC_VZIP2 204) + (UNSPEC_MISALIGNED_ACCESS 205) (UNSPEC_VCLE 206) (UNSPEC_VCLT 207)]) @@ -369,6 +370,52 @@ neon_disambiguate_copy (operands, dest, src, 4); }) +(define_expand "movmisalign<mode>" + [(set (match_operand:VDQX 0 "nonimmediate_operand" "") + (unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")] + UNSPEC_MISALIGNED_ACCESS))] + "TARGET_NEON && !BYTES_BIG_ENDIAN" +{ + /* This pattern is not permitted to fail during expansion: if both arguments + are non-registers (e.g. memory := constant, which can be created by the + auto-vectorizer), force operand 1 into a register. */ + if (!s_register_operand (operands[0], <MODE>mode) + && !s_register_operand (operands[1], <MODE>mode)) + operands[1] = force_reg (<MODE>mode, operands[1]); +}) + +(define_insn "*movmisalign<mode>_neon_store" + [(set (match_operand:VDX 0 "memory_operand" "=Um") + (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] + UNSPEC_MISALIGNED_ACCESS))] + "TARGET_NEON && !BYTES_BIG_ENDIAN" + "vst1.<V_sz_elem>\t{%P1}, %A0" + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + +(define_insn "*movmisalign<mode>_neon_load" + [(set (match_operand:VDX 0 "s_register_operand" "=w") + (unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")] + UNSPEC_MISALIGNED_ACCESS))] + "TARGET_NEON && !BYTES_BIG_ENDIAN" + "vld1.<V_sz_elem>\t{%P0}, %A1" + [(set_attr "neon_type" "neon_vld1_1_2_regs")]) + +(define_insn "*movmisalign<mode>_neon_store" + [(set (match_operand:VQX 0 "memory_operand" "=Um") + (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")] + UNSPEC_MISALIGNED_ACCESS))] + "TARGET_NEON && !BYTES_BIG_ENDIAN" + "vst1.<V_sz_elem>\t{%q1}, %A0" + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + +(define_insn "*movmisalign<mode>_neon_load" + [(set (match_operand:VQX 0 "s_register_operand" "=w") + (unspec:VQX [(match_operand:VQX 1 "memory_operand" " Um")] + UNSPEC_MISALIGNED_ACCESS))] + "TARGET_NEON && !BYTES_BIG_ENDIAN" + "vld1.<V_sz_elem>\t{%q0}, %A1" + [(set_attr "neon_type" "neon_vld1_1_2_regs")]) + (define_insn "vec_set<mode>_internal" [(set (match_operand:VD 0 "s_register_operand" "=w") (vec_merge:VD diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index 2c7a8ad0204..e300dd65bb0 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -747,6 +747,9 @@ expand_prologue (void) } } } + + if (flag_stack_usage) + current_function_static_stack_size = cfun->machine->stack_usage; } /* Output summary at end of function prologue. */ diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 30b298d76e1..11cc5cab71b 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -72,10 +72,6 @@ extern unsigned int bfin_workarounds; /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") -/* Run-time compilation parameters selecting different hardware subsets. */ - -extern int target_flags; - /* Predefinition in the preprocessor for this target machine */ #ifndef TARGET_CPU_CPP_BUILTINS #define TARGET_CPU_CPP_BUILTINS() \ diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index 84191c0920b..16acb52c4ed 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -31,8 +31,6 @@ extern bool cris_simple_epilogue (void); extern const char *cris_op_str (rtx); extern void cris_notice_update_cc (rtx, rtx); extern bool cris_reload_address_legitimized (rtx, enum machine_mode, int, int, int); -extern int cris_register_move_cost (enum machine_mode, enum reg_class, - enum reg_class); extern int cris_side_effect_mode_ok (enum rtx_code, rtx *, int, int, int, int, int); extern bool cris_cc0_user_requires_cmp (rtx); diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 52367c2c71d..3163022b661 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -121,6 +121,8 @@ static void cris_asm_output_mi_thunk static void cris_file_start (void); static void cris_init_libfuncs (void); +static int cris_register_move_cost (enum machine_mode, reg_class_t, reg_class_t); +static int cris_memory_move_cost (enum machine_mode, reg_class_t, bool); static bool cris_rtx_costs (rtx, int, int, int *, bool); static int cris_address_cost (rtx, bool); static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, @@ -185,6 +187,10 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_INIT_LIBFUNCS #define TARGET_INIT_LIBFUNCS cris_init_libfuncs +#undef TARGET_REGISTER_MOVE_COST +#define TARGET_REGISTER_MOVE_COST cris_register_move_cost +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST cris_memory_move_cost #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS cris_rtx_costs #undef TARGET_ADDRESS_COST @@ -1378,11 +1384,11 @@ cris_reload_address_legitimized (rtx x, return false; } -/* Worker function for REGISTER_MOVE_COST. */ +/* Worker function for TARGET_REGISTER_MOVE_COST. */ -int +static int cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, - enum reg_class from, enum reg_class to) + reg_class_t from, reg_class_t to) { if (!TARGET_V32) { @@ -1424,6 +1430,23 @@ cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, return 2; } +/* Worker function for TARGET_MEMORY_MOVE_COST. + + This isn't strictly correct for v0..3 in buswidth-8bit mode, but should + suffice. */ + +static int +cris_memory_move_cost (enum machine_mode mode, + reg_class_t rclass ATTRIBUTE_UNUSED, + bool in ATTRIBUTE_UNUSED) +{ + if (mode == QImode + || mode == HImode) + return 4; + else + return 6; +} + /* Worker for cris_notice_update_cc; handles the "normal" cases. FIXME: this code is historical; its functionality should be refactored to look at insn attributes and moved to diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index d302c9f5540..090bcd12084 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -280,9 +280,6 @@ extern int cris_cpu_version; } \ while (0) -/* This needs to be at least 32 bits. */ -extern int target_flags; - /* Previously controlled by target_flags. */ #define TARGET_ELF 1 @@ -1076,14 +1073,6 @@ struct cum_args {int regs;}; /* Node: Costs */ -#define REGISTER_MOVE_COST(MODE, FROM, TO) \ - cris_register_move_cost (MODE, FROM, TO) - -/* This isn't strictly correct for v0..3 in buswidth-8bit mode, but - should suffice. */ -#define MEMORY_MOVE_COST(M, CLASS, IN) \ - (((M) == QImode) ? 4 : ((M) == HImode) ? 4 : 6) - /* Regardless of the presence of delay slots, the default value of 1 for BRANCH_COST is the best in the range (1, 2, 3), tested with gcc-2.7.2 with testcases ipps and gcc, giving smallest and fastest code. */ diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index f0ff9010b93..220f46a8b57 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -1052,8 +1052,6 @@ __enable_execute_stack (void *addr) \ /* For Apple KEXTs, we make the constructors return this to match gcc 2.95. */ #define TARGET_CXX_CDTOR_RETURNS_THIS (darwin_kextabi_p) -extern int flag_mkernel; -extern int flag_apple_kext; #define TARGET_KEXTABI flag_apple_kext #define TARGET_HAS_TARGETCM 1 diff --git a/gcc/config/darwin.opt b/gcc/config/darwin.opt index ba3b27ef500..c878ec24b36 100644 --- a/gcc/config/darwin.opt +++ b/gcc/config/darwin.opt @@ -45,3 +45,6 @@ Generate code for the kernel or loadable kernel extensions iframework Target RejectNegative C ObjC C++ ObjC++ Joined Separate -iframework <dir> Add <dir> to the end of the system framework include path + +undefined +Driver Separate diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 42d0b1d9d0e..401aeecf65b 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -572,7 +572,7 @@ frv_const_unspec_p (rtx x, struct frv_unspec *unspec) if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) && unspec->offset > 0 - && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value) + && unspec->offset < g_switch_value) return true; } } @@ -611,11 +611,6 @@ frv_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - case OPT_mcpu_: if (strcmp (arg, "simple") == 0) frv_cpu_type = FRV_CPU_SIMPLE; @@ -692,9 +687,8 @@ frv_option_override (void) if (!flag_pic) /* -fPIC */ flag_pic = 2; - if (! g_switch_set) /* -G0 */ + if (!global_options_set.x_g_switch_value) /* -G0 */ { - g_switch_set = 1; g_switch_value = 0; } } @@ -786,7 +780,7 @@ frv_option_override (void) } /* Check for small data option */ - if (!g_switch_set) + if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC) g_switch_value = SDATA_DEFAULT_SIZE; /* A C expression which defines the machine-dependent operand @@ -9570,7 +9564,7 @@ frv_in_small_data_p (const_tree decl) } size = int_size_in_bytes (TREE_TYPE (decl)); - if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) + if (size > 0 && size <= g_switch_value) return true; return false; diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 463f6ad1ecc..bf433d9978e 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -2069,7 +2069,7 @@ extern int size_directive_output; #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \ do { \ - if ((SIZE) > 0 && (SIZE) <= g_switch_value) \ + if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ switch_to_section (get_named_section (NULL, ".sbss", 0)); \ else \ switch_to_section (bss_section); \ diff --git a/gcc/config/g.opt b/gcc/config/g.opt index 346a4d1af92..b0e30348d80 100644 --- a/gcc/config/g.opt +++ b/gcc/config/g.opt @@ -24,7 +24,7 @@ ; Please try to keep this file in ASCII collating order. G -Target Joined Separate UInteger +Target Joined Separate UInteger Var(g_switch_value) -G<number> Put global and static data smaller than <number> bytes into a special section (on some targets) ; This comment is to ensure we retain the blank line above. diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 7fbb5d2f56d..bb1a420b1dd 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -73,11 +73,25 @@ along with GCC; see the file COPYING3. If not see won't allow it. */ #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \ do { \ - if (SIZE != 4 && (!TARGET_64BIT || SIZE != 8)) \ - abort (); \ - \ - fputs ("\t.secrel32\t", FILE); \ - assemble_name (FILE, LABEL); \ + switch (SIZE) \ + { \ + case 4: \ + fputs ("\t.secrel32\t", FILE); \ + assemble_name (FILE, LABEL); \ + break; \ + case 8: \ + /* This is a hack. There is no 64-bit section relative \ + relocation. However, the COFF format also does not \ + support 64-bit file offsets; 64-bit applications are \ + limited to 32-bits of code+data in any one module. \ + Fake the 64-bit offset by zero-extending it. */ \ + fputs ("\t.secrel32\t", FILE); \ + assemble_name (FILE, LABEL); \ + fputs ("\n\t.long\t0", FILE); \ + break; \ + default: \ + gcc_unreachable (); \ + } \ } while (0) #endif diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index c03c8515bc3..1846efbe617 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on the ia-32. - Copyright (C) 2008, 2009 + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. This file is part of GCC. @@ -283,7 +283,8 @@ ix86_pragma_target_parse (tree args, tree pop_target) cur_tree = ((pop_target) ? pop_target : target_option_default_node); - cl_target_option_restore (TREE_TARGET_OPTION (cur_tree)); + cl_target_option_restore (&global_options, + TREE_TARGET_OPTION (cur_tree)); } else { @@ -297,8 +298,8 @@ ix86_pragma_target_parse (tree args, tree pop_target) /* Figure out the previous/current isa, arch, tune and the differences. */ prev_opt = TREE_TARGET_OPTION (prev_tree); cur_opt = TREE_TARGET_OPTION (cur_tree); - prev_isa = prev_opt->ix86_isa_flags; - cur_isa = cur_opt->ix86_isa_flags; + prev_isa = prev_opt->x_ix86_isa_flags; + cur_isa = cur_opt->x_ix86_isa_flags; diff_isa = (prev_isa ^ cur_isa); prev_arch = (enum processor_type) prev_opt->arch; prev_tune = (enum processor_type) prev_opt->tune; diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index fd31e9917f5..75562e8be90 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -29,6 +29,7 @@ extern void ix86_setup_frame_addresses (void); extern HOST_WIDE_INT ix86_initial_elimination_offset (int, int); extern void ix86_expand_prologue (void); extern void ix86_expand_epilogue (int); +extern void ix86_expand_split_stack_prologue (void); extern void ix86_output_addr_vec_elt (FILE *, int); extern void ix86_output_addr_diff_elt (FILE *, int, int); @@ -117,7 +118,7 @@ extern bool ix86_expand_int_vcond (rtx[]); extern void ix86_expand_sse_unpack (rtx[], bool, bool); extern void ix86_expand_sse4_unpack (rtx[], bool, bool); extern bool ix86_expand_int_addcc (rtx[]); -extern void ix86_expand_call (rtx, rtx, rtx, rtx, rtx, int); +extern rtx ix86_expand_call (rtx, rtx, rtx, rtx, rtx, int); extern void x86_initialize_trampoline (rtx, rtx, rtx); extern rtx ix86_zero_extend_to_Pmode (rtx); extern void ix86_split_long_move (rtx[]); @@ -139,7 +140,6 @@ extern rtx ix86_libcall_value (enum machine_mode); extern bool ix86_function_arg_regno_p (int); extern void ix86_asm_output_function_label (FILE *, const char *, tree); extern int ix86_function_arg_boundary (enum machine_mode, const_tree); -extern bool ix86_solaris_return_in_memory (const_tree, const_tree); extern rtx ix86_force_to_memory (enum machine_mode, rtx); extern void ix86_free_from_memory (enum machine_mode); extern void ix86_call_abi_override (const_tree); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 627d8d20ea0..7fe654a3586 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1898,7 +1898,6 @@ int x86_prefetch_sse; static int ix86_regparm; /* -mstackrealign option */ -extern int ix86_force_align_arg_pointer; static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer"; @@ -1989,6 +1988,8 @@ static void ix86_add_new_builtins (int); static rtx ix86_expand_vec_perm_builtin (tree); static tree ix86_canonical_va_list_type (tree); static void predict_jump (int); +static unsigned int split_stack_prologue_scratch_regno (void); +static bool i386_asm_output_addr_const_extra (FILE *, rtx); enum ix86_function_specific_strings { @@ -2630,6 +2631,7 @@ ix86_target_string (int isa, int flags, const char *arch, const char *tune, { "-msseregparm", MASK_SSEREGPARM }, { "-mstack-arg-probe", MASK_STACK_PROBE }, { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS }, + { "-mvect8-ret-in-mem", MASK_VECT8_RETURNS }, { "-m8bit-idiv", MASK_USE_8BIT_IDIV }, }; @@ -3649,7 +3651,7 @@ ix86_option_override_internal (bool main_args_p) /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0) can be optimized to ap = __builtin_next_arg (0). */ - if (!TARGET_64BIT) + if (!TARGET_64BIT && !flag_split_stack) targetm.expand_builtin_va_start = NULL; if (TARGET_64BIT) @@ -3800,7 +3802,7 @@ ix86_function_specific_save (struct cl_target_option *ptr) ptr->tune_defaulted = ix86_tune_defaulted; ptr->arch_specified = ix86_arch_specified; ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit; - ptr->target_flags_explicit = target_flags_explicit; + ptr->ix86_target_flags_explicit = target_flags_explicit; /* The fields are char but the variables are not; make sure the values fit in the fields. */ @@ -3829,7 +3831,7 @@ ix86_function_specific_restore (struct cl_target_option *ptr) ix86_tune_defaulted = ptr->tune_defaulted; ix86_arch_specified = ptr->arch_specified; ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit; - target_flags_explicit = ptr->target_flags_explicit; + target_flags_explicit = ptr->ix86_target_flags_explicit; /* Recreate the arch feature tests if the arch changed */ if (old_arch != ix86_arch) @@ -3857,7 +3859,7 @@ ix86_function_specific_print (FILE *file, int indent, struct cl_target_option *ptr) { char *target_string - = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags, + = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags, NULL, NULL, NULL, false); fprintf (file, "%*sarch = %d (%s)\n", @@ -4114,8 +4116,8 @@ ix86_valid_target_attribute_tree (tree args) ix86_option_override_internal, and then save the options away. The string options are are attribute options, and will be undone when we copy the save structure. */ - if (ix86_isa_flags != def->ix86_isa_flags - || target_flags != def->target_flags + if (ix86_isa_flags != def->x_ix86_isa_flags + || target_flags != def->x_target_flags || option_strings[IX86_FUNCTION_SPECIFIC_ARCH] || option_strings[IX86_FUNCTION_SPECIFIC_TUNE] || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH]) @@ -4178,11 +4180,12 @@ ix86_valid_target_attribute_p (tree fndecl, /* If the function changed the optimization levels as well as setting target options, start with the optimizations specified. */ if (func_optimize && func_optimize != old_optimize) - cl_optimization_restore (TREE_OPTIMIZATION (func_optimize)); + cl_optimization_restore (&global_options, + TREE_OPTIMIZATION (func_optimize)); /* The target attributes may also change some optimization flags, so update the optimization options if necessary. */ - cl_target_option_save (&cur_target); + cl_target_option_save (&cur_target, &global_options); new_target = ix86_valid_target_attribute_tree (args); new_optimize = build_optimization_node (); @@ -4197,10 +4200,11 @@ ix86_valid_target_attribute_p (tree fndecl, DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize; } - cl_target_option_restore (&cur_target); + cl_target_option_restore (&global_options, &cur_target); if (old_optimize != new_optimize) - cl_optimization_restore (TREE_OPTIMIZATION (old_optimize)); + cl_optimization_restore (&global_options, + TREE_OPTIMIZATION (old_optimize)); return ret; } @@ -4232,12 +4236,12 @@ ix86_can_inline_p (tree caller, tree callee) /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function can inline a SSE2 function but a SSE2 function can't inline a SSE4 function. */ - if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags) - != callee_opts->ix86_isa_flags) + if ((caller_opts->x_ix86_isa_flags & callee_opts->x_ix86_isa_flags) + != callee_opts->x_ix86_isa_flags) ret = false; /* See if we have the same non-isa options. */ - else if (caller_opts->target_flags != callee_opts->target_flags) + else if (caller_opts->x_target_flags != callee_opts->x_target_flags) ret = false; /* See if arch, tune, etc. are the same. */ @@ -4289,7 +4293,8 @@ ix86_set_current_function (tree fndecl) else if (new_tree) { - cl_target_option_restore (TREE_TARGET_OPTION (new_tree)); + cl_target_option_restore (&global_options, + TREE_TARGET_OPTION (new_tree)); target_reinit (); } @@ -4298,7 +4303,7 @@ ix86_set_current_function (tree fndecl) struct cl_target_option *def = TREE_TARGET_OPTION (target_option_current_node); - cl_target_option_restore (def); + cl_target_option_restore (&global_options, def); target_reinit (); } } @@ -4890,6 +4895,10 @@ ix86_function_regparm (const_tree type, const_tree decl) if (local_regparm == 3 && DECL_STATIC_CHAIN (decl)) local_regparm = 2; + /* In 32-bit mode save a register for the split stack. */ + if (!TARGET_64BIT && local_regparm == 3 && flag_split_stack) + local_regparm = 2; + /* Each fixed register usage increases register pressure, so less registers should be used for argument passing. This functionality can be overriden by an explicit @@ -6843,9 +6852,9 @@ return_in_memory_32 (const_tree type, enum machine_mode mode) return false; /* MMX/3dNow values are returned in MM0, - except when it doesn't exits. */ + except when it doesn't exits or the ABI prescribes otherwise. */ if (size == 8) - return !TARGET_MMX; + return !TARGET_MMX || TARGET_VECT8_RETURNS; /* SSE values are returned in XMM0, except when it doesn't exist. */ if (size == 16) @@ -6909,43 +6918,6 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #endif } -/* Return false iff TYPE is returned in memory. This version is used - on Solaris 2. It is similar to the generic ix86_return_in_memory, - but differs notably in that when MMX is available, 8-byte vectors - are returned in memory, rather than in MMX registers. */ - -bool -ix86_solaris_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -{ - int size; - enum machine_mode mode = type_natural_mode (type, NULL); - - if (TARGET_64BIT) - return return_in_memory_64 (type, mode); - - if (mode == BLKmode) - return 1; - - size = int_size_in_bytes (type); - - if (VECTOR_MODE_P (mode)) - { - /* Return in memory only if MMX registers *are* available. This - seems backwards, but it is consistent with the existing - Solaris x86 ABI. */ - if (size == 8) - return TARGET_MMX; - if (size == 16) - return !TARGET_SSE; - } - else if (mode == TImode) - return !TARGET_SSE; - else if (mode == XFmode) - return 0; - - return size > 12; -} - /* When returning SSE vector types, we have a choice of either (1) being abi incompatible with a -march switch, or (2) generating an error. @@ -7248,10 +7220,56 @@ ix86_va_start (tree valist, rtx nextarg) tree gpr, fpr, ovf, sav, t; tree type; + rtx ovf_rtx; + + if (flag_split_stack + && cfun->machine->split_stack_varargs_pointer == NULL_RTX) + { + unsigned int scratch_regno; + + /* When we are splitting the stack, we can't refer to the stack + arguments using internal_arg_pointer, because they may be on + the old stack. The split stack prologue will arrange to + leave a pointer to the old stack arguments in a scratch + register, which we here copy to a pseudo-register. The split + stack prologue can't set the pseudo-register directly because + it (the prologue) runs before any registers have been saved. */ + + scratch_regno = split_stack_prologue_scratch_regno (); + if (scratch_regno != INVALID_REGNUM) + { + rtx reg, seq; + + reg = gen_reg_rtx (Pmode); + cfun->machine->split_stack_varargs_pointer = reg; + + start_sequence (); + emit_move_insn (reg, gen_rtx_REG (Pmode, scratch_regno)); + seq = get_insns (); + end_sequence (); + + push_topmost_sequence (); + emit_insn_after (seq, entry_of_function ()); + pop_topmost_sequence (); + } + } + /* Only 64bit target needs something special. */ if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist))) { - std_expand_builtin_va_start (valist, nextarg); + if (cfun->machine->split_stack_varargs_pointer == NULL_RTX) + std_expand_builtin_va_start (valist, nextarg); + else + { + rtx va_r, next; + + va_r = expand_expr (valist, NULL_RTX, VOIDmode, EXPAND_WRITE); + next = expand_binop (ptr_mode, add_optab, + cfun->machine->split_stack_varargs_pointer, + crtl->args.arg_offset_rtx, + NULL_RTX, 0, OPTAB_LIB_WIDEN); + convert_move (va_r, next, 0); + } return; } @@ -7297,7 +7315,11 @@ ix86_va_start (tree valist, rtx nextarg) /* Find the overflow area. */ type = TREE_TYPE (ovf); - t = make_tree (type, crtl->args.internal_arg_pointer); + if (cfun->machine->split_stack_varargs_pointer == NULL_RTX) + ovf_rtx = crtl->args.internal_arg_pointer; + else + ovf_rtx = cfun->machine->split_stack_varargs_pointer; + t = make_tree (type, ovf_rtx); if (words != 0) t = build2 (POINTER_PLUS_EXPR, type, t, size_int (words * UNITS_PER_WORD)); @@ -7502,6 +7524,8 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, tree dest_addr, dest; int cur_size = GET_MODE_SIZE (mode); + gcc_assert (prev_size <= INTVAL (XEXP (slot, 1))); + prev_size = INTVAL (XEXP (slot, 1)); if (prev_size + cur_size > size) { cur_size = size - prev_size; @@ -7534,7 +7558,7 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, dest_addr = fold_convert (daddr_type, addr); dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr, - size_int (INTVAL (XEXP (slot, 1)))); + size_int (prev_size)); if (cur_size == GET_MODE_SIZE (mode)) { src = build_va_arg_indirect_ref (src_addr); @@ -8042,6 +8066,9 @@ ix86_code_end (void) set_cfun (NULL); current_function_decl = NULL; } + + if (flag_split_stack) + file_end_indicate_split_stack (); } /* Emit code for the SET_GOT patterns. */ @@ -8344,6 +8371,37 @@ ix86_builtin_setjmp_frame_value (void) return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx; } +/* On the x86 -fsplit-stack and -fstack-protector both use the same + field in the TCB, so they can not be used together. */ + +static bool +ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED) +{ + bool ret = true; + +#ifndef TARGET_THREAD_SPLIT_STACK_OFFSET + if (report) + error ("%<-fsplit-stack%> currently only supported on GNU/Linux"); + ret = false; +#else + if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) + { + if (report) + error ("%<-fsplit-stack%> requires " + "assembler support for CFI directives"); + ret = false; + } +#endif + + return ret; +} + +/* When using -fsplit-stack, the allocation routines set a field in + the TCB to the bottom of the stack plus this much space, measured + in bytes. */ + +#define SPLIT_STACK_AVAILABLE 256 + /* Fill structure ix86_frame about frame of currently computed function. */ static void @@ -10334,6 +10392,277 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, #endif } + +/* Return a scratch register to use in the split stack prologue. The + split stack prologue is used for -fsplit-stack. It is the first + instructions in the function, even before the regular prologue. + The scratch register can be any caller-saved register which is not + used for parameters or for the static chain. */ + +static unsigned int +split_stack_prologue_scratch_regno (void) +{ + if (TARGET_64BIT) + return R11_REG; + else + { + bool is_fastcall; + int regparm; + + is_fastcall = (lookup_attribute ("fastcall", + TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl))) + != NULL); + regparm = ix86_function_regparm (TREE_TYPE (cfun->decl), cfun->decl); + + if (is_fastcall) + { + if (DECL_STATIC_CHAIN (cfun->decl)) + { + sorry ("-fsplit-stack does not support fastcall with " + "nested function"); + return INVALID_REGNUM; + } + return AX_REG; + } + else if (regparm < 3) + { + if (!DECL_STATIC_CHAIN (cfun->decl)) + return CX_REG; + else + { + if (regparm >= 2) + { + sorry ("-fsplit-stack does not support 2 register " + " parameters for a nested function"); + return INVALID_REGNUM; + } + return DX_REG; + } + } + else + { + /* FIXME: We could make this work by pushing a register + around the addition and comparison. */ + sorry ("-fsplit-stack does not support 3 register parameters"); + return INVALID_REGNUM; + } + } +} + +/* A SYMBOL_REF for the function which allocates new stackspace for + -fsplit-stack. */ + +static GTY(()) rtx split_stack_fn; + +/* Handle -fsplit-stack. These are the first instructions in the + function, even before the regular prologue. */ + +void +ix86_expand_split_stack_prologue (void) +{ + struct ix86_frame frame; + HOST_WIDE_INT allocate; + int args_size; + rtx label, limit, current, jump_insn, allocate_rtx, call_insn, call_fusage; + rtx scratch_reg = NULL_RTX; + rtx varargs_label = NULL_RTX; + + gcc_assert (flag_split_stack && reload_completed); + + ix86_finalize_stack_realign_flags (); + ix86_compute_frame_layout (&frame); + allocate = frame.stack_pointer_offset - INCOMING_FRAME_SP_OFFSET; + + /* This is the label we will branch to if we have enough stack + space. We expect the basic block reordering pass to reverse this + branch if optimizing, so that we branch in the unlikely case. */ + label = gen_label_rtx (); + + /* We need to compare the stack pointer minus the frame size with + the stack boundary in the TCB. The stack boundary always gives + us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we + can compare directly. Otherwise we need to do an addition. */ + + limit = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), + UNSPEC_STACK_CHECK); + limit = gen_rtx_CONST (Pmode, limit); + limit = gen_rtx_MEM (Pmode, limit); + if (allocate < SPLIT_STACK_AVAILABLE) + current = stack_pointer_rtx; + else + { + unsigned int scratch_regno; + rtx offset; + + /* We need a scratch register to hold the stack pointer minus + the required frame size. Since this is the very start of the + function, the scratch register can be any caller-saved + register which is not used for parameters. */ + offset = GEN_INT (- allocate); + scratch_regno = split_stack_prologue_scratch_regno (); + if (scratch_regno == INVALID_REGNUM) + return; + scratch_reg = gen_rtx_REG (Pmode, scratch_regno); + if (!TARGET_64BIT || x86_64_immediate_operand (offset, Pmode)) + { + /* We don't use ix86_gen_add3 in this case because it will + want to split to lea, but when not optimizing the insn + will not be split after this point. */ + emit_insn (gen_rtx_SET (VOIDmode, scratch_reg, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + offset))); + } + else + { + emit_move_insn (scratch_reg, offset); + emit_insn (gen_adddi3 (scratch_reg, scratch_reg, + stack_pointer_rtx)); + } + current = scratch_reg; + } + + ix86_expand_branch (GEU, current, limit, label); + jump_insn = get_last_insn (); + JUMP_LABEL (jump_insn) = label; + + /* Mark the jump as very likely to be taken. */ + add_reg_note (jump_insn, REG_BR_PROB, + GEN_INT (REG_BR_PROB_BASE - REG_BR_PROB_BASE / 100)); + + /* Get more stack space. We pass in the desired stack space and the + size of the arguments to copy to the new stack. In 32-bit mode + we push the parameters; __morestack will return on a new stack + anyhow. In 64-bit mode we pass the parameters in r10 and + r11. */ + allocate_rtx = GEN_INT (allocate); + args_size = crtl->args.size >= 0 ? crtl->args.size : 0; + call_fusage = NULL_RTX; + if (TARGET_64BIT) + { + rtx reg; + + reg = gen_rtx_REG (Pmode, R10_REG); + + /* If this function uses a static chain, it will be in %r10. + Preserve it across the call to __morestack. */ + if (DECL_STATIC_CHAIN (cfun->decl)) + { + rtx rax; + + rax = gen_rtx_REG (Pmode, AX_REG); + emit_move_insn (rax, reg); + use_reg (&call_fusage, rax); + } + + emit_move_insn (reg, allocate_rtx); + use_reg (&call_fusage, reg); + reg = gen_rtx_REG (Pmode, R11_REG); + emit_move_insn (reg, GEN_INT (args_size)); + use_reg (&call_fusage, reg); + } + else + { + emit_insn (gen_push (GEN_INT (args_size))); + emit_insn (gen_push (allocate_rtx)); + } + if (split_stack_fn == NULL_RTX) + split_stack_fn = gen_rtx_SYMBOL_REF (Pmode, "__morestack"); + call_insn = ix86_expand_call (NULL_RTX, gen_rtx_MEM (QImode, split_stack_fn), + GEN_INT (UNITS_PER_WORD), constm1_rtx, + NULL_RTX, 0); + add_function_usage_to (call_insn, call_fusage); + + /* In order to make call/return prediction work right, we now need + to execute a return instruction. See + libgcc/config/i386/morestack.S for the details on how this works. + + For flow purposes gcc must not see this as a return + instruction--we need control flow to continue at the subsequent + label. Therefore, we use an unspec. */ + gcc_assert (crtl->args.pops_args < 65536); + emit_insn (gen_split_stack_return (GEN_INT (crtl->args.pops_args))); + + /* If we are in 64-bit mode and this function uses a static chain, + we saved %r10 in %rax before calling _morestack. */ + if (TARGET_64BIT && DECL_STATIC_CHAIN (cfun->decl)) + emit_move_insn (gen_rtx_REG (Pmode, R10_REG), + gen_rtx_REG (Pmode, AX_REG)); + + /* If this function calls va_start, we need to store a pointer to + the arguments on the old stack, because they may not have been + all copied to the new stack. At this point the old stack can be + found at the frame pointer value used by __morestack, because + __morestack has set that up before calling back to us. Here we + store that pointer in a scratch register, and in + ix86_expand_prologue we store the scratch register in a stack + slot. */ + if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) + { + unsigned int scratch_regno; + rtx frame_reg; + int words; + + scratch_regno = split_stack_prologue_scratch_regno (); + scratch_reg = gen_rtx_REG (Pmode, scratch_regno); + frame_reg = gen_rtx_REG (Pmode, BP_REG); + + /* 64-bit: + fp -> old fp value + return address within this function + return address of caller of this function + stack arguments + So we add three words to get to the stack arguments. + + 32-bit: + fp -> old fp value + return address within this function + first argument to __morestack + second argument to __morestack + return address of caller of this function + stack arguments + So we add five words to get to the stack arguments. + */ + words = TARGET_64BIT ? 3 : 5; + emit_insn (gen_rtx_SET (VOIDmode, scratch_reg, + gen_rtx_PLUS (Pmode, frame_reg, + GEN_INT (words * UNITS_PER_WORD)))); + + varargs_label = gen_label_rtx (); + emit_jump_insn (gen_jump (varargs_label)); + JUMP_LABEL (get_last_insn ()) = varargs_label; + + emit_barrier (); + } + + emit_label (label); + LABEL_NUSES (label) = 1; + + /* If this function calls va_start, we now have to set the scratch + register for the case where we do not call __morestack. In this + case we need to set it based on the stack pointer. */ + if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) + { + emit_insn (gen_rtx_SET (VOIDmode, scratch_reg, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + GEN_INT (UNITS_PER_WORD)))); + + emit_label (varargs_label); + LABEL_NUSES (varargs_label) = 1; + } +} + +/* We may have to tell the dataflow pass that the split stack prologue + is initializing a scratch register. */ + +static void +ix86_live_on_entry (bitmap regs) +{ + if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) + { + gcc_assert (flag_split_stack); + bitmap_set_bit (regs, split_stack_prologue_scratch_regno ()); + } +} /* Extract the parts of an RTL expression that is a valid memory address for an instruction. Return 0 if the structure of the address is @@ -10979,6 +11308,10 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, case UNSPEC_DTPOFF: break; + case UNSPEC_STACK_CHECK: + gcc_assert (flag_split_stack); + break; + default: /* Invalid address unspec. */ return false; @@ -11870,6 +12203,13 @@ output_pic_addr_const (FILE *file, rtx x, int code) break; case UNSPEC: + if (XINT (x, 1) == UNSPEC_STACK_CHECK) + { + bool f = i386_asm_output_addr_const_extra (file, x); + gcc_assert (f); + break; + } + gcc_assert (XVECLEN (x, 0) == 1); output_pic_addr_const (file, XVECEXP (x, 0, 0), code); switch (XINT (x, 1)) @@ -13273,6 +13613,22 @@ i386_asm_output_addr_const_extra (FILE *file, rtx x) break; #endif + case UNSPEC_STACK_CHECK: + { + int offset; + + gcc_assert (flag_split_stack); + +#ifdef TARGET_THREAD_SPLIT_STACK_OFFSET + offset = TARGET_THREAD_SPLIT_STACK_OFFSET; +#else + gcc_unreachable (); +#endif + + fprintf (file, "%s:%d", TARGET_64BIT ? "%fs" : "%gs", offset); + } + break; + default: return false; } @@ -20359,7 +20715,7 @@ construct_plt_address (rtx symbol) return tmp; } -void +rtx ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx callarg2, rtx pop, int sibcall) @@ -20450,6 +20806,8 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, call = emit_call_insn (call); if (use) CALL_INSN_FUNCTION_USAGE (call) = use; + + return call; } @@ -32856,6 +33214,9 @@ ix86_units_per_simd_word (enum machine_mode mode) #undef TARGET_STACK_PROTECT_FAIL #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail +#undef TARGET_SUPPORTS_SPLIT_STACK +#define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack + #undef TARGET_FUNCTION_VALUE #define TARGET_FUNCTION_VALUE ix86_function_value @@ -32914,6 +33275,9 @@ ix86_units_per_simd_word (enum machine_mode mode) #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE ix86_can_eliminate +#undef TARGET_EXTRA_LIVE_ON_ENTRY +#define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry + #undef TARGET_ASM_CODE_END #define TARGET_ASM_CODE_END ix86_code_end diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index b3439bc9f0c..62f35cae2ec 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -447,8 +447,6 @@ extern int x86_prefetch_sse; #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) #define TARGET_SUN_TLS 0 -extern int ix86_isa_flags; - #ifndef TARGET_64BIT_DEFAULT #define TARGET_64BIT_DEFAULT 0 #endif @@ -2277,6 +2275,13 @@ struct GTY(()) machine_function { has been computed for. */ int use_fast_prologue_epilogue_nregs; + /* For -fsplit-stack support: A stack local which holds a pointer to + the stack arguments for a function with a variable number of + arguments. This is set at the start of the function and is used + to initialize the overflow_arg_area field of the va_list + structure. */ + rtx split_stack_varargs_pointer; + /* This value is used for amd64 targets and specifies the current abi to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ ENUM_BITFIELD(calling_abi) call_abi : 8; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c541c1485c4..fc190e9629f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -85,6 +85,7 @@ UNSPEC_SET_RIP UNSPEC_SET_GOT_OFFSET UNSPEC_MEMORY_BLOCKAGE + UNSPEC_STACK_CHECK ;; TLS support UNSPEC_TP @@ -461,7 +462,7 @@ ;; Set when REX opcode prefix is used. (define_attr "prefix_rex" "" - (cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0)) + (cond [(eq (symbol_ref "TARGET_64BIT") (const_int 0)) (const_int 0) (and (eq_attr "mode" "DI") (and (eq_attr "type" "!push,pop,call,callv,leave,ibr") @@ -712,9 +713,6 @@ ;; Mapping of unsigned max and min (define_code_iterator umaxmin [umax umin]) -;; Mapping of signed/unsigned max and min -(define_code_iterator maxmin [smax smin umax umin]) - ;; Base name for integer and FP insn mnemonic (define_code_attr maxmin_int [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")]) @@ -9153,6 +9151,33 @@ DONE; }) +;; Avoid useless masking of count operand. +(define_insn_and_split "*ashl<mode>3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (ashift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) + == GET_MODE_BITSIZE (<MODE>mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (ashift:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} + [(set_attr "type" "ishift") + (set_attr "mode" "<MODE>")]) + (define_insn "*ashl<mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,l") @@ -9692,6 +9717,33 @@ "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") +;; Avoid useless masking of count operand. +(define_insn_and_split "*<shiftrt_insn><mode>3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (any_shiftrt:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) + == GET_MODE_BITSIZE (<MODE>mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} + [(set_attr "type" "ishift") + (set_attr "mode" "<MODE>")]) + (define_insn_and_split "*<shiftrt_insn><mode>3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=r") (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0") @@ -10044,6 +10096,33 @@ "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") +;; Avoid useless masking of count operand. +(define_insn_and_split "*<rotate_insn><mode>3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (any_rotate:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) + == GET_MODE_BITSIZE (<MODE>mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (any_rotate:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} + [(set_attr "type" "rotate") + (set_attr "mode" "<MODE>")]) + ;; Implement rotation using two double-precision ;; shift instructions and a scratch register. @@ -11612,6 +11691,64 @@ "leave" [(set_attr "type" "leave")]) +;; Handle -fsplit-stack. + +(define_expand "split_stack_prologue" + [(const_int 0)] + "" +{ + ix86_expand_split_stack_prologue (); + DONE; +}) + +;; In order to support the call/return predictor, we use a return +;; instruction which the middle-end doesn't see. +(define_insn "split_stack_return" + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")] + UNSPEC_STACK_CHECK)] + "" +{ + if (operands[0] == const0_rtx) + return "ret"; + else + return "ret\t%0"; +} + [(set_attr "atom_unit" "jeu") + (set_attr "modrm" "0") + (set (attr "length") + (if_then_else (match_operand:SI 0 "const0_operand" "") + (const_int 1) + (const_int 3))) + (set (attr "length_immediate") + (if_then_else (match_operand:SI 0 "const0_operand" "") + (const_int 0) + (const_int 2)))]) + +;; If there are operand 0 bytes available on the stack, jump to +;; operand 1. + +(define_expand "split_stack_space_check" + [(set (pc) (if_then_else + (ltu (minus (reg SP_REG) + (match_operand 0 "register_operand" "")) + (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) + (label_ref (match_operand 1 "" "")) + (pc)))] + "" +{ + rtx reg, size, limit; + + reg = gen_reg_rtx (Pmode); + size = force_reg (Pmode, operands[0]); + emit_insn (gen_sub3_insn (reg, stack_pointer_rtx, size)); + limit = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), + UNSPEC_STACK_CHECK); + limit = gen_rtx_MEM (Pmode, gen_rtx_CONST (Pmode, limit)); + ix86_expand_branch (GEU, reg, limit, operands[1]); + + DONE; +}) + ;; Bit manipulation instructions. (define_expand "ffs<mode>2" diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 38a53f616c7..9c1fe1fd729 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -50,7 +50,7 @@ int ix86_isa_flags_explicit ;; which flags were passed by the user TargetSave -int target_flags_explicit +int ix86_target_flags_explicit ;; whether -mtune was not specified TargetSave @@ -244,6 +244,10 @@ mveclibabi= Target RejectNegative Joined Var(ix86_veclibabi_string) Vector library ABI to use +mvect8-ret-in-mem +Target Report Mask(VECT8_RETURNS) Save +Return 8-byte vectors in memory + mrecip Target Report Mask(RECIP) Save Generate reciprocals instead of divss and sqrtss. @@ -266,111 +270,111 @@ is selected. ;; ISA support m32 -Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save +Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save Generate 32bit i386 code m64 -Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save +Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save Generate 64bit x86-64 code mmmx -Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save Support MMX built-in functions m3dnow -Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save Support 3DNow! built-in functions m3dnowa -Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save +Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save Support Athlon 3Dnow! built-in functions msse -Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save Support MMX and SSE built-in functions and code generation msse2 -Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save Support MMX, SSE and SSE2 built-in functions and code generation msse3 -Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation mssse3 -Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation msse4.1 -Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation msse4.2 -Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation msse4 -Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save +Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation mno-sse4 -Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save +Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save Do not support SSE4.1 and SSE4.2 built-in functions and code generation mavx -Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists +Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation mfma -Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists +Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation msse4a -Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation mfma4 -Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save Support FMA4 built-in functions and code generation mxop -Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save Support XOP built-in functions and code generation mlwp -Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save Support LWP built-in functions and code generation mabm -Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save Support code generation of Advanced Bit Manipulation (ABM) instructions. mpopcnt -Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save Support code generation of popcnt instruction. mcx16 -Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save Support code generation of cmpxchg16b instruction. msahf -Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save Support code generation of sahf instruction in 64bit x86-64 code. mmovbe -Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save Support code generation of movbe instruction. mcrc32 -Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save Support code generation of crc32 instruction. maes -Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save Support AES built-in functions and code generation mpclmul -Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save Support PCLMUL built-in functions and code generation msse2avx @@ -378,15 +382,15 @@ Target Report Var(ix86_sse2avx) Encode SSE instructions with VEX prefix mfsgsbase -Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save Support FSGSBASE built-in functions and code generation mrdrnd -Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save Support RDRND built-in functions and code generation mf16c -Target Report Mask(ISA_F16C) Var(ix86_isa_flags) VarExists Save +Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save Support F16C built-in functions and code generation mfentry diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index 81dfd1e2509..7564c70b6d2 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -218,4 +218,8 @@ along with GCC; see the file COPYING3. If not see #ifdef TARGET_LIBC_PROVIDES_SSP /* i386 glibc provides __stack_chk_guard in %gs:0x14. */ #define TARGET_THREAD_SSP_OFFSET 0x14 + +/* We steal the last transactional memory word. */ +#define TARGET_CAN_SPLIT_STACK +#define TARGET_THREAD_SPLIT_STACK_OFFSET 0x30 #endif diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h index fda73d21107..4a3e366fb4e 100644 --- a/gcc/config/i386/linux64.h +++ b/gcc/config/i386/linux64.h @@ -123,4 +123,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* i386 glibc provides __stack_chk_guard in %gs:0x14, x86_64 glibc provides it in %fs:0x28. */ #define TARGET_THREAD_SSP_OFFSET (TARGET_64BIT ? 0x28 : 0x14) + +/* We steal the last transactional memory word. */ +#define TARGET_CAN_SPLIT_STACK +#define TARGET_THREAD_SPLIT_STACK_OFFSET (TARGET_64BIT ? 0x70 : 0x30) #endif diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index 0b0de2d143c..4f8a63a3500 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -223,7 +223,7 @@ __enable_execute_stack (void *addr) \ /* For 64-bit Windows we can't use DW2 unwind info. Also for multilib builds we can't use it, too. */ -#if !TARGET_64BIT && !defined (TARGET_BI_ARCH) +#if !TARGET_64BIT_DEFAULT && !defined (TARGET_BI_ARCH) #define MD_UNWIND_SUPPORT "config/i386/w32-unwind.h" #endif diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 56a92bd5f3e..60a310b91e8 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -499,19 +499,6 @@ return true; }) -;; True for any non-virtual or eliminable register. Used in places where -;; instantiation of such a register may cause the pattern to not be recognized. -(define_predicate "register_no_elim_operand" - (match_operand 0 "register_operand") -{ - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - return !(op == arg_pointer_rtx - || op == frame_pointer_rtx - || IN_RANGE (REGNO (op), - FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER)); -}) - ;; P6 processors will jump to the address after the decrement when %esp ;; is used as a call operand, so they will execute return address as a code. ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17. @@ -528,6 +515,19 @@ return register_no_elim_operand (op, mode); }) +;; True for any non-virtual or eliminable register. Used in places where +;; instantiation of such a register may cause the pattern to not be recognized. +(define_predicate "register_no_elim_operand" + (match_operand 0 "register_operand") +{ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + return !(op == arg_pointer_rtx + || op == frame_pointer_rtx + || IN_RANGE (REGNO (op), + FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER)); +}) + ;; Similarly, but include the stack pointer. This is used to prevent esp ;; from being used as an index reg. (define_predicate "index_register_operand" diff --git a/gcc/config/i386/sol2-10.h b/gcc/config/i386/sol2-10.h index c7fdec9a1a3..d4f6450be01 100644 --- a/gcc/config/i386/sol2-10.h +++ b/gcc/config/i386/sol2-10.h @@ -89,9 +89,12 @@ along with GCC; see the file COPYING3. If not see } \ while (0) +/* Override i386/sol2.h version: return 8-byte vectors in MMX registers if + possible, matching Sun Studio 12 Update 1+ compilers and other x86 + targets. */ #undef TARGET_SUBTARGET_DEFAULT -#define TARGET_SUBTARGET_DEFAULT (MASK_80387 | MASK_IEEE_FP \ - | MASK_FLOAT_RETURNS) +#define TARGET_SUBTARGET_DEFAULT \ + (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS) #define SUBTARGET_OPTIMIZATION_OPTIONS \ do \ diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index 57f75ea5092..b86308fe2fc 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -140,9 +140,15 @@ along with GCC; see the file COPYING3. If not see /* Register the Solaris-specific #pragma directives. */ #define REGISTER_SUBTARGET_PRAGMAS() solaris_register_pragmas () +/* Undo i386/sysv4.h version. */ #undef SUBTARGET_RETURN_IN_MEMORY -#define SUBTARGET_RETURN_IN_MEMORY(TYPE, FNTYPE) \ - ix86_solaris_return_in_memory (TYPE, FNTYPE) + +/* Augment i386/unix.h version to return 8-byte vectors in memory, matching + Sun Studio compilers until version 12, the only ones supported on + Solaris 8 and 9. */ +#undef TARGET_SUBTARGET_DEFAULT +#define TARGET_SUBTARGET_DEFAULT \ + (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_VECT8_RETURNS) /* Output a simple call for .init/.fini. */ #define ASM_OUTPUT_CALL(FILE, FN) \ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0a116aa8370..1784da9d05c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6031,18 +6031,16 @@ (define_insn "*avx_<code><mode>3" [(set (match_operand:SSEMODE124 0 "register_operand" "=x") - (maxmin:SSEMODE124 + (umaxmin:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x") (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set (attr "prefix_extra") - (if_then_else - (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)") - (const_int 0)) - (const_string "1") - (const_string "0"))) + (if_then_else (match_operand:V16QI 0 "" "") + (const_string "0") + (const_string "1"))) (set_attr "prefix" "vex") (set_attr "mode" "TI")]) @@ -6065,6 +6063,21 @@ (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) +(define_insn "*avx_<code><mode>3" + [(set (match_operand:SSEMODE124 0 "register_operand" "=x") + (smaxmin:SSEMODE124 + (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x") + (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))] + "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sseiadd") + (set (attr "prefix_extra") + (if_then_else (match_operand:V8HI 0 "" "") + (const_string "0") + (const_string "1"))) + (set_attr "prefix" "vex") + (set_attr "mode" "TI")]) + (define_expand "<code>v8hi3" [(set (match_operand:V8HI 0 "register_operand" "") (smaxmin:V8HI @@ -6917,7 +6930,7 @@ } [(set_attr "type" "sselog") (set (attr "prefix_extra") - (if_then_else (match_operand:V8HI 0 "register_operand" "") + (if_then_else (match_operand:V8HI 0 "" "") (const_string "0") (const_string "1"))) (set_attr "length_immediate" "1") diff --git a/gcc/config/i386/vx-common.h b/gcc/config/i386/vx-common.h index f4547f08848..e63b91eb72d 100644 --- a/gcc/config/i386/vx-common.h +++ b/gcc/config/i386/vx-common.h @@ -20,10 +20,11 @@ along with GCC; see the file COPYING3. If not see #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) -/* VxWorks uses the same ABI as Solaris 2. */ +/* VxWorks uses the same ABI as Solaris 2, so use i386/sol2.h version. */ -#define SUBTARGET_RETURN_IN_MEMORY(TYPE, FNTYPE) \ - ix86_solaris_return_in_memory (TYPE, FNTYPE) +#undef TARGET_SUBTARGET_DEFAULT +#define TARGET_SUBTARGET_DEFAULT \ + (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_VECT8_RETURNS) /* Provide our target specific DBX_REGISTER_NUMBER, as advertised by the common svr4.h. VxWorks relies on the SVR4 numbering. */ diff --git a/gcc/config/ia64/hpux.h b/gcc/config/ia64/hpux.h index 4a3a40f4bed..47bbd1e463b 100644 --- a/gcc/config/ia64/hpux.h +++ b/gcc/config/ia64/hpux.h @@ -215,3 +215,14 @@ do { \ #undef HANDLE_PRAGMA_PACK_PUSH_POP #define HANDLE_PRAGMA_PACK_PUSH_POP + +/* The HP-UX linker has a bug that causes calls from functions in + .text.unlikely to functions in .text to cause a segfault. Until + it is fixed, prevent code from being put into .text.unlikely or + .text.hot. */ + +#undef UNLIKELY_EXECUTED_TEXT_SECTION_NAME +#define UNLIKELY_EXECUTED_TEXT_SECTION_NAME ".text" + +#undef HOT_TEXT_SECTION_NAME +#define HOT_TEXT_SECTION_NAME ".text" diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 61be5a45bbe..d2728606861 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -251,6 +251,9 @@ static void ia64_asm_unwind_emit (FILE *, rtx); static void ia64_asm_emit_except_personality (rtx); static void ia64_asm_init_sections (void); +static enum unwind_info_type ia64_debug_unwind_info (void); +static enum unwind_info_type ia64_except_unwind_info (void); + static struct bundle_state *get_free_bundle_state (void); static void free_bundle_state (struct bundle_state *); static void initiate_bundle_states (void); @@ -319,6 +322,7 @@ static void ia64_trampoline_init (rtx, tree, rtx); static void ia64_override_options_after_change (void); static void ia64_dwarf_handle_frame_unspec (const char *, rtx, int); +static tree ia64_builtin_decl (unsigned, bool); /* Table of valid machine attributes. */ static const struct attribute_spec ia64_attribute_table[] = @@ -344,6 +348,9 @@ static const struct attribute_spec ia64_attribute_table[] = #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN ia64_expand_builtin +#undef TARGET_BUILTIN_DECL +#define TARGET_BUILTIN_DECL ia64_builtin_decl + #undef TARGET_ASM_BYTE_OP #define TARGET_ASM_BYTE_OP "\tdata1\t" #undef TARGET_ASM_ALIGNED_HI_OP @@ -537,6 +544,11 @@ static const struct attribute_spec ia64_attribute_table[] = #undef TARGET_ASM_INIT_SECTIONS #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections +#undef TARGET_DEBUG_UNWIND_INFO +#define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info +#undef TARGET_EXCEPT_UNWIND_INFO +#define TARGET_EXCEPT_UNWIND_INFO ia64_except_unwind_info + #undef TARGET_SCALAR_MODE_SUPPORTED_P #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p #undef TARGET_VECTOR_MODE_SUPPORTED_P @@ -3903,7 +3915,7 @@ ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) current_frame_info.n_output_regs, current_frame_info.n_rotate_regs); - if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS)) + if (ia64_except_unwind_info () != UI_TARGET) return; /* Emit the .prologue directive. */ @@ -3961,7 +3973,7 @@ ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) static void ia64_output_function_end_prologue (FILE *file) { - if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS)) + if (ia64_except_unwind_info () != UI_TARGET) return; fputs ("\t.body\n", file); @@ -5554,11 +5566,6 @@ ia64_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - case OPT_mfixed_range_: fix_range (arg); return true; @@ -5615,7 +5622,9 @@ ia64_option_override (void) flag_ira_loop_pressure = 1; - ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE; + ia64_section_threshold = (global_options_set.x_g_switch_value + ? g_switch_value + : IA64_DEFAULT_GVALUE); init_machine_status = ia64_init_machine_status; @@ -5638,7 +5647,8 @@ ia64_override_options_after_change (void) flag_schedule_insns_after_reload = 0; if (optimize >= 3 - && ! sel_sched_switch_set) + && !global_options_set.x_flag_selective_scheduling + && !global_options_set.x_flag_selective_scheduling2) { flag_selective_scheduling2 = 1; flag_sel_sched_pipelining = 1; @@ -8558,7 +8568,7 @@ ia64_add_bundle_selector_before (int template0, rtx insn) ia64_emit_insn_before (b, insn); #if NR_BUNDLES == 10 if ((template0 == 4 || template0 == 5) - && (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) + && ia64_except_unwind_info () == UI_TARGET) { int i; rtx note = NULL_RTX; @@ -9399,7 +9409,7 @@ ia64_reorg (void) /* A call must not be the last instruction in a function, so that the return address is still within the function, so that unwinding works properly. Note that IA-64 differs from dwarf2 on this point. */ - if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)) + if (ia64_except_unwind_info () == UI_TARGET) { rtx insn; int saw_stop = 0; @@ -9865,8 +9875,7 @@ process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind) static void ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn) { - bool unwind = (flag_unwind_tables - || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)); + bool unwind = ia64_except_unwind_info () == UI_TARGET; bool frame = dwarf2out_do_frame (); rtx note, pat; bool handled_one; @@ -9991,6 +10000,33 @@ ia64_asm_init_sections (void) exception_section = get_unnamed_section (0, output_section_asm_op, "\t.handlerdata"); } + +/* Implement TARGET_DEBUG_UNWIND_INFO. */ + +static enum unwind_info_type +ia64_debug_unwind_info (void) +{ + return UI_TARGET; +} + +/* Implement TARGET_EXCEPT_UNWIND_INFO. */ + +static enum unwind_info_type +ia64_except_unwind_info (void) +{ + /* Honor the --enable-sjlj-exceptions configure switch. */ +#ifdef CONFIG_UNWIND_EXCEPTIONS + if (CONFIG_UNWIND_EXCEPTIONS) + return UI_SJLJ; +#endif + + /* For simplicity elsewhere in this file, indicate that all unwind + info is disabled if we're not emitting unwind tables. */ + if (!flag_exceptions && !flag_unwind_tables) + return UI_NONE; + + return UI_TARGET; +} enum ia64_builtins { @@ -9999,14 +10035,18 @@ enum ia64_builtins IA64_BUILTIN_FABSQ, IA64_BUILTIN_FLUSHRS, IA64_BUILTIN_INFQ, - IA64_BUILTIN_HUGE_VALQ + IA64_BUILTIN_HUGE_VALQ, + IA64_BUILTIN_max }; +static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max]; + void ia64_init_builtins (void) { tree fpreg_type; tree float80_type; + tree decl; /* The __fpreg type. */ fpreg_type = make_node (REAL_TYPE); @@ -10023,7 +10063,7 @@ ia64_init_builtins (void) /* The __float128 type. */ if (!TARGET_HPUX) { - tree ftype, decl; + tree ftype; tree float128_type = make_node (REAL_TYPE); TYPE_PRECISION (float128_type) = 128; @@ -10032,13 +10072,15 @@ ia64_init_builtins (void) /* TFmode support builtins. */ ftype = build_function_type (float128_type, void_list_node); - add_builtin_function ("__builtin_infq", ftype, - IA64_BUILTIN_INFQ, BUILT_IN_MD, - NULL, NULL_TREE); + decl = add_builtin_function ("__builtin_infq", ftype, + IA64_BUILTIN_INFQ, BUILT_IN_MD, + NULL, NULL_TREE); + ia64_builtins[IA64_BUILTIN_INFQ] = decl; - add_builtin_function ("__builtin_huge_valq", ftype, - IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, - NULL, NULL_TREE); + decl = add_builtin_function ("__builtin_huge_valq", ftype, + IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, + NULL, NULL_TREE); + ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl; ftype = build_function_type_list (float128_type, float128_type, @@ -10047,6 +10089,7 @@ ia64_init_builtins (void) IA64_BUILTIN_FABSQ, BUILT_IN_MD, "__fabstf2", NULL_TREE); TREE_READONLY (decl) = 1; + ia64_builtins[IA64_BUILTIN_FABSQ] = decl; ftype = build_function_type_list (float128_type, float128_type, @@ -10056,6 +10099,7 @@ ia64_init_builtins (void) IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD, "__copysigntf3", NULL_TREE); TREE_READONLY (decl) = 1; + ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl; } else /* Under HPUX, this is a synonym for "long double". */ @@ -10073,13 +10117,15 @@ ia64_init_builtins (void) add_builtin_function ((name), (type), (code), BUILT_IN_MD, \ NULL, NULL_TREE) - def_builtin ("__builtin_ia64_bsp", + decl = def_builtin ("__builtin_ia64_bsp", build_function_type (ptr_type_node, void_list_node), IA64_BUILTIN_BSP); + ia64_builtins[IA64_BUILTIN_BSP] = decl; - def_builtin ("__builtin_ia64_flushrs", + decl = def_builtin ("__builtin_ia64_flushrs", build_function_type (void_type_node, void_list_node), IA64_BUILTIN_FLUSHRS); + ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl; #undef def_builtin @@ -10149,6 +10195,17 @@ ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return NULL_RTX; } +/* Return the ia64 builtin for CODE. */ + +static tree +ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (code >= IA64_BUILTIN_max) + return error_mark_node; + + return ia64_builtins[code]; +} + /* For the HP-UX IA64 aggregate parameters are passed stored in the most significant bits of the stack slot. */ diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index dbb5ebd434b..98e9b64d05a 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -1731,12 +1731,6 @@ do { \ #define DWARF2_DEBUGGING_INFO 1 -/* We do not want call-frame info to be output, since debuggers are - supposed to use the target unwind info. Leave this undefined it - TARGET_UNWIND_INFO might ever be false. */ - -#define DWARF2_FRAME_INFO 0 - #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) /* Use tags for debug info labels, so that they don't break instruction @@ -1849,8 +1843,6 @@ do { \ extern int ia64_final_schedule; -#define TARGET_UNWIND_INFO 1 - #define TARGET_UNWIND_TABLES_DEFAULT true #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) diff --git a/gcc/config/iq2000/t-iq2000 b/gcc/config/iq2000/t-iq2000 index e7de5165ea8..487b9fcfea1 100644 --- a/gcc/config/iq2000/t-iq2000 +++ b/gcc/config/iq2000/t-iq2000 @@ -21,10 +21,6 @@ LIBGCC1 = CROSS_LIBGCC1 = -# We must build libgcc2.a with -G 0, in case the user wants to link -# without the $gp register. -TARGET_LIBGCC2_CFLAGS = -G 0 - LIB2FUNCS_EXTRA = $(srcdir)/config/udivmod.c $(srcdir)/config/divmod.c $(srcdir)/config/udivmodsi4.c $(srcdir)/config/iq2000/lib2extra-funcs.c # We want fine grained libraries, so use the new code to build the diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt index 9ace3e39b13..ba6b9f83e6d 100644 --- a/gcc/config/linux.opt +++ b/gcc/config/linux.opt @@ -24,9 +24,9 @@ Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Nega Use Bionic C library mglibc -Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) VarExists Negative(muclibc) +Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) Use GNU C library muclibc -Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) VarExists Negative(mbionic) +Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mbionic) Use uClibc C library diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c index a0e9472c5ec..671f0e16d27 100644 --- a/gcc/config/lm32/lm32.c +++ b/gcc/config/lm32/lm32.c @@ -75,11 +75,8 @@ static bool lm32_can_eliminate (const int, const int); static bool lm32_legitimate_address_p (enum machine_mode mode, rtx x, bool strict); static HOST_WIDE_INT lm32_compute_frame_size (int size); -static bool lm32_handle_option (size_t code, const char *arg, int value); static void lm32_option_override (void); -#undef TARGET_HANDLE_OPTION -#define TARGET_HANDLE_OPTION lm32_handle_option #undef TARGET_OPTION_OVERRIDE #define TARGET_OPTION_OVERRIDE lm32_option_override #undef TARGET_ADDRESS_COST @@ -698,23 +695,6 @@ lm32_setup_incoming_varargs (CUMULATIVE_ARGS * cum, enum machine_mode mode, } } -/* Implement TARGET_HANDLE_OPTION. */ - -static bool -lm32_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value) -{ - switch (code) - { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - - default: - return true; - } -} - /* Override command line options. */ static void lm32_option_override (void) @@ -797,7 +777,7 @@ lm32_in_small_data_p (const_tree exp) /* If this is an incomplete type with size 0, then we can't put it in sdata because it might be too big when completed. */ - if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) + if (size > 0 && size <= g_switch_value) return true; } diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h index 2698d40b896..b0c2d59ca9c 100644 --- a/gcc/config/lm32/lm32.h +++ b/gcc/config/lm32/lm32.h @@ -68,8 +68,6 @@ #undef LIB_SPEC #define LIB_SPEC "%{!T*:-T sim.ld}" -extern int target_flags; - /* Add -G xx support. */ #undef SWITCH_TAKES_ARG @@ -431,7 +429,7 @@ enum reg_class #undef ASM_OUTPUT_ALIGNED_LOCAL #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ do { \ - if ((SIZE) <= g_switch_value) \ + if ((SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ switch_to_section (sbss_section); \ else \ switch_to_section (bss_section); \ @@ -448,7 +446,7 @@ do { \ #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ do \ { \ - if ((SIZE) <= g_switch_value) \ + if ((SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ { \ switch_to_section (sbss_section); \ (*targetm.asm_out.globalize_label) (FILE, NAME); \ diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 066d1a84886..d62b4f2321c 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -3317,7 +3317,19 @@ m32c_subreg (enum machine_mode outer, return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0)); if (GET_CODE (x) != REG) - return simplify_gen_subreg (outer, x, inner, byte); + { + rtx r = simplify_gen_subreg (outer, x, inner, byte); + if (GET_CODE (r) == SUBREG + && GET_CODE (x) == MEM + && MEM_VOLATILE_P (x)) + { + /* Volatile MEMs don't get simplified, but we need them to + be. We are little endian, so the subreg byte is the + offset. */ + r = adjust_address (x, outer, byte); + } + return r; + } r = REGNO (x); if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO) diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index 6748f04527c..903f410a07d 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -210,11 +210,6 @@ m32r_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - case OPT_m32r: target_flags &= ~(MASK_M32R2 | MASK_M32RX); return true; @@ -270,7 +265,7 @@ m32r_init (void) m32r_punct_chars['@'] = 1; /* ??? no longer used */ /* Provide default value if not specified. */ - if (!g_switch_set) + if (!global_options_set.x_g_switch_value) g_switch_value = SDATA_DEFAULT_SIZE; } @@ -545,7 +540,7 @@ m32r_in_small_data_p (const_tree decl) { int size = int_size_in_bytes (TREE_TYPE (decl)); - if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) + if (size > 0 && size <= g_switch_value) return true; } } @@ -2106,7 +2101,7 @@ m32r_file_start (void) if (flag_verbose_asm) fprintf (asm_out_file, - "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n", + "%s M32R/D special options: -G %d\n", ASM_COMMENT_START, g_switch_value); if (TARGET_LITTLE_ENDIAN) diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index c232a74258c..d767cb9234e 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1227,7 +1227,8 @@ L2: .word STATIC do \ { \ if (! TARGET_SDATA_NONE \ - && (SIZE) > 0 && (SIZE) <= g_switch_value) \ + && (SIZE) > 0 \ + && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ else \ fprintf ((FILE), "%s", COMMON_ASM_OP); \ @@ -1240,7 +1241,8 @@ L2: .word STATIC do \ { \ if (! TARGET_SDATA_NONE \ - && (SIZE) > 0 && (SIZE) <= g_switch_value) \ + && (SIZE) > 0 \ + && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ switch_to_section (get_named_section (NULL, ".sbss", 0)); \ else \ switch_to_section (bss_section); \ diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c index ea60db6a35c..bf9c26cbbef 100644 --- a/gcc/config/m68hc11/m68hc11.c +++ b/gcc/config/m68hc11/m68hc11.c @@ -76,6 +76,7 @@ static int m68hc11_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); static bool m68hc11_rtx_costs (rtx, int, int, int *, bool); static tree m68hc11_handle_fntype_attribute (tree *, tree, tree, int, bool *); static tree m68hc11_handle_page0_attribute (tree *, tree, tree, int, bool *); +static bool m68hc11_class_likely_spilled_p (reg_class_t); void create_regs_rtx (void); @@ -291,6 +292,9 @@ static const struct attribute_spec m68hc11_attribute_table[] = #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE m68hc11_can_eliminate +#undef TARGET_CLASS_LIKELY_SPILLED_P +#define TARGET_CLASS_LIKELY_SPILLED_P m68hc11_class_likely_spilled_p + #undef TARGET_TRAMPOLINE_INIT #define TARGET_TRAMPOLINE_INIT m68hc11_trampoline_init @@ -581,6 +585,32 @@ preferred_reload_class (rtx operand, enum reg_class rclass) return rclass; } +/* Implement TARGET_CLASS_LIKELY_SPILLED_P. */ + +static bool +m68hc11_class_likely_spilled_p (reg_class_t rclass) +{ + switch (rclass) + { + case D_REGS: + case X_REGS: + case Y_REGS: + case A_REGS: + case SP_REGS: + case D_OR_X_REGS: + case D_OR_Y_REGS: + case X_OR_SP_REGS: + case Y_OR_SP_REGS: + case D_OR_SP_REGS: + return true; + + default: + break; + } + + return false; +} + /* Return 1 if the operand is a valid indexed addressing mode. For 68hc11: n,r with n in [0..255] and r in A_REGS class For 68hc12: n,r no constraint on the constant, r in A_REGS class. */ diff --git a/gcc/config/m68hc11/m68hc11.h b/gcc/config/m68hc11/m68hc11.h index f19180d4a1b..9e45cb51496 100644 --- a/gcc/config/m68hc11/m68hc11.h +++ b/gcc/config/m68hc11/m68hc11.h @@ -704,34 +704,6 @@ extern enum reg_class m68hc11_tmp_regs_class; #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) -/* A C expression whose value is nonzero if pseudos that have been - assigned to registers of class CLASS would likely be spilled - because registers of CLASS are needed for spill registers. - - The default value of this macro returns 1 if CLASS has exactly one - register and zero otherwise. On most machines, this default - should be used. Only define this macro to some other expression - if pseudo allocated by `local-alloc.c' end up in memory because - their hard registers were needed for spill registers. If this - macro returns nonzero for those classes, those pseudos will only - be allocated by `global.c', which knows how to reallocate the - pseudo to another register. If there would not be another - register available for reallocation, you should not change the - definition of this macro since the only effect of such a - definition would be to slow down register allocation. */ - -#define CLASS_LIKELY_SPILLED_P(CLASS) \ - (((CLASS) == D_REGS) \ - || ((CLASS) == X_REGS) \ - || ((CLASS) == Y_REGS) \ - || ((CLASS) == A_REGS) \ - || ((CLASS) == SP_REGS) \ - || ((CLASS) == D_OR_X_REGS) \ - || ((CLASS) == D_OR_Y_REGS) \ - || ((CLASS) == X_OR_SP_REGS) \ - || ((CLASS) == Y_OR_SP_REGS) \ - || ((CLASS) == D_OR_SP_REGS)) - /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 5044811761b..11047c91a21 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -134,7 +134,6 @@ extern char * mcore_current_function_name; #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) /* Largest increment in UNITS we allow the stack to grow in a single operation. */ -extern int mcore_stack_increment; #define STACK_UNITS_MAXSTEP 4096 /* Allocation boundary (in *bits*) for the code of a function. */ diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md index 65b91588fc2..532181db0cc 100644 --- a/gcc/config/mcore/mcore.md +++ b/gcc/config/mcore/mcore.md @@ -1,5 +1,5 @@ ;; Machine description the Motorola MCore -;; Copyright (C) 1993, 1999, 2000, 2004, 2005, 2007 +;; Copyright (C) 1993, 1999, 2000, 2004, 2005, 2007, 2009, 2010 ;; Free Software Foundation, Inc. ;; Contributed by Motorola. @@ -697,8 +697,6 @@ "" " { - extern int flag_omit_frame_pointer; - /* If this is an add to the frame pointer, then accept it as is so that we can later fold in the fp/sp offset from frame pointer elimination. */ diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h index 1bebf3badb7..ad2cf306a5a 100644 --- a/gcc/config/mep/mep.h +++ b/gcc/config/mep/mep.h @@ -108,8 +108,6 @@ crtbegin.o%s" } \ while (0) -extern int target_flags; - /* Controlled by MeP-Integrator. */ #define TARGET_H1 0 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md new file mode 100644 index 00000000000..2abe3019016 --- /dev/null +++ b/gcc/config/microblaze/constraints.md @@ -0,0 +1,72 @@ +;; Constraint definitions for Xilinx MicroBlaze processors. +;; Copyright 2010 Free Software Foundation, Inc. + +;; Contributed by Michael Eager <eager@eagercon.com>. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_register_constraint "d" "GR_REGS" + "A general register.") + +(define_register_constraint "z" "ST_REGS" + "A status register.") + +;; Define integer constraints + +(define_constraint "I" + "A signed 16-bit constant." + (and (match_code "const_int") + (match_test "SMALL_OPERAND (ival)"))) + +(define_constraint "J" + "Integer zero." + (and (match_code "const_int") + (match_test "ival == 0"))) + +(define_constraint "M" + "A constant which needs two instructions to load." + (and (match_code "const_int") + (match_test "LARGE_OPERAND (ival)"))) + +(define_constraint "N" + "A constant in the range -65535 to -1 (inclusive)." + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) (ival + 0xffff) < 0xffff"))) + +(define_constraint "P" + "A constant in the range 1 to 65535 (inclusive)." + (and (match_code "const_int") + (match_test "ival > 0 && ival < 0x10000"))) + +;; Define floating point constraints + +(define_constraint "G" + "Floating-point zero." + (and (match_code "const_double") + (match_test "op == CONST0_RTX (mode)"))) + +;; Define memory constraints + +(define_memory_constraint "R" + "Memory operand which fits in single instruction." + (and (match_code "mem") + (match_test "simple_memory_operand (op, GET_MODE (op))"))) + +(define_memory_constraint "T" + "Double word operand." + (and (match_code "mem") + (match_test "double_memory_operand (op, GET_MODE (op))"))) diff --git a/gcc/config/microblaze/crti.s b/gcc/config/microblaze/crti.s new file mode 100644 index 00000000000..3944443b437 --- /dev/null +++ b/gcc/config/microblaze/crti.s @@ -0,0 +1,39 @@ +/* crti.s for __init, __fini + This file supplies the prologue for __init and __fini routines + + Copyright 2009, 2010 Free Software Foundation, Inc. + + Contributed by Michael Eager <eager@eagercon.com>. + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) any + later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .init, "ax" + .global __init + .align 2 +__init: + addik r1, r1, -8 + sw r15, r0, r1 + + .section .fini, "ax" + .global __fini + .align 2 +__fini: + addik r1, r1, -8 + sw r15, r0, r1 diff --git a/gcc/config/microblaze/crtn.s b/gcc/config/microblaze/crtn.s new file mode 100644 index 00000000000..7970dee1c93 --- /dev/null +++ b/gcc/config/microblaze/crtn.s @@ -0,0 +1,35 @@ +/* crtn.s for __init, __fini + This file supplies the epilogue for __init and __fini routines + + Copyright 2009, 2010 Free Software Foundation, Inc. + + Contributed by Michael Eager <eager@eagercon.com>. + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) any + later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 8 + + .section .fini, "ax" + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 8 diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h new file mode 100644 index 00000000000..adf5fcccf38 --- /dev/null +++ b/gcc/config/microblaze/linux.h @@ -0,0 +1,35 @@ +/* Definitions for MicroBlaze running Linux. + Copyright 2009, 2010 Free Software Foundation, Inc. + + This file is part of GCC. + + Contributed by Michael Eager <eager@eagercon.com>. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + + +#define DYNAMIC_LINKER "/lib/ld.so.1" +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "dynamic_linker", DYNAMIC_LINKER } + +#undef LINK_SPEC +#define LINK_SPEC "%{shared:-shared} \ + %{!shared: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker %(dynamic_linker)}} \ + %{static:-static}}" + diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c new file mode 100644 index 00000000000..3b0059e71c7 --- /dev/null +++ b/gcc/config/microblaze/microblaze-c.c @@ -0,0 +1,93 @@ +/* Subroutines used for the C front end for Xilinx MicroBlaze. + Copyright 2010 Free Software Foundation, Inc. + + Contributed by Michael Eager <eager@eagercon.com>. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "cpplib.h" +#include "tree.h" +#include "c-family/c-common.h" +#include "toplev.h" +#include "tm_p.h" +#include "target.h" + +#define builtin_define(TXT) cpp_define (pfile, TXT) +#define builtin_assert(TXT) cpp_assert (pfile, TXT) + +/* Define preprocessor symbols for MicroBlaze. + Symbols which do not start with __ are deprecated. */ + +void +microblaze_cpp_define (cpp_reader *pfile) +{ + builtin_assert ("cpu=microblaze"); + builtin_assert ("machine=microblaze"); + builtin_define ("__MICROBLAZE__"); + if (!TARGET_SOFT_MUL) + { + if (!flag_iso) + builtin_define ("HAVE_HW_MUL"); + builtin_define ("__HAVE_HW_MUL__"); + } + if (TARGET_MULTIPLY_HIGH) + { + if (!flag_iso) + builtin_define ("HAVE_HW_MUL_HIGH"); + builtin_define ("__HAVE_HW_MUL_HIGH__"); + } + if (!TARGET_SOFT_DIV) + { + if (!flag_iso) + builtin_define ("HAVE_HW_DIV"); + builtin_define ("__HAVE_HW_DIV__"); + } + if (TARGET_BARREL_SHIFT) + { + if (!flag_iso) + builtin_define ("HAVE_HW_BSHIFT"); + builtin_define ("__HAVE_HW_BSHIFT__"); + } + if (TARGET_PATTERN_COMPARE) + { + if (!flag_iso) + builtin_define ("HAVE_HW_PCMP"); + builtin_define ("__HAVE_HW_PCMP__"); + } + if (TARGET_HARD_FLOAT) + { + if (!flag_iso) + builtin_define ("HAVE_HW_FPU"); + builtin_define ("__HAVE_HW_FPU__"); + } + if (TARGET_FLOAT_CONVERT) + { + if (!flag_iso) + builtin_define ("HAVE_HW_FPU_CONVERT"); + builtin_define ("__HAVE_HW_FPU_CONVERT__"); + } + if (TARGET_FLOAT_SQRT) + { + if (!flag_iso) + builtin_define ("HAVE_HW_FPU_SQRT"); + builtin_define ("__HAVE_HW_FPU_SQRT__"); + } +} diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h new file mode 100644 index 00000000000..ca8ca6e8dc3 --- /dev/null +++ b/gcc/config/microblaze/microblaze-protos.h @@ -0,0 +1,64 @@ +/* Definitions of target machine for GNU compiler, for Xilinx MicroBlaze. + Copyright 2009, 2010 Free Software Foundation, Inc. + + This file is part of GCC. + + Contributed by Michael Eager <eager@eagercon.com>. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#ifndef GCC_MICROBLAZE_PROTOS_H +#define GCC_MICROBLAZE_PROTOS_H + +#ifdef RTX_CODE +extern int pic_address_needs_scratch (rtx); +extern void expand_block_move (rtx *); +extern void microblaze_expand_prologue (void); +extern void microblaze_expand_epilogue (void); +extern void override_options (void); +extern int microblaze_expand_shift (rtx *); +extern bool microblaze_expand_move (enum machine_mode, rtx *); +extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); +extern void microblaze_expand_divide (rtx *); +extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); +extern void microblaze_expand_conditional_branch_sf (rtx *); +extern int microblaze_can_use_return_insn (void); +extern int microblaze_const_double_ok (rtx, enum machine_mode); +extern void print_operand (FILE *, rtx, int); +extern void print_operand_address (FILE *, rtx); +extern void init_cumulative_args (CUMULATIVE_ARGS *,tree, rtx); +extern bool microblaze_legitimate_address_p (enum machine_mode, rtx, bool); +extern int microblaze_is_interrupt_handler (void); +extern rtx microblaze_return_addr (int, rtx); +extern int simple_memory_operand (rtx, enum machine_mode); +extern int double_memory_operand (rtx, enum machine_mode); + +extern int microblaze_regno_ok_for_base_p (int, int); +extern HOST_WIDE_INT microblaze_initial_elimination_offset (int, int); +extern void microblaze_declare_object (FILE *, const char *, const char *, + const char *, int); +extern void microblaze_asm_output_ident (FILE *, const char *); +#endif /* RTX_CODE */ + +#ifdef TREE_CODE +extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, + tree, int); +extern rtx function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int); +#endif /* TREE_CODE */ + +/* Declare functions in microblaze-c.c. */ +extern void microblaze_cpp_define (struct cpp_reader *); + +#endif /* GCC_MICROBLAZE_PROTOS_H */ diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c new file mode 100644 index 00000000000..9872d8f7e2c --- /dev/null +++ b/gcc/config/microblaze/microblaze.c @@ -0,0 +1,3033 @@ +/* Subroutines used for code generation on Xilinx MicroBlaze. + Copyright 2009, 2010 Free Software Foundation, Inc. + + Contributed by Michael Eager <eager@eagercon.com>. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include <signal.h> +#include "tm.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" +#include "integrate.h" +#include "recog.h" +#include "toplev.h" +#include "tree.h" +#include "function.h" +#include "expr.h" +#include "flags.h" +#include "reload.h" +#include "output.h" +#include "ggc.h" +#include "hashtab.h" +#include "target.h" +#include "target-def.h" +#include "tm_p.h" +#include "gstab.h" +#include "df.h" +#include "optabs.h" +#include "diagnostic-core.h" + +#define MICROBLAZE_VERSION_COMPARE(VA,VB) strcasecmp (VA, VB) + +/* Classifies an address. + +ADDRESS_INVALID +An invalid address. + +ADDRESS_REG + +A natural register or a register + const_int offset address. +The register satisfies microblaze_valid_base_register_p and the +offset is a const_arith_operand. + +ADDRESS_REG_INDEX + +A natural register offset by the index contained in an index register. The base +register satisfies microblaze_valid_base_register_p and the index register +satisfies microblaze_valid_index_register_p + +ADDRESS_CONST_INT + +A signed 16/32-bit constant address. + +ADDRESS_SYMBOLIC: + +A constant symbolic address or a (register + symbol). */ + +enum microblaze_address_type +{ + ADDRESS_INVALID, + ADDRESS_REG, + ADDRESS_REG_INDEX, + ADDRESS_CONST_INT, + ADDRESS_SYMBOLIC, + ADDRESS_GOTOFF, + ADDRESS_PLT +}; + +/* Classifies symbols + +SYMBOL_TYPE_GENERAL + +A general symbol. */ +enum microblaze_symbol_type +{ + SYMBOL_TYPE_INVALID, + SYMBOL_TYPE_GENERAL +}; + +/* Classification of a MicroBlaze address. */ +struct microblaze_address_info +{ + enum microblaze_address_type type; + rtx regA; /* Contains valid values on ADDRESS_REG, ADDRESS_REG_INDEX, + ADDRESS_SYMBOLIC. */ + rtx regB; /* Contains valid values on ADDRESS_REG_INDEX. */ + rtx offset; /* Contains valid values on ADDRESS_CONST_INT and ADDRESS_REG. */ + rtx symbol; /* Contains valid values on ADDRESS_SYMBOLIC. */ + enum microblaze_symbol_type symbol_type; +}; + +/* Structure to be filled in by compute_frame_size with register + save masks, and offsets for the current function. */ + +struct GTY(()) microblaze_frame_info { + long total_size; /* # bytes that the entire frame takes up. */ + long var_size; /* # bytes that variables take up. */ + long args_size; /* # bytes that outgoing arguments take up. */ + int link_debug_size; /* # bytes for the link reg and back pointer. */ + int gp_reg_size; /* # bytes needed to store gp regs. */ + long gp_offset; /* offset from new sp to store gp registers. */ + long mask; /* mask of saved gp registers. */ + int initialized; /* != 0 if frame size already calculated. */ + int num_gp; /* number of gp registers saved. */ + long insns_len; /* length of insns. */ + int alloc_stack; /* Flag to indicate if the current function + must not create stack space. (As an optimization). */ +}; + +/* Global variables for machine-dependent things. */ + +/* Toggle which pipleline interface to use. */ +static GTY(()) int microblaze_sched_use_dfa = 0; + +/* Threshold for data being put into the small data/bss area, instead + of the normal data area (references to the small data/bss area take + 1 instruction, and use the global pointer, references to the normal + data area takes 2 instructions). */ +int microblaze_section_threshold = -1; + +/* Prevent scheduling potentially exception causing instructions in + delay slots. -mcpu=v3.00.a or v4.00.a turns this on. */ +int microblaze_no_unsafe_delay; + +/* Which CPU pipeline do we use. We haven't really standardized on a CPU + version having only a particular type of pipeline. There can still be + options on the CPU to scale pipeline features up or down. :( + Bad Presentation (??), so we let the MD file rely on the value of + this variable instead Making PIPE_5 the default. It should be backward + optimal with PIPE_3 MicroBlazes. */ +enum pipeline_type microblaze_pipe = MICROBLAZE_PIPE_5; + +/* High and low marks for floating point values which we will accept + as legitimate constants for LEGITIMATE_CONSTANT_P. These are + initialized in override_options. */ +REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow; + +/* Array giving truth value on whether or not a given hard register + can support a given mode. */ +char microblaze_hard_regno_mode_ok[(int)MAX_MACHINE_MODE] + [FIRST_PSEUDO_REGISTER]; + +/* Current frame information calculated by compute_frame_size. */ +struct microblaze_frame_info current_frame_info; + +/* Zero structure to initialize current_frame_info. */ +struct microblaze_frame_info zero_frame_info; + +/* List of all MICROBLAZE punctuation characters used by print_operand. */ +char microblaze_print_operand_punct[256]; + +/* Map GCC register number to debugger register number. */ +int microblaze_dbx_regno[FIRST_PSEUDO_REGISTER]; + +/* Map hard register number to register class. */ +enum reg_class microblaze_regno_to_class[] = +{ + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + ST_REGS, GR_REGS, GR_REGS, GR_REGS +}; + +/* MicroBlaze specific machine attributes. + interrupt_handler - Interrupt handler attribute to add interrupt prologue + and epilogue and use appropriate interrupt return. + save_volatiles - Similiar to interrupt handler, but use normal return. */ +int interrupt_handler; +int save_volatiles; + +const struct attribute_spec microblaze_attribute_table[] = { + /* name min_len, max_len, decl_req, type_req, fn_type, req_handler */ + {"interrupt_handler", 0, 0, true, false, false, NULL}, + {"save_volatiles" , 0, 0, true, false, false, NULL}, + { NULL, 0, 0, false, false, false, NULL} +}; + +static int microblaze_interrupt_function_p (tree); + +section *sdata2_section; + +/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ +int +microblaze_const_double_ok (rtx op, enum machine_mode mode) +{ + REAL_VALUE_TYPE d; + + if (GET_CODE (op) != CONST_DOUBLE) + return 0; + + if (mode == VOIDmode) + return 1; + + if (mode != SFmode && mode != DFmode) + return 0; + + if (op == CONST0_RTX (mode)) + return 1; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + if (REAL_VALUE_ISNAN (d)) + return FALSE; + + if (REAL_VALUE_NEGATIVE (d)) + d = real_value_negate (&d); + + if (mode == DFmode) + { + if (REAL_VALUES_LESS (d, dfhigh) && REAL_VALUES_LESS (dflow, d)) + return 1; + } + else + { + if (REAL_VALUES_LESS (d, sfhigh) && REAL_VALUES_LESS (sflow, d)) + return 1; + } + + return 0; +} + +/* Return truth value if a memory operand fits in a single instruction + (ie, register + small offset) or (register + register). */ + +int +simple_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) +{ + rtx addr, plus0, plus1; + + /* Eliminate non-memory operations. */ + if (GET_CODE (op) != MEM) + return 0; + + /* dword operations really put out 2 instructions, so eliminate them. */ + /* ??? This isn't strictly correct. It is OK to accept multiword modes + here, since the length attributes are being set correctly, but only + if the address is offsettable. */ + if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD) + return 0; + + + /* Decode the address now. */ + addr = XEXP (op, 0); + switch (GET_CODE (addr)) + + { + case REG: + return 1; + + case PLUS: + plus0 = XEXP (addr, 0); + plus1 = XEXP (addr, 1); + + if (GET_CODE (plus0) == REG && GET_CODE (plus1) == CONST_INT + && SMALL_INT (plus1)) + { + return 1; + } + else if (GET_CODE (plus1) == REG && GET_CODE (plus0) == CONST_INT) + { + return 1; + } + else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) + { + return 1; + } + else + return 0; + + case SYMBOL_REF: + return 0; + + default: + break; + } + + return 0; +} + +/* Return nonzero for a memory address that can be used to load or store + a doubleword. */ + +int +double_memory_operand (rtx op, enum machine_mode mode) +{ + rtx addr; + + if (GET_CODE (op) != MEM || !memory_operand (op, mode)) + { + /* During reload, we accept a pseudo register if it has an + appropriate memory address. If we don't do this, we will + wind up reloading into a register, and then reloading that + register from memory, when we could just reload directly from + memory. */ + if (reload_in_progress + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (op)] < 0 + && reg_equiv_mem[REGNO (op)] != 0 + && double_memory_operand (reg_equiv_mem[REGNO (op)], mode)) + return 1; + return 0; + } + + /* Make sure that 4 added to the address is a valid memory address. + This essentially just checks for overflow in an added constant. */ + + addr = XEXP (op, 0); + + if (CONSTANT_ADDRESS_P (addr)) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT + ? SImode : SFmode), plus_constant (addr, 4)); +} + +/* Implement REG_OK_FOR_BASE_P -and- REG_OK_FOR_INDEX_P. */ +int +microblaze_regno_ok_for_base_p (int regno, int strict) +{ + if (regno >= FIRST_PSEUDO_REGISTER) + { + if (!strict) + return true; + regno = reg_renumber[regno]; + } + + /* These fake registers will be eliminated to either the stack or + hard frame pointer, both of which are usually valid base registers. + Reload deals with the cases where the eliminated form isn't valid. */ + if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) + return true; + + return GP_REG_P (regno); +} + +/* Return true if X is a valid base register for the given mode. + Allow only hard registers if STRICT. */ + +static bool +microblaze_valid_base_register_p (rtx x, + enum machine_mode mode ATTRIBUTE_UNUSED, + int strict) +{ + if (!strict && GET_CODE (x) == SUBREG) + x = SUBREG_REG (x); + + return (GET_CODE (x) == REG + && microblaze_regno_ok_for_base_p (REGNO (x), strict)); +} + +static bool +microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) +{ + info->symbol_type = SYMBOL_TYPE_GENERAL; + info->symbol = XVECEXP (x, 0, 0); + + if (XINT (x, 1) == UNSPEC_GOTOFF) + { + info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); + info->type = ADDRESS_GOTOFF; + } + else if (XINT (x, 1) == UNSPEC_PLT) + { + info->type = ADDRESS_PLT; + } + else + { + return false; + } + return true; +} + + +/* Return true if X is a valid index register for the given mode. + Allow only hard registers if STRICT. */ + +static bool +microblaze_valid_index_register_p (rtx x, + enum machine_mode mode ATTRIBUTE_UNUSED, + int strict) +{ + if (!strict && GET_CODE (x) == SUBREG) + x = SUBREG_REG (x); + + return (GET_CODE (x) == REG + /* A base register is good enough to be an index register on MicroBlaze. */ + && microblaze_regno_ok_for_base_p (REGNO (x), strict)); +} + +/* Get the base register for accessing a value from the memory or + Symbol ref. Used for MicroBlaze Small Data Area Pointer Optimization. */ +static int +get_base_reg (rtx x) +{ + tree decl; + int base_reg = (flag_pic ? MB_ABI_PIC_ADDR_REGNUM : MB_ABI_BASE_REGNUM); + + if (TARGET_XLGPOPT + && GET_CODE (x) == SYMBOL_REF + && SYMBOL_REF_SMALL_P (x) && (decl = SYMBOL_REF_DECL (x)) != NULL) + { + if (TREE_READONLY (decl)) + base_reg = MB_ABI_GPRO_REGNUM; + else + base_reg = MB_ABI_GPRW_REGNUM; + } + + return base_reg; +} + +/* Return true if X is a valid address for machine mode MODE. If it is, + fill in INFO appropriately. STRICT is true if we should only accept + hard base registers. + + type regA regB offset symbol + + ADDRESS_INVALID NULL NULL NULL NULL + + ADDRESS_REG %0 NULL const_0 / NULL + const_int + ADDRESS_REG_INDEX %0 %1 NULL NULL + + ADDRESS_SYMBOLIC r0 / NULL NULL symbol + sda_base_reg + + ADDRESS_CONST_INT r0 NULL const NULL + + For modes spanning multiple registers (DFmode in 32-bit GPRs, + DImode, TImode), indexed addressing cannot be used because + adjacent memory cells are accessed by adding word-sized offsets + during assembly output. */ + +static bool +microblaze_classify_address (struct microblaze_address_info *info, rtx x, + enum machine_mode mode, int strict) +{ + rtx xplus0; + rtx xplus1; + + info->type = ADDRESS_INVALID; + info->regA = NULL; + info->regB = NULL; + info->offset = NULL; + info->symbol = NULL; + info->symbol_type = SYMBOL_TYPE_INVALID; + + switch (GET_CODE (x)) + { + case REG: + case SUBREG: + { + info->type = ADDRESS_REG; + info->regA = x; + info->offset = const0_rtx; + return microblaze_valid_base_register_p (info->regA, mode, strict); + } + case PLUS: + { + xplus0 = XEXP (x, 0); + xplus1 = XEXP (x, 1); + + if (microblaze_valid_base_register_p (xplus0, mode, strict)) + { + info->type = ADDRESS_REG; + info->regA = xplus0; + + if (GET_CODE (xplus1) == CONST_INT) + { + info->offset = xplus1; + return true; + } + else if (GET_CODE (xplus1) == UNSPEC) + { + return microblaze_classify_unspec (info, xplus1); + } + else if ((GET_CODE (xplus1) == SYMBOL_REF || + GET_CODE (xplus1) == LABEL_REF) && flag_pic == 2) + { + return false; + } + else if (GET_CODE (xplus1) == SYMBOL_REF || + GET_CODE (xplus1) == LABEL_REF || + GET_CODE (xplus1) == CONST) + { + if (GET_CODE (XEXP (xplus1, 0)) == UNSPEC) + return microblaze_classify_unspec (info, XEXP (xplus1, 0)); + else if (flag_pic == 2) + { + return false; + } + info->type = ADDRESS_SYMBOLIC; + info->symbol = xplus1; + info->symbol_type = SYMBOL_TYPE_GENERAL; + return true; + } + else if (GET_CODE (xplus1) == REG + && microblaze_valid_index_register_p (xplus1, mode, + strict) + && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)) + { + /* Restrict larger than word-width modes from using an index register. */ + info->type = ADDRESS_REG_INDEX; + info->regB = xplus1; + return true; + } + } + break; + } + case CONST_INT: + { + info->regA = gen_rtx_raw_REG (mode, 0); + info->type = ADDRESS_CONST_INT; + info->offset = x; + return true; + } + case CONST: + case LABEL_REF: + case SYMBOL_REF: + { + info->type = ADDRESS_SYMBOLIC; + info->symbol_type = SYMBOL_TYPE_GENERAL; + info->symbol = x; + info->regA = gen_rtx_raw_REG (mode, get_base_reg (x)); + + if (GET_CODE (x) == CONST) + { + return !(flag_pic && pic_address_needs_scratch (x)); + } + else if (flag_pic == 2) + { + return false; + } + + return true; + } + + case UNSPEC: + { + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + return microblaze_classify_unspec (info, x); + } + + default: + return false; + } + + return false; +} + +/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It + returns a nonzero value if X is a legitimate address for a memory + operand of the indicated MODE. STRICT is nonzero if this function + is called during reload. */ + +bool +microblaze_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) +{ + struct microblaze_address_info addr; + + return microblaze_classify_address (&addr, x, mode, strict); +} + + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This is used from only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was + called. In some cases it is useful to look at this to decide what + needs to be done. + + It is always safe for this function to do nothing. It exists to + recognize opportunities to optimize the output. + + For the MicroBlaze, transform: + + memory(X + <large int>) + + into: + + Y = <large int> & ~0x7fff; + Z = X + Y + memory (Z + (<large int> & 0x7fff)); + + This is for CSE to find several similar references, and only use one Z. + + When PIC, convert addresses of the form memory (symbol+large int) to + memory (reg+large int). */ + +static rtx +microblaze_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED) +{ + register rtx xinsn = x, result; + + if (GET_CODE (xinsn) == CONST + && flag_pic && pic_address_needs_scratch (xinsn)) + { + rtx ptr_reg = gen_reg_rtx (Pmode); + rtx constant = XEXP (XEXP (xinsn, 0), 1); + + emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); + + result = gen_rtx_PLUS (Pmode, ptr_reg, constant); + if (SMALL_INT (constant)) + return result; + /* Otherwise we fall through so the code below will fix the + constant. */ + xinsn = result; + } + + if (GET_CODE (xinsn) == PLUS) + { + register rtx xplus0 = XEXP (xinsn, 0); + register rtx xplus1 = XEXP (xinsn, 1); + register enum rtx_code code0 = GET_CODE (xplus0); + register enum rtx_code code1 = GET_CODE (xplus1); + + if (code0 != REG && code1 == REG) + { + xplus0 = XEXP (xinsn, 1); + xplus1 = XEXP (xinsn, 0); + code0 = GET_CODE (xplus0); + code1 = GET_CODE (xplus1); + } + + if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) + && code1 == CONST_INT && !SMALL_INT (xplus1)) + { + rtx int_reg = gen_reg_rtx (Pmode); + rtx ptr_reg = gen_reg_rtx (Pmode); + + emit_move_insn (int_reg, GEN_INT (INTVAL (xplus1) & ~0x7fff)); + + emit_insn (gen_rtx_SET (VOIDmode, + ptr_reg, + gen_rtx_PLUS (Pmode, xplus0, int_reg))); + + result = gen_rtx_PLUS (Pmode, ptr_reg, + GEN_INT (INTVAL (xplus1) & 0x7fff)); + return result; + } + + if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) && flag_pic == 2) + { + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + if (code1 == CONST) + { + xplus1 = XEXP (xplus1, 0); + code1 = GET_CODE (xplus1); + } + if (code1 == SYMBOL_REF) + { + result = + gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xplus1), UNSPEC_GOTOFF); + result = gen_rtx_CONST (Pmode, result); + result = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, result); + result = gen_const_mem (Pmode, result); + result = gen_rtx_PLUS (Pmode, xplus0, result); + return result; + } + } + } + + if (GET_CODE (xinsn) == SYMBOL_REF) + { + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + result = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xinsn), UNSPEC_GOTOFF); + result = gen_rtx_CONST (Pmode, result); + result = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, result); + result = gen_const_mem (Pmode, result); + return result; + } + + return x; +} + +/* Block Moves. */ + +#define MAX_MOVE_REGS 8 +#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) + +/* Emit straight-line code to move LENGTH bytes from SRC to DEST. + Assume that the areas do not overlap. */ + +static void +microblaze_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) +{ + HOST_WIDE_INT offset, delta; + unsigned HOST_WIDE_INT bits; + int i; + enum machine_mode mode; + rtx *regs; + + bits = BITS_PER_WORD; + mode = mode_for_size (bits, MODE_INT, 0); + delta = bits / BITS_PER_UNIT; + + /* Allocate a buffer for the temporary registers. */ + regs = alloca (sizeof (rtx) * length / delta); + + /* Load as many BITS-sized chunks as possible. Use a normal load if + the source has enough alignment, otherwise use left/right pairs. */ + for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) + { + regs[i] = gen_reg_rtx (mode); + emit_move_insn (regs[i], adjust_address (src, mode, offset)); + } + + /* Copy the chunks to the destination. */ + for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) + emit_move_insn (adjust_address (dest, mode, offset), regs[i]); + + /* Mop up any left-over bytes. */ + if (offset < length) + { + src = adjust_address (src, BLKmode, offset); + dest = adjust_address (dest, BLKmode, offset); + move_by_pieces (dest, src, length - offset, + MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); + } +} + +/* Helper function for doing a loop-based block operation on memory + reference MEM. Each iteration of the loop will operate on LENGTH + bytes of MEM. + + Create a new base register for use within the loop and point it to + the start of MEM. Create a new memory reference that uses this + register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ + +static void +microblaze_adjust_block_mem (rtx mem, HOST_WIDE_INT length, + rtx * loop_reg, rtx * loop_mem) +{ + *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); + + /* Although the new mem does not refer to a known location, + it does keep up to LENGTH bytes of alignment. */ + *loop_mem = change_address (mem, BLKmode, *loop_reg); + set_mem_align (*loop_mem, + MIN ((HOST_WIDE_INT) MEM_ALIGN (mem), + length * BITS_PER_UNIT)); +} + + +/* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES + per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the + memory regions do not overlap. */ + +static void +microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) +{ + rtx label, src_reg, dest_reg, final_src; + HOST_WIDE_INT leftover; + + leftover = length % MAX_MOVE_BYTES; + length -= leftover; + + /* Create registers and memory references for use within the loop. */ + microblaze_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src); + microblaze_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest); + + /* Calculate the value that SRC_REG should have after the last iteration + of the loop. */ + final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), + 0, 0, OPTAB_WIDEN); + + /* Emit the start of the loop. */ + label = gen_label_rtx (); + emit_label (label); + + /* Emit the loop body. */ + microblaze_block_move_straight (dest, src, MAX_MOVE_BYTES); + + /* Move on to the next block. */ + emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES)); + emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES)); + + /* Emit the test & branch. */ + emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), + src_reg, final_src, label)); + + /* Mop up any left-over bytes. */ + if (leftover) + microblaze_block_move_straight (dest, src, leftover); +} + +/* Expand a movmemsi instruction. */ + +bool +microblaze_expand_block_move (rtx dest, rtx src, rtx length, rtx align_rtx) +{ + + if (GET_CODE (length) == CONST_INT) + { + HOST_WIDE_INT bytes = INTVAL (length); + int align = INTVAL (align_rtx); + + if (align > UNITS_PER_WORD) + { + align = UNITS_PER_WORD; /* We can't do any better. */ + } + else if (align < UNITS_PER_WORD) + { + if (INTVAL (length) <= MAX_MOVE_BYTES) + { + move_by_pieces (dest, src, bytes, align, 0); + return true; + } + else + return false; + } + + if (INTVAL (length) <= 2 * MAX_MOVE_BYTES) + { + microblaze_block_move_straight (dest, src, INTVAL (length)); + return true; + } + else if (optimize) + { + microblaze_block_move_loop (dest, src, INTVAL (length)); + return true; + } + } + return false; +} + +static bool +microblaze_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total, + bool speed ATTRIBUTE_UNUSED) +{ + enum machine_mode mode = GET_MODE (x); + + switch (code) + { + case MEM: + { + int num_words = (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ? 2 : 1; + if (simple_memory_operand (x, mode)) + *total = COSTS_N_INSNS (2 * num_words); + else + *total = COSTS_N_INSNS (2 * (2 * num_words)); + + return true; + } + case NOT: + { + if (mode == DImode) + { + *total = COSTS_N_INSNS (2); + } + else + *total = COSTS_N_INSNS (1); + return false; + } + case AND: + case IOR: + case XOR: + { + if (mode == DImode) + { + *total = COSTS_N_INSNS (2); + } + else + *total = COSTS_N_INSNS (1); + + return false; + } + case ASHIFT: + case ASHIFTRT: + case LSHIFTRT: + { + if (TARGET_BARREL_SHIFT) + { + if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") + >= 0) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (2); + } + else if (!TARGET_SOFT_MUL) + *total = COSTS_N_INSNS (1); + else if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + /* Add 1 to make shift slightly more expensive than add. */ + *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))) + 1; + /* Reduce shift costs for for special circumstances. */ + if (optimize_size && INTVAL (XEXP (x, 1)) > 5) + *total -= 2; + if (!optimize_size && INTVAL (XEXP (x, 1)) > 17) + *total -= 2; + } + else + /* Double the worst cost of shifts when there is no barrel shifter and + the shift amount is in a reg. */ + *total = COSTS_N_INSNS (32 * 4); + return true; + } + case PLUS: + case MINUS: + { + if (mode == SFmode || mode == DFmode) + { + if (TARGET_HARD_FLOAT) + *total = COSTS_N_INSNS (6); + return true; + } + else if (mode == DImode) + { + *total = COSTS_N_INSNS (4); + return true; + } + else + { + *total = COSTS_N_INSNS (1); + return true; + } + + return false; + } + case NEG: + { + if (mode == DImode) + *total = COSTS_N_INSNS (4); + + return false; + } + case MULT: + { + if (mode == SFmode) + { + if (TARGET_HARD_FLOAT) + *total = COSTS_N_INSNS (6); + } + else if (!TARGET_SOFT_MUL) + { + if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") + >= 0) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (3); + } + else + *total = COSTS_N_INSNS (10); + return true; + } + case DIV: + case UDIV: + { + if (mode == SFmode) + { + if (TARGET_HARD_FLOAT) + *total = COSTS_N_INSNS (23); + } + return false; + } + case SIGN_EXTEND: + { + *total = COSTS_N_INSNS (1); + return false; + } + case ZERO_EXTEND: + { + *total = COSTS_N_INSNS (1); + return false; + } + } + + return false; +} + +/* Return the number of instructions needed to load or store a value + of mode MODE at X. Return 0 if X isn't valid for MODE. */ + +static int +microblaze_address_insns (rtx x, enum machine_mode mode) +{ + struct microblaze_address_info addr; + + if (microblaze_classify_address (&addr, x, mode, false)) + { + switch (addr.type) + { + case ADDRESS_REG: + if (SMALL_INT (addr.offset)) + return 1; + else + return 2; + case ADDRESS_CONST_INT: + if (SMALL_INT (x)) + return 1; + else + return 2; + case ADDRESS_REG_INDEX: + case ADDRESS_SYMBOLIC: + return 1; + case ADDRESS_GOTOFF: + return 2; + default: + break; + } + } + return 0; +} + +/* Provide the costs of an addressing mode that contains ADDR. + If ADDR is not a valid address, its cost is irrelevant. */ +static int +microblaze_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) +{ + return COSTS_N_INSNS (microblaze_address_insns (addr, GET_MODE (addr))); +} + +/* Return nonzero if X is an address which needs a temporary register when + reloaded while generating PIC code. */ + +int +pic_address_needs_scratch (rtx x) +{ + /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && (flag_pic == 2 || !SMALL_INT (XEXP (XEXP (x, 0), 1)))) + return 1; + + return 0; +} + +/* Argument support functions. */ +/* Initialize CUMULATIVE_ARGS for a function. */ + +void +init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype, + rtx libname ATTRIBUTE_UNUSED) +{ + static CUMULATIVE_ARGS zero_cum; + tree param, next_param; + + *cum = zero_cum; + + /* Determine if this function has variable arguments. This is + indicated by the last argument being 'void_type_mode' if there + are no variable arguments. The standard MicroBlaze calling sequence + passes all arguments in the general purpose registers in this case. */ + + for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0; + param != 0; param = next_param) + { + next_param = TREE_CHAIN (param); + if (next_param == 0 && TREE_VALUE (param) != void_type_node) + cum->gp_reg_found = 1; + } +} + +/* Advance the argument to the next argument position. */ + +void +function_arg_advance (CUMULATIVE_ARGS * cum, enum machine_mode mode, + tree type, int named ATTRIBUTE_UNUSED) +{ + cum->arg_number++; + switch (mode) + { + case VOIDmode: + break; + + default: + gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT + || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT); + + cum->gp_reg_found = 1; + cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case BLKmode: + cum->gp_reg_found = 1; + cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case SFmode: + cum->arg_words++; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 1 << ((cum->arg_number - 1) * 2); + break; + + case DFmode: + cum->arg_words += 2; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case DImode: + cum->gp_reg_found = 1; + cum->arg_words += 2; + break; + + case QImode: + case HImode: + case SImode: + case TImode: + cum->gp_reg_found = 1; + cum->arg_words++; + break; + } +} + +/* Return an RTL expression containing the register for the given mode, + or 0 if the argument is to be passed on the stack. */ + +rtx +function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED) +{ + rtx ret; + int regbase = -1; + int *arg_words = &cum->arg_words; + + cum->last_arg_fp = 0; + switch (mode) + { + case SFmode: + case DFmode: + case VOIDmode: + case QImode: + case HImode: + case SImode: + case DImode: + case TImode: + regbase = GP_ARG_FIRST; + break; + default: + gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT + || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT); + /* Drops through. */ + case BLKmode: + regbase = GP_ARG_FIRST; + break; + } + + if (*arg_words >= MAX_ARGS_IN_REGISTERS) + ret = 0; + else + { + gcc_assert (regbase != -1); + + ret = gen_rtx_REG (mode, regbase + *arg_words); + } + + if (mode == VOIDmode) + { + if (cum->num_adjusts > 0) + ret = gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code, + gen_rtvec_v (cum->num_adjusts, cum->adjust)); + } + + return ret; +} + +/* Return number of bytes of argument to put in registers. */ +static int +function_arg_partial_bytes (CUMULATIVE_ARGS * cum, enum machine_mode mode, + tree type, bool named ATTRIBUTE_UNUSED) +{ + if ((mode == BLKmode + || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + && cum->arg_words < MAX_ARGS_IN_REGISTERS) + { + int words; + if (mode == BLKmode) + words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + else + words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS) + return 0; /* structure fits in registers */ + + return (MAX_ARGS_IN_REGISTERS - cum->arg_words) * UNITS_PER_WORD; + } + + else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS - 1) + return UNITS_PER_WORD; + + return 0; +} + +/* Convert a version number of the form "vX.YY.Z" to an integer encoding + for easier range comparison. */ +static int +microblaze_version_to_int (const char *version) +{ + const char *p, *v; + const char *tmpl = "vX.YY.Z"; + int iver = 0; + + p = version; + v = tmpl; + + while (*v) + { + if (*v == 'X') + { /* Looking for major */ + if (!(*p >= '0' && *p <= '9')) + return -1; + iver += (int) (*p - '0'); + iver *= 10; + } + else if (*v == 'Y') + { /* Looking for minor */ + if (!(*p >= '0' && *p <= '9')) + return -1; + iver += (int) (*p - '0'); + iver *= 10; + } + else if (*v == 'Z') + { /* Looking for compat */ + if (!(*p >= 'a' && *p <= 'z')) + return -1; + iver *= 10; + iver += (int) (*p - 'a'); + } + else + { + if (*p != *v) + return -1; + } + + v++; + p++; + } + + if (*p) + return -1; + + return iver; +} + +static bool +microblaze_handle_option (size_t code, + const char *arg ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED) +{ + switch (code) + { + case OPT_mno_clearbss: + flag_zero_initialized_in_bss = 0; + warning (0, "-mno-clearbss is deprecated; use -fno-zero-initialized-in-bss"); + break; + case OPT_mxl_stack_check: + warning (0, "-mxl_stack_check is deprecated; use -fstack-check."); + break; + } + return true; +} + + +static void +microblaze_option_override (void) +{ + register int i, start; + register int regno; + register enum machine_mode mode; + int ver; + + microblaze_section_threshold = (global_options_set.x_g_switch_value + ? g_switch_value + : MICROBLAZE_DEFAULT_GVALUE); + + /* Check the MicroBlaze CPU version for any special action to be done. */ + if (microblaze_select_cpu == NULL) + microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; + ver = microblaze_version_to_int (microblaze_select_cpu); + if (ver == -1) + { + error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu); + } + + ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); + if (ver < 0) + { + /* No hardware exceptions in earlier versions. So no worries. */ + // microblaze_select_flags &= ~(MICROBLAZE_MASK_NO_UNSAFE_DELAY); + microblaze_no_unsafe_delay = 0; + microblaze_pipe = MICROBLAZE_PIPE_3; + } + else if (ver == 0 + || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b") + == 0)) + { + // microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); + microblaze_no_unsafe_delay = 1; + microblaze_pipe = MICROBLAZE_PIPE_3; + } + else + { + /* We agree to use 5 pipe-stage model even on area optimized 3 + pipe-stage variants. */ + // microblaze_select_flags &= ~(MICROBLAZE_MASK_NO_UNSAFE_DELAY); + microblaze_no_unsafe_delay = 0; + microblaze_pipe = MICROBLAZE_PIPE_5; + if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0 + || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, + "v5.00.b") == 0 + || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, + "v5.00.c") == 0) + { + /* Pattern compares are to be turned on by default only when + compiling for MB v5.00.'z'. */ + target_flags |= MASK_PATTERN_COMPARE; + } + } + + ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a"); + if (ver < 0) + { + if (TARGET_MULTIPLY_HIGH) + warning (0, + "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater"); + } + + if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) + error ("-mxl-multiply-high requires -mno-xl-soft-mul"); + + /* Always use DFA scheduler. */ + microblaze_sched_use_dfa = 1; + + // microblaze_abicalls = MICROBLAZE_ABICALLS_NO; + + /* Initialize the high, low values for legit floating point constants. */ + real_maxval (&dfhigh, 0, DFmode); + real_maxval (&dflow, 1, DFmode); + real_maxval (&sfhigh, 0, SFmode); + real_maxval (&sflow, 1, SFmode); + + microblaze_print_operand_punct['?'] = 1; + microblaze_print_operand_punct['#'] = 1; + microblaze_print_operand_punct['&'] = 1; + microblaze_print_operand_punct['!'] = 1; + microblaze_print_operand_punct['*'] = 1; + microblaze_print_operand_punct['@'] = 1; + microblaze_print_operand_punct['.'] = 1; + microblaze_print_operand_punct['('] = 1; + microblaze_print_operand_punct[')'] = 1; + microblaze_print_operand_punct['['] = 1; + microblaze_print_operand_punct[']'] = 1; + microblaze_print_operand_punct['<'] = 1; + microblaze_print_operand_punct['>'] = 1; + microblaze_print_operand_punct['{'] = 1; + microblaze_print_operand_punct['}'] = 1; + microblaze_print_operand_punct['^'] = 1; + microblaze_print_operand_punct['$'] = 1; + microblaze_print_operand_punct['+'] = 1; + + /* Set up array to map GCC register number to debug register number. + Ignore the special purpose register numbers. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + microblaze_dbx_regno[i] = -1; + + start = GP_DBX_FIRST - GP_REG_FIRST; + for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) + microblaze_dbx_regno[i] = i + start; + + /* Set up array giving whether a given register can hold a given mode. */ + + for (mode = VOIDmode; + mode != MAX_MACHINE_MODE; mode = (enum machine_mode) ((int) mode + 1)) + { + register int size = GET_MODE_SIZE (mode); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + { + register int ok; + + if (mode == CCmode) + { + ok = (ST_REG_P (regno) || GP_REG_P (regno)); + } + else if (GP_REG_P (regno)) + ok = ((regno & 1) == 0 || size <= UNITS_PER_WORD); + else + ok = 0; + + microblaze_hard_regno_mode_ok[(int) mode][regno] = ok; + } + } +} + +/* Return true if FUNC is an interrupt function as specified + by the "interrupt_handler" attribute. */ + +static int +microblaze_interrupt_function_p (tree func) +{ + tree a; + + if (TREE_CODE (func) != FUNCTION_DECL) + return 0; + + a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); + return a != NULL_TREE; +} + +/* Return true if FUNC is an interrupt function which uses + normal return, indicated by the "save_volatiles" attribute. */ + +static int +microblaze_save_volatiles (tree func) +{ + tree a; + + if (TREE_CODE (func) != FUNCTION_DECL) + return 0; + + a = lookup_attribute ("save_volatiles", DECL_ATTRIBUTES (func)); + return a != NULL_TREE; +} + +/* Return whether function is tagged with 'interrupt_handler' + attribute. Return true if function should use return from + interrupt rather than normal function return. */ +int +microblaze_is_interrupt_handler (void) +{ + return interrupt_handler; +} + +/* Determine of register must be saved/restored in call. */ +static int +microblaze_must_save_register (int regno) +{ + if (pic_offset_table_rtx && + (regno == MB_ABI_PIC_ADDR_REGNUM) && df_regs_ever_live_p (regno)) + return 1; + + if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) + return 1; + + if (frame_pointer_needed && (regno == HARD_FRAME_POINTER_REGNUM)) + return 1; + + if (!current_function_is_leaf) + { + if (regno == MB_ABI_SUB_RETURN_ADDR_REGNUM) + return 1; + if ((interrupt_handler || save_volatiles) && + (regno >= 3 && regno <= 12)) + return 1; + } + + if (interrupt_handler) + { + if (df_regs_ever_live_p (regno) + || regno == MB_ABI_MSR_SAVE_REG + || regno == MB_ABI_ASM_TEMP_REGNUM + || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM) + return 1; + } + + if (save_volatiles) + { + if (df_regs_ever_live_p (regno) + || regno == MB_ABI_ASM_TEMP_REGNUM + || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM) + return 1; + } + + return 0; +} + +/* Return the bytes needed to compute the frame pointer from the current + stack pointer. + + MicroBlaze stack frames look like: + + + + Before call After call + +-----------------------+ +-----------------------+ + high | | | | + mem. | local variables, | | local variables, | + | callee saved and | | callee saved and | + | temps | | temps | + +-----------------------+ +-----------------------+ + | arguments for called | | arguments for called | + | subroutines | | subroutines | + | (optional) | | (optional) | + +-----------------------+ +-----------------------+ + | Link register | | Link register | + SP->| | | | + +-----------------------+ +-----------------------+ + | | + | local variables, | + | callee saved and | + | temps | + +-----------------------+ + | MSR (optional if, | + | interrupt handler) | + +-----------------------+ + | | + | alloca allocations | + | | + +-----------------------+ + | | + | arguments for called | + | subroutines | + | (optional) | + | | + +-----------------------+ + | Link register | + low FP,SP->| | + memory +-----------------------+ + +*/ + +static HOST_WIDE_INT +compute_frame_size (HOST_WIDE_INT size) +{ + int regno; + HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ + HOST_WIDE_INT var_size; /* # bytes that local variables take up. */ + HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up. */ + int link_debug_size; /* # bytes for link register. */ + HOST_WIDE_INT gp_reg_size; /* # bytes needed to store calle-saved gp regs. */ + long mask; /* mask of saved gp registers. */ + + interrupt_handler = + microblaze_interrupt_function_p (current_function_decl); + save_volatiles = microblaze_save_volatiles (current_function_decl); + + gp_reg_size = 0; + mask = 0; + var_size = size; + args_size = crtl->outgoing_args_size; + + if ((args_size == 0) && cfun->calls_alloca) + args_size = NUM_OF_ARGS * UNITS_PER_WORD; + + total_size = var_size + args_size; + + if (flag_pic == 2) + /* force setting GOT. */ + df_set_regs_ever_live (MB_ABI_PIC_ADDR_REGNUM, true); + + /* Calculate space needed for gp registers. */ + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + { + if (microblaze_must_save_register (regno)) + { + + if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't account for link register. It is accounted specially below. */ + gp_reg_size += GET_MODE_SIZE (SImode); + + mask |= (1L << (regno - GP_REG_FIRST)); + } + } + + total_size += gp_reg_size; + + /* Add 4 bytes for MSR. */ + if (interrupt_handler) + total_size += 4; + + /* No space to be allocated for link register in leaf functions with no other + stack requirements. */ + if (total_size == 0 && current_function_is_leaf) + link_debug_size = 0; + else + link_debug_size = UNITS_PER_WORD; + + total_size += link_debug_size; + + /* Save other computed information. */ + current_frame_info.total_size = total_size; + current_frame_info.var_size = var_size; + current_frame_info.args_size = args_size; + current_frame_info.gp_reg_size = gp_reg_size; + current_frame_info.mask = mask; + current_frame_info.initialized = reload_completed; + current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD; + current_frame_info.link_debug_size = link_debug_size; + + if (mask) + /* Offset from which to callee-save GP regs. */ + current_frame_info.gp_offset = (total_size - gp_reg_size); + else + current_frame_info.gp_offset = 0; + + /* Ok, we're done. */ + return total_size; +} + +/* Make sure that we're not trying to eliminate to the wrong hard frame + pointer. */ + +static bool +microblaze_can_eliminate (const int from, const int to) +{ + return ((from == RETURN_ADDRESS_POINTER_REGNUM && !leaf_function_p()) + || (to == MB_ABI_SUB_RETURN_ADDR_REGNUM && leaf_function_p()) + || (from != RETURN_ADDRESS_POINTER_REGNUM + && (to == HARD_FRAME_POINTER_REGNUM + || (to == STACK_POINTER_REGNUM && !frame_pointer_needed)))); +} + +/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame + pointer or argument pointer or the return address pointer. TO is either + the stack pointer or hard frame pointer. */ + +HOST_WIDE_INT +microblaze_initial_elimination_offset (int from, int to) +{ + HOST_WIDE_INT offset; + + switch (from) + { + case FRAME_POINTER_REGNUM: + offset = 0; + break; + case ARG_POINTER_REGNUM: + if (to == STACK_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM) + offset = compute_frame_size (get_frame_size ()); + else + gcc_unreachable (); + break; + case RETURN_ADDRESS_POINTER_REGNUM: + if (current_function_is_leaf) + offset = 0; + else + offset = current_frame_info.gp_offset + + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT))); + break; + default: + gcc_unreachable (); + } + return offset; +} + +/* Print operands using format code. + + The MicroBlaze specific codes are: + + 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", + 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", + 'F' op is CONST_DOUBLE, print 32 bits in hex, + 'd' output integer constant in decimal, + 'z' if the operand is 0, use $0 instead of normal operand. + 'D' print second register of double-word register operand. + 'L' print low-order register of double-word register operand. + 'M' print high-order register of double-word register operand. + 'C' print part of opcode for a branch condition. + 'N' print part of opcode for a branch condition, inverted. + 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch). + 'B' print 'z' for EQ, 'n' for NE + 'b' print 'n' for EQ, 'z' for NE + 'T' print 'f' for EQ, 't' for NE + 't' print 't' for EQ, 'f' for NE + 'm' Print 1<<operand. + 'i' Print 'i' if MEM operand has immediate value + 'o' Print operand address+4 + '?' Print 'd' if we use a branch with delay slot instead of normal branch. + 'h' Print high word of const_double (int or float) value as hex + 'j' Print low word of const_double (int or float) value as hex + 's' Print -1 if operand is negative, 0 if positive (sign extend) + '@' Print the name of the temporary register (rMB_ABI_ASM_TEMP_REGNUM). + '#' Print nop if the delay slot of a branch is not filled. +*/ + +void +print_operand (FILE * file, rtx op, int letter) +{ + register enum rtx_code code; + + if (PRINT_OPERAND_PUNCT_VALID_P (letter)) + { + switch (letter) + { + case '?': + /* Conditionally add a 'd' to indicate filled delay slot. */ + if (final_sequence != NULL) + fputs ("d", file); + break; + + case '#': + /* Conditionally add a nop in unfilled delay slot. */ + if (final_sequence == NULL) + fputs ("nop\t\t# Unfilled delay slot\n", file); + break; + + case '@': + fputs (reg_names[GP_REG_FIRST + MB_ABI_ASM_TEMP_REGNUM], file); + break; + + default: + output_operand_lossage ("unknown punctuation '%c'", letter); + break; + } + + return; + } + + if (!op) + { + output_operand_lossage ("null pointer"); + return; + } + + code = GET_CODE (op); + + if (code == SIGN_EXTEND) + op = XEXP (op, 0), code = GET_CODE (op); + + if (letter == 'C') + switch (code) + { + case EQ: + fputs ("eq", file); + break; + case NE: + fputs ("ne", file); + break; + case GT: + case GTU: + fputs ("gt", file); + break; + case GE: + case GEU: + fputs ("ge", file); + break; + case LT: + case LTU: + fputs ("lt", file); + break; + case LE: + case LEU: + fputs ("le", file); + break; + default: + fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op); + } + + else if (letter == 'N') + switch (code) + { + case EQ: + fputs ("ne", file); + break; + case NE: + fputs ("eq", file); + break; + case GT: + case GTU: + fputs ("le", file); + break; + case GE: + case GEU: + fputs ("lt", file); + break; + case LT: + case LTU: + fputs ("ge", file); + break; + case LE: + case LEU: + fputs ("gt", file); + break; + default: + fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op); + } + + else if (letter == 'S') + { + char buffer[100]; + + ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op)); + assemble_name (file, buffer); + } + + /* Print 'i' for memory operands which have immediate values. */ + else if (letter == 'i') + { + if (code == MEM) + { + struct microblaze_address_info info; + + if (!microblaze_classify_address + (&info, XEXP (op, 0), GET_MODE (op), 1)) + fatal_insn ("insn contains an invalid address !", op); + + switch (info.type) + { + case ADDRESS_REG: + case ADDRESS_CONST_INT: + case ADDRESS_SYMBOLIC: + case ADDRESS_GOTOFF: + fputs ("i", file); + break; + case ADDRESS_REG_INDEX: + break; + case ADDRESS_INVALID: + case ADDRESS_PLT: + fatal_insn ("Invalid address", op); + } + } + } + + else if (code == REG || code == SUBREG) + { + register int regnum; + + if (code == REG) + regnum = REGNO (op); + else + regnum = true_regnum (op); + + if ((letter == 'M' && !WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') + regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } + + else if (code == MEM) + if (letter == 'o') + { + rtx op4 = adjust_address (op, GET_MODE (op), 4); + output_address (XEXP (op4, 0)); + } + else + output_address (XEXP (op, 0)); + + else if (letter == 'h' || letter == 'j') + { + long val[2]; + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) + { + REAL_VALUE_TYPE value; + REAL_VALUE_FROM_CONST_DOUBLE (value, op); + REAL_VALUE_TO_TARGET_DOUBLE (value, val); + } + else + { + val[0] = CONST_DOUBLE_HIGH (op); + val[1] = CONST_DOUBLE_LOW (op); + } + } + else if (code == CONST_INT) + { + val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; + val[1] = INTVAL (op) & 0x00000000ffffffffLL; + if (val[0] == 0 && val[1] < 0) + val[0] = -1; + + } + fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } + else if (code == CONST_DOUBLE) + { + if (letter == 'F') + { + unsigned long value_long; + REAL_VALUE_TYPE value; + REAL_VALUE_FROM_CONST_DOUBLE (value, op); + REAL_VALUE_TO_TARGET_SINGLE (value, value_long); + fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); + } + else + { + char s[60]; + real_to_decimal (s, CONST_DOUBLE_REAL_VALUE (op), sizeof (s), 0, 1); + fputs (s, file); + } + } + + else if (code == UNSPEC) + { + print_operand_address (file, op); + } + + else if (letter == 'x' && GET_CODE (op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL (op)); + + else if (letter == 'X' && GET_CODE (op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); + + else if (letter == 'd' && GET_CODE (op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL (op))); + + else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0) + fputs (reg_names[GP_REG_FIRST], file); + + else if (letter == 's' && GET_CODE (op) == CONST_INT) + if (INTVAL (op) < 0) + fputs ("-1", file); + else + fputs ("0", file); + + else if (letter == 'd' || letter == 'x' || letter == 'X' || letter == 's') + output_operand_lossage ("letter %c was found & insn was not CONST_INT", letter); + + else if (letter == 'B') + fputs (code == EQ ? "z" : "n", file); + else if (letter == 'b') + fputs (code == EQ ? "n" : "z", file); + else if (letter == 'T') + fputs (code == EQ ? "f" : "t", file); + else if (letter == 't') + fputs (code == EQ ? "t" : "f", file); + + else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG) + { + print_operand (file, XEXP (op, 0), letter); + } + else if (letter == 'm') + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); + else + output_addr_const (file, op); +} + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + Possible address classifications and output formats are, + + ADDRESS_REG "%0, r0" + + ADDRESS_REG with non-zero "%0, <addr_const>" + offset + + ADDRESS_REG_INDEX "rA, RB" + (if rA is r0, rA and rB are swapped) + + ADDRESS_CONST_INT "r0, <addr_const>" + + ADDRESS_SYMBOLIC "rBase, <addr_const>" + (rBase is a base register suitable for the + symbol's type) +*/ + +void +print_operand_address (FILE * file, rtx addr) +{ + struct microblaze_address_info info; + enum microblaze_address_type type; + if (!microblaze_classify_address (&info, addr, GET_MODE (addr), 1)) + fatal_insn ("insn contains an invalid address !", addr); + + type = info.type; + switch (info.type) + { + case ADDRESS_REG: + fprintf (file, "%s,", reg_names[REGNO (info.regA)]); + output_addr_const (file, info.offset); + break; + case ADDRESS_REG_INDEX: + if (REGNO (info.regA) == 0) + /* Make rB == r0 instead of rA == r0. This helps reduce read port + congestion. */ + fprintf (file, "%s,%s", reg_names[REGNO (info.regB)], + reg_names[REGNO (info.regA)]); + else if (REGNO (info.regB) != 0) + /* This is a silly swap to help Dhrystone. */ + fprintf (file, "%s,%s", reg_names[REGNO (info.regB)], + reg_names[REGNO (info.regA)]); + break; + case ADDRESS_CONST_INT: + fprintf (file, "%s,", reg_names[REGNO (info.regA)]); + output_addr_const (file, info.offset); + break; + case ADDRESS_SYMBOLIC: + case ADDRESS_GOTOFF: + case ADDRESS_PLT: + if (info.regA) + fprintf (file, "%s,", reg_names[REGNO (info.regA)]); + output_addr_const (file, info.symbol); + if (type == ADDRESS_GOTOFF) + { + fputs ("@GOT", file); + } + else if (type == ADDRESS_PLT) + { + fputs ("@PLT", file); + } + break; + case ADDRESS_INVALID: + fatal_insn ("invalid address", addr); + break; + } +} + +/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol + is used, so that we don't emit an .extern for it in + microblaze_asm_file_end. */ + +void +microblaze_declare_object (FILE * stream, const char *name, + const char *section, const char *fmt, int size) +{ + + fputs (section, stream); + assemble_name (stream, name); + fprintf (stream, fmt, size); +} + +/* Common code to emit the insns (or to write the instructions to a file) + to save/restore registers. + + Other parts of the code assume that MICROBLAZE_TEMP1_REGNUM (aka large_reg) + is not modified within save_restore_insns. */ + +#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0) + +/* Save or restore instructions based on whether this is the prologue or + epilogue. prologue is 1 for the prologue. */ +static void +save_restore_insns (int prologue) +{ + rtx base_reg_rtx, reg_rtx, mem_rtx, /* msr_rtx, */ isr_reg_rtx = + 0, isr_mem_rtx = 0; + rtx isr_msr_rtx = 0, insn; + long mask = current_frame_info.mask; + HOST_WIDE_INT base_offset, gp_offset; + int regno; + + if (frame_pointer_needed + && !BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST)) + gcc_unreachable (); + + if (mask == 0) + return; + + /* Save registers starting from high to low. The debuggers prefer at least + the return register be stored at func+4, and also it allows us not to + need a nop in the epilog if at least one register is reloaded in + addition to return address. */ + + /* Pick which pointer to use as a base register. For small frames, just + use the stack pointer. Otherwise, use a temporary register. Save 2 + cycles if the save area is near the end of a large frame, by reusing + the constant created in the prologue/epilogue to adjust the stack + frame. */ + + gp_offset = current_frame_info.gp_offset; + + gcc_assert (gp_offset > 0); + + base_reg_rtx = stack_pointer_rtx; + base_offset = 0; + + /* For interrupt_handlers, need to save/restore the MSR. */ + if (interrupt_handler) + { + isr_mem_rtx = gen_rtx_MEM (SImode, + gen_rtx_PLUS (Pmode, base_reg_rtx, + GEN_INT (current_frame_info. + gp_offset - + UNITS_PER_WORD))); + + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (isr_mem_rtx) = 1; + isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); + isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); + } + + if (interrupt_handler && !prologue) + { + emit_move_insn (isr_reg_rtx, isr_mem_rtx); + emit_move_insn (isr_msr_rtx, isr_reg_rtx); + /* Do not optimize in flow analysis. */ + emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); + emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); + } + + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + { + if (BITSET_P (mask, regno - GP_REG_FIRST)) + { + if (regno == MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't handle here. Already handled as the first register. */ + continue; + + reg_rtx = gen_rtx_REG (SImode, regno); + insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); + mem_rtx = gen_rtx_MEM (SImode, insn); + if (interrupt_handler || save_volatiles) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + + if (prologue) + { + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (reg_rtx, mem_rtx); + } + + gp_offset += GET_MODE_SIZE (SImode); + } + } + + if (interrupt_handler && prologue) + { + emit_move_insn (isr_reg_rtx, isr_msr_rtx); + emit_move_insn (isr_mem_rtx, isr_reg_rtx); + + /* Do not optimize in flow analysis. */ + emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); + emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); + } + + /* Done saving and restoring */ +} + + +/* Set up the stack and frame (if desired) for the function. */ +static void +microblaze_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) +{ + const char *fnname; + long fsiz = current_frame_info.total_size; + + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + if (!flag_inhibit_size_directive) + { + fputs ("\t.ent\t", file); + if (interrupt_handler && strcmp (INTERRUPT_HANDLER_NAME, fnname)) + fputs ("_interrupt_handler", file); + else + assemble_name (file, fnname); + fputs ("\n", file); + if (!interrupt_handler) + ASM_OUTPUT_TYPE_DIRECTIVE (file, fnname, "function"); + } + + assemble_name (file, fnname); + fputs (":\n", file); + + if (interrupt_handler && strcmp (INTERRUPT_HANDLER_NAME, fnname)) + fputs ("_interrupt_handler:\n", file); + + if (!flag_inhibit_size_directive) + { + /* .frame FRAMEREG, FRAMESIZE, RETREG. */ + fprintf (file, + "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d, args= %d\n", + (reg_names[(frame_pointer_needed) + ? HARD_FRAME_POINTER_REGNUM : + STACK_POINTER_REGNUM]), fsiz, + reg_names[MB_ABI_SUB_RETURN_ADDR_REGNUM + GP_REG_FIRST], + current_frame_info.var_size, current_frame_info.num_gp, + crtl->outgoing_args_size); + fprintf (file, "\t.mask\t0x%08lx\n", current_frame_info.mask); + } +} + +/* Output extra assembler code at the end of a prologue. */ +static void +microblaze_function_end_prologue (FILE * file) +{ + if (TARGET_STACK_CHECK) + { + fprintf (file, "\t# Stack Check Stub -- Start.\n\t"); + fprintf (file, "ori\tr18,r0,_stack_end\n\t"); + fprintf (file, "cmpu\tr18,r1,r18\n\t"); + fprintf (file, "bgei\tr18,_stack_overflow_exit\n\t"); + fprintf (file, "# Stack Check Stub -- End.\n"); + } +} + +/* Expand the prologue into a bunch of separate insns. */ + +void +microblaze_expand_prologue (void) +{ + int regno; + HOST_WIDE_INT fsiz; + const char *arg_name = 0; + tree fndecl = current_function_decl; + tree fntype = TREE_TYPE (fndecl); + tree fnargs = DECL_ARGUMENTS (fndecl); + rtx next_arg_reg; + int i; + tree next_arg; + tree cur_arg; + CUMULATIVE_ARGS args_so_far; + rtx mem_rtx, reg_rtx; + + /* If struct value address is treated as the first argument, make it so. */ + if (aggregate_value_p (DECL_RESULT (fndecl), fntype) + && !cfun->returns_pcc_struct) + { + tree type = build_pointer_type (fntype); + tree function_result_decl = build_decl (BUILTINS_LOCATION, PARM_DECL, + NULL_TREE, type); + + DECL_ARG_TYPE (function_result_decl) = type; + TREE_CHAIN (function_result_decl) = fnargs; + fnargs = function_result_decl; + } + + /* Determine the last argument, and get its name. */ + + INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0, 0); + regno = GP_ARG_FIRST; + + for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg) + { + tree passed_type = DECL_ARG_TYPE (cur_arg); + enum machine_mode passed_mode = TYPE_MODE (passed_type); + rtx entry_parm; + + if (TREE_ADDRESSABLE (passed_type)) + { + passed_type = build_pointer_type (passed_type); + passed_mode = Pmode; + } + + entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1); + + if (entry_parm) + { + int words; + + /* passed in a register, so will get homed automatically. */ + if (GET_MODE (entry_parm) == BLKmode) + words = (int_size_in_bytes (passed_type) + 3) / 4; + else + words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4; + + regno = REGNO (entry_parm) + words - 1; + } + else + { + regno = GP_ARG_LAST + 1; + break; + } + + FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1); + + next_arg = TREE_CHAIN (cur_arg); + if (next_arg == 0) + { + if (DECL_NAME (cur_arg)) + arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg)); + + break; + } + } + + /* Split parallel insn into a sequence of insns. */ + + next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1); + if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL) + { + rtvec adjust = XVEC (next_arg_reg, 0); + int num = GET_NUM_ELEM (adjust); + + for (i = 0; i < num; i++) + { + rtx pattern = RTVEC_ELT (adjust, i); + emit_insn (pattern); + } + } + + fsiz = compute_frame_size (get_frame_size ()); + + /* If this function is a varargs function, store any registers that + would normally hold arguments ($5 - $10) on the stack. */ + if (((TYPE_ARG_TYPES (fntype) != 0 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) + != void_type_node)) + || (arg_name != 0 + && ((arg_name[0] == '_' + && strcmp (arg_name, "__builtin_va_alist") == 0) + || (arg_name[0] == 'v' + && strcmp (arg_name, "va_alist") == 0))))) + { + int offset = (regno - GP_ARG_FIRST + 1) * UNITS_PER_WORD; + rtx ptr = stack_pointer_rtx; + + /* If we are doing svr4-abi, sp has already been decremented by fsiz. */ + for (; regno <= GP_ARG_LAST; regno++) + { + if (offset != 0) + ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); + emit_move_insn (gen_rtx_MEM (SImode, ptr), + gen_rtx_REG (SImode, regno)); + + offset += GET_MODE_SIZE (SImode); + } + + } + + if (fsiz > 0) + { + rtx fsiz_rtx = GEN_INT (fsiz); + + rtx insn = NULL; + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, + fsiz_rtx)); + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + + /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ + if (!current_function_is_leaf || interrupt_handler) + { + mem_rtx = gen_rtx_MEM (SImode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + + reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* _save_ registers for prologue. */ + save_restore_insns (1); + + if (frame_pointer_needed) + { + rtx insn = 0; + + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + } + } + + if (flag_pic == 2 && df_regs_ever_live_p (MB_ABI_PIC_ADDR_REGNUM)) + { + rtx insn; + SET_REGNO (pic_offset_table_rtx, MB_ABI_PIC_ADDR_REGNUM); + insn = emit_insn (gen_set_got (pic_offset_table_rtx)); /* setting GOT. */ + } + + /* If we are profiling, make sure no instructions are scheduled before + the call to mcount. */ + + if (profile_flag) + emit_insn (gen_blockage ()); +} + +/* Do necessary cleanup after a function to restore stack, frame, and regs. */ + +#define RA_MASK ((long) 0x80000000) /* 1 << 31 */ +#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + +static void +microblaze_function_epilogue (FILE * file ATTRIBUTE_UNUSED, + HOST_WIDE_INT size ATTRIBUTE_UNUSED) +{ + const char *fnname; + + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + if (!flag_inhibit_size_directive) + { + fputs ("\t.end\t", file); + if (interrupt_handler) + fputs ("_interrupt_handler", file); + else + assemble_name (file, fnname); + fputs ("\n", file); + } + + /* Reset state info for each function. */ + current_frame_info = zero_frame_info; + + /* Restore the output file if optimizing the GP (optimizing the GP causes + the text to be diverted to a tempfile, so that data decls come before + references to the data). */ +} + +/* Expand the epilogue into a bunch of separate insns. */ + +void +microblaze_expand_epilogue (void) +{ + HOST_WIDE_INT fsiz = current_frame_info.total_size; + rtx fsiz_rtx = GEN_INT (fsiz); + rtx reg_rtx; + rtx mem_rtx; + + /* In case of interrupt handlers use addki instead of addi for changing the + stack pointer value. */ + + if (microblaze_can_use_return_insn ()) + { + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, + GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + return; + } + + if (fsiz > 0) + { + /* Restore SUB_RETURN_ADDR_REGNUM at first. This is to prevent the + sequence of load-followed by a use (in rtsd) in every prologue. Saves + a load-use stall cycle :) This is also important to handle alloca. + (See comments for if (frame_pointer_needed) below. */ + + if (!current_function_is_leaf || interrupt_handler) + { + mem_rtx = + gen_rtx_MEM (SImode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + emit_move_insn (reg_rtx, mem_rtx); + } + + /* It is important that this is done after we restore the return address + register (above). When alloca is used, we want to restore the + sub-routine return address only from the current stack top and not + from the frame pointer (which we restore below). (frame_pointer + 0) + might have been over-written since alloca allocates memory on the + current stack. */ + if (frame_pointer_needed) + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + + /* _restore_ registers for epilogue. */ + save_restore_insns (0); + emit_insn (gen_blockage ()); + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); + } + + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); +} + + +/* Return nonzero if this function is known to have a null epilogue. + This allows the optimizer to omit jumps to jumps if no stack + was created. */ + +int +microblaze_can_use_return_insn (void) +{ + if (!reload_completed) + return 0; + + if (df_regs_ever_live_p (MB_ABI_SUB_RETURN_ADDR_REGNUM) || profile_flag) + return 0; + + if (current_frame_info.initialized) + return current_frame_info.total_size == 0; + + return compute_frame_size (get_frame_size ()) == 0; +} + +/* Implement TARGET_SECONDARY_RELOAD. */ + +static enum reg_class +microblaze_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED, + enum reg_class rclass, enum machine_mode mode ATTRIBUTE_UNUSED, + secondary_reload_info *sri ATTRIBUTE_UNUSED) +{ + if (rclass == ST_REGS) + return GR_REGS; + + return NO_REGS; +} + +static void +microblaze_globalize_label (FILE * stream, const char *name) +{ + fputs ("\t.globl\t", stream); + if (interrupt_handler && strcmp (name, INTERRUPT_HANDLER_NAME)) + { + fputs (INTERRUPT_HANDLER_NAME, stream); + fputs ("\n\t.globl\t", stream); + } + assemble_name (stream, name); + fputs ("\n", stream); +} + +/* Returns true if decl should be placed into a "small data" section. */ +static bool +microblaze_elf_in_small_data_p (const_tree decl) +{ + if (!TARGET_XLGPOPT) + return false; + + /* We want to merge strings, so we never consider them small data. */ + if (TREE_CODE (decl) == STRING_CST) + return false; + + /* Functions are never in the small data area. */ + if (TREE_CODE (decl) == FUNCTION_DECL) + return false; + + if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) + { + const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); + if (strcmp (section, ".sdata") == 0 + || strcmp (section, ".sdata2") == 0 + || strcmp (section, ".sbss") == 0 + || strcmp (section, ".sbss2") == 0) + return true; + } + + HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); + + return (size > 0 && size <= microblaze_section_threshold); +} + + +static section * +microblaze_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) +{ + switch (categorize_decl_for_section (decl, reloc)) + { + case SECCAT_RODATA_MERGE_STR: + case SECCAT_RODATA_MERGE_STR_INIT: + /* MB binutils have various issues with mergeable string sections and + relaxation/relocation. Currently, turning mergeable sections + into regular readonly sections. */ + + return readonly_data_section; + default: + return default_elf_select_section (decl, reloc, align); + } +} + +/* + Encode info about sections into the RTL based on a symbol's declaration. + The default definition of this hook, default_encode_section_info in + `varasm.c', sets a number of commonly-useful bits in SYMBOL_REF_FLAGS. */ + +static void +microblaze_encode_section_info (tree decl, rtx rtl, int first) +{ + default_encode_section_info (decl, rtl, first); +} + +static rtx +expand_pic_symbol_ref (enum machine_mode mode ATTRIBUTE_UNUSED, rtx op) +{ + rtx result; + result = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), UNSPEC_GOTOFF); + result = gen_rtx_CONST (Pmode, result); + result = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, result); + result = gen_const_mem (Pmode, result); + return result; +} + +bool +microblaze_expand_move (enum machine_mode mode, rtx operands[]) +{ + /* If operands[1] is a constant address invalid for pic, then we need to + handle it just like LEGITIMIZE_ADDRESS does. */ + if (flag_pic) + { + if (GET_CODE (operands[0]) == MEM) + { + rtx addr = XEXP (operands[0], 0); + if (GET_CODE (addr) == SYMBOL_REF) + { + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + + rtx ptr_reg, result; + + addr = expand_pic_symbol_ref (mode, addr); + ptr_reg = gen_reg_rtx (Pmode); + emit_move_insn (ptr_reg, addr); + result = gen_rtx_MEM (mode, ptr_reg); + operands[0] = result; + } + } + if (GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == LABEL_REF) + { + rtx result; + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + result = expand_pic_symbol_ref (mode, operands[1]); + if (GET_CODE (operands[0]) != REG) + { + rtx ptr_reg = gen_reg_rtx (Pmode); + emit_move_insn (ptr_reg, result); + emit_move_insn (operands[0], ptr_reg); + } + else + { + emit_move_insn (operands[0], result); + } + return true; + } + else if (GET_CODE (operands[1]) == MEM && + GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) + { + rtx result; + rtx ptr_reg; + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + result = expand_pic_symbol_ref (mode, XEXP (operands[1], 0)); + + ptr_reg = gen_reg_rtx (Pmode); + + emit_move_insn (ptr_reg, result); + result = gen_rtx_MEM (mode, ptr_reg); + emit_move_insn (operands[0], result); + return true; + } + else if (pic_address_needs_scratch (operands[1])) + { + rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + + if (reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); + emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2)); + return true; + } + } + + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], SImode) + && !register_operand (operands[1], SImode) + && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)) + { + rtx temp = force_reg (SImode, operands[1]); + emit_move_insn (operands[0], temp); + return true; + } + return false; +} + +/* Expand shift operations. */ +int +microblaze_expand_shift (rtx operands[]) +{ + gcc_assert ((GET_CODE (operands[2]) == CONST_INT) + || (GET_CODE (operands[2]) == REG) + || (GET_CODE (operands[2]) == SUBREG)); + + /* Shift by one -- generate pattern. */ + if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 1)) + return 0; + + /* Have barrel shifter and shift > 1: use it. */ + if (TARGET_BARREL_SHIFT) + return 0; + + gcc_assert ((GET_CODE (operands[0]) == REG) + || (GET_CODE (operands[0]) == SUBREG) + || (GET_CODE (operands[1]) == REG) + || (GET_CODE (operands[1]) == SUBREG)); + + /* Shift by zero -- copy regs if necessary. */ + if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 0)) + { + if (REGNO (operands[0]) != REGNO (operands[1])) + emit_insn (gen_movsi (operands[0], operands[1])); + return 1; + } + + return 0; +} + +/* Return an RTX indicating where the return address to the + calling function can be found. */ +rtx +microblaze_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) +{ + if (count != 0) + return NULL_RTX; + + return gen_rtx_PLUS (Pmode, + get_hard_reg_initial_val (Pmode, + MB_ABI_SUB_RETURN_ADDR_REGNUM), + GEN_INT (8)); +} + +/* Put string into .sdata2 if below threashold. */ +void +microblaze_asm_output_ident (FILE *file ATTRIBUTE_UNUSED, const char *string) +{ + int size = strlen (string) + 1; + if (size <= microblaze_section_threshold) + switch_to_section (sdata2_section); + else + switch_to_section (readonly_data_section); + assemble_string (string, size); +} + +static void +microblaze_elf_asm_init_sections (void) +{ + sdata2_section + = get_unnamed_section (SECTION_WRITE, output_section_asm_op, + SDATA2_SECTION_ASM_OP); +} + +/* Generate assembler code for constant parts of a trampoline. */ + +static void +microblaze_asm_trampoline_template (FILE *f) +{ + fprintf (f, "\t.word\t0x03e00821\t\t# move $1,$31\n"); + fprintf (f, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); + fprintf (f, "\t.word\t0x00000000\t\t# nop\n"); + fprintf (f, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); + fprintf (f, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); + fprintf (f, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); + fprintf (f, "\t.word\t0x00600008\t\t# jr $3\n"); + fprintf (f, "\t.word\t0x0020f821\t\t# move $31,$1\n"); + /* fprintf (f, "\t.word\t0x00000000\t\t# <function address>\n"); */ + /* fprintf (f, "\t.word\t0x00000000\t\t# <static chain value>\n"); */ +} + +/* Implement TARGET_TRAMPOLINE_INIT. */ + +static void +microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) +{ + rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); + rtx mem; + + emit_block_move (m_tramp, assemble_trampoline_template (), + GEN_INT (8*UNITS_PER_WORD), BLOCK_OP_NORMAL); + + mem = adjust_address (m_tramp, SImode, 8); + emit_move_insn (mem, chain_value); + mem = adjust_address (m_tramp, SImode, 12); + emit_move_insn (mem, fnaddr); +} + +/* Emit instruction to perform compare. + cmp is (compare_op op0 op1). */ +static rtx +microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code) +{ + rtx cmp_op0 = XEXP (cmp, 0); + rtx cmp_op1 = XEXP (cmp, 1); + rtx comp_reg = gen_reg_rtx (SImode); + enum rtx_code code = *cmp_code; + + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); + + /* If comparing against zero, just test source reg. */ + if (cmp_op1 == const0_rtx) + return cmp_op0; + + if (code == EQ || code == NE) + { + if (TARGET_PATTERN_COMPARE && GET_CODE(cmp_op1) == REG) + { + if (code == EQ) + emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, cmp_op1)); + else + { + emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, cmp_op1)); + *cmp_code = EQ; + } + } + else + /* Use xor for equal/not-equal comparison. */ + emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); + } + else if (code == GT || code == GTU || code == LE || code == LEU) + { + /* MicroBlaze compare is not symmetrical. */ + /* Swap argument order. */ + cmp_op1 = force_reg (mode, cmp_op1); + if (code == GT || code == LE) + emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1)); + else + emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1)); + /* Translate test condition. */ + *cmp_code = swap_condition (code); + } + else /* if (code == GE || code == GEU || code == LT || code == LTU) */ + { + cmp_op1 = force_reg (mode, cmp_op1); + if (code == GE || code == LT) + emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0)); + else + emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0)); + } + + return comp_reg; +} + +/* Generate conditional branch -- first, generate test condition, + second, generate correct branch instruction. */ + +void +microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[]) +{ + enum rtx_code code = GET_CODE (operands[0]); + rtx comp; + rtx condition; + + comp = microblaze_emit_compare (mode, operands[0], &code); + condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); +} + +void +microblaze_expand_conditional_branch_sf (rtx operands[]) +{ + rtx condition; + rtx cmp_op0 = XEXP (operands[0], 0); + rtx cmp_op1 = XEXP (operands[0], 1); + rtx comp_reg = gen_reg_rtx (SImode); + + emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); + condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); +} + +/* Implement TARGET_FRAME_POINTER_REQUIRED. */ + +static bool +microblaze_frame_pointer_required (void) +{ + /* If the function contains dynamic stack allocations, we need to + use the frame pointer to access the static parts of the frame. */ + if (cfun->calls_alloca) + return true; + return false; +} + +void +microblaze_expand_divide (rtx operands[]) +{ + /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ + + rtx regt1 = gen_reg_rtx (SImode); + rtx reg18 = gen_rtx_REG (SImode, R_TMP); + rtx regqi = gen_reg_rtx (QImode); + rtx div_label = gen_label_rtx (); + rtx div_end_label = gen_label_rtx (); + rtx div_table_rtx = gen_rtx_SYMBOL_REF (QImode,"_divsi3_table"); + rtx mem_rtx; + rtx ret; + rtx jump, cjump, insn; + + insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); + cjump = emit_jump_insn_after (gen_cbranchsi4 ( + gen_rtx_GTU (SImode, regt1, GEN_INT (15)), + regt1, GEN_INT (15), div_label), insn); + LABEL_NUSES (div_label) = 1; + JUMP_LABEL (cjump) = div_label; + emit_insn (gen_rtx_CLOBBER (SImode, reg18)); + + emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_addsi3 (regt1, regt1, operands[2])); + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); + + insn = emit_insn (gen_movqi (regqi, mem_rtx)); + insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; + emit_barrier (); + + emit_label (div_label); + ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, "__divsi3"), + operands[0], LCT_NORMAL, + GET_MODE (operands[0]), 2, operands[1], + GET_MODE (operands[1]), operands[2], + GET_MODE (operands[2])); + if (ret != operands[0]) + emit_move_insn (operands[0], ret); + + emit_label (div_end_label); + emit_insn (gen_blockage ()); +} + +/* Implement TARGET_FUNCTION_VALUE. */ +static rtx +microblaze_function_value (const_tree valtype, + const_tree func ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) +{ + return LIBCALL_VALUE (TYPE_MODE (valtype)); +} + +/* Implement TARGET_SCHED_ADJUST_COST. */ +static int +microblaze_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, + rtx dep ATTRIBUTE_UNUSED, int cost) +{ + if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) + return cost; + if (REG_NOTE_KIND (link) != 0) + return 0; + return cost; +} + +#undef TARGET_ENCODE_SECTION_INFO +#define TARGET_ENCODE_SECTION_INFO microblaze_encode_section_info + +#undef TARGET_ASM_GLOBALIZE_LABEL +#define TARGET_ASM_GLOBALIZE_LABEL microblaze_globalize_label + +#undef TARGET_ASM_FUNCTION_PROLOGUE +#define TARGET_ASM_FUNCTION_PROLOGUE microblaze_function_prologue + +#undef TARGET_ASM_FUNCTION_EPILOGUE +#define TARGET_ASM_FUNCTION_EPILOGUE microblaze_function_epilogue + +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS microblaze_rtx_costs + +#undef TARGET_ADDRESS_COST +#define TARGET_ADDRESS_COST microblaze_address_cost + +#undef TARGET_ATTRIBUTE_TABLE +#define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table + +#undef TARGET_IN_SMALL_DATA_P +#define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p + +#undef TARGET_ASM_SELECT_SECTION +#define TARGET_ASM_SELECT_SECTION microblaze_select_section + +#undef TARGET_HAVE_SRODATA_SECTION +#define TARGET_HAVE_SRODATA_SECTION true + +#undef TARGET_ASM_FUNCTION_END_PROLOGUE +#define TARGET_ASM_FUNCTION_END_PROLOGUE \ + microblaze_function_end_prologue + +#undef TARGET_HANDLE_OPTION +#define TARGET_HANDLE_OPTION microblaze_handle_option + +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + +#undef TARGET_ARG_PARTIAL_BYTES +#define TARGET_ARG_PARTIAL_BYTES function_arg_partial_bytes + +#undef TARGET_CAN_ELIMINATE +#define TARGET_CAN_ELIMINATE microblaze_can_eliminate + +#undef TARGET_LEGITIMIZE_ADDRESS +#define TARGET_LEGITIMIZE_ADDRESS microblaze_legitimize_address + +#undef TARGET_LEGITIMATE_ADDRESS_P +#define TARGET_LEGITIMATE_ADDRESS_P microblaze_legitimate_address_p + +#undef TARGET_FRAME_POINTER_REQUIRED +#define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required + +#undef TARGET_ASM_TRAMPOLINE_TEMPLATE +#define TARGET_ASM_TRAMPOLINE_TEMPLATE microblaze_asm_trampoline_template + +#undef TARGET_TRAMPOLINE_INIT +#define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init + +#undef TARGET_PROMOTE_FUNCTION_MODE +#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote + +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE microblaze_function_value + +#undef TARGET_SECONDARY_RELOAD +#define TARGET_SECONDARY_RELOAD microblaze_secondary_reload + +#undef TARGET_SCHED_ADJUST_COST +#define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost + +#undef TARGET_ASM_INIT_SECTIONS +#define TARGET_ASM_INIT_SECTIONS microblaze_elf_asm_init_sections + +#undef TARGET_OPTION_OVERRIDE +#define TARGET_OPTION_OVERRIDE microblaze_option_override + +struct gcc_target targetm = TARGET_INITIALIZER; + +#include "gt-microblaze.h" diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h new file mode 100644 index 00000000000..c7bf756034b --- /dev/null +++ b/gcc/config/microblaze/microblaze.h @@ -0,0 +1,952 @@ +/* Definitions of target machine for GNU compiler for Xilinx MicroBlaze. + Copyright 2009, 2010 Free Software Foundation, Inc. + + Contributed by Michael Eager <eager@eagercon.com>. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +/* Standard GCC variables that we reference. */ + +/* MicroBlaze external variables defined in microblaze.c. */ + +/* Which pipeline to schedule for. */ +enum pipeline_type +{ + MICROBLAZE_PIPE_3 = 0, + MICROBLAZE_PIPE_5 = 1 +}; + +#define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 + +/* print_operand punctuation chars */ +extern char microblaze_print_operand_punct[]; + +/* # bytes of data/sdata cutoff */ +extern int microblaze_section_threshold; + +/* Map register # to debug register # */ +extern int microblaze_dbx_regno[]; + +extern int microblaze_no_unsafe_delay; +extern enum pipeline_type microblaze_pipe; + +#define OBJECT_FORMAT_ELF + +/* Default target_flags if no switches are specified */ +#define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT) + +/* What is the default setting for -mcpu= . We set it to v4.00.a even though + we are actually ahead. This is safest version that has generate code + compatible for the original ISA */ +#define MICROBLAZE_DEFAULT_CPU "v4.00.a" + +/* Macros to decide whether certain features are available or not, + depending on the instruction set architecture level. */ + +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') + +/* We can debug without having a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP + +#define DRIVER_SELF_SPECS \ + "%{mxl-soft-mul:%<mno-xl-soft-mul}", \ + "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \ + "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \ + "%{mxl-soft-div:%<mno-xl-soft-div}", \ + "%{msoft-float:%<mhard-float}" + +/* Tell collect what flags to pass to nm. */ +#ifndef NM_FLAGS +#define NM_FLAGS "-Bn" +#endif + +/* Names to predefine in the preprocessor for this target machine. */ +#define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile) + +/* Assembler specs. */ + +#define TARGET_ASM_SPEC "%{v}" + +#define ASM_SPEC "\ +%{microblaze1} \ +%(target_asm_spec)" + +/* Extra switches sometimes passed to the linker. */ +/* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */ + +#define LINK_SPEC "%{shared:-shared} -N -relax \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ + %{!Wl,-T*: %{!T*: -dT xilinx.ld%s}}" + +/* Specs for the compiler proper */ + +#ifndef CC1_SPEC +#define CC1_SPEC " \ +%{G*} %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ +%{save-temps: } \ +%(subtarget_cc1_spec) \ +%{mxl-multiply-high:-mcpu=v6.00.a} \ +" +#endif + +#define EXTRA_SPECS \ + { "target_asm_spec", TARGET_ASM_SPEC }, \ + SUBTARGET_EXTRA_SPECS + +/* Print subsidiary information on the compiler version in use. */ +#define MICROBLAZE_VERSION MICROBLAZE_DEFAULT_CPU + +#ifndef MACHINE_TYPE +#define MACHINE_TYPE "MicroBlaze/ELF" +#endif + +#ifndef TARGET_VERSION_INTERNAL +#define TARGET_VERSION_INTERNAL(STREAM) \ + fprintf (STREAM, " %s %s", MACHINE_TYPE, MICROBLAZE_VERSION) +#endif + +#ifndef TARGET_VERSION +#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) +#endif + +/* Local compiler-generated symbols must have a prefix that the assembler + understands. */ + +#ifndef LOCAL_LABEL_PREFIX +#define LOCAL_LABEL_PREFIX "$" +#endif + +/* fixed registers. */ +#define MB_ABI_BASE_REGNUM 0 +#define MB_ABI_STACK_POINTER_REGNUM 1 +#define MB_ABI_GPRO_REGNUM 2 +#define MB_ABI_GPRW_REGNUM 13 +#define MB_ABI_INTR_RETURN_ADDR_REGNUM 14 +#define MB_ABI_SUB_RETURN_ADDR_REGNUM 15 +#define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16 +#define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17 +#define MB_ABI_ASM_TEMP_REGNUM 18 +/* This is our temp register. */ +#define MB_ABI_FRAME_POINTER_REGNUM 19 +#define MB_ABI_PIC_ADDR_REGNUM 20 +#define MB_ABI_PIC_FUNC_REGNUM 21 +/* Volatile registers. */ +#define MB_ABI_INT_RETURN_VAL_REGNUM 3 +#define MB_ABI_INT_RETURN_VAL2_REGNUM 4 +#define MB_ABI_FIRST_ARG_REGNUM 5 +#define MB_ABI_LAST_ARG_REGNUM 10 +#define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \ + - MB_ABI_FIRST_ARG_REGNUM + 1) +#define MB_ABI_STATIC_CHAIN_REGNUM 3 +#define MB_ABI_TEMP1_REGNUM 11 +#define MB_ABI_TEMP2_REGNUM 12 +#define MB_ABI_MSR_SAVE_REG 11 +/* Volatile register used to save MSR in interrupt handlers. */ + + +/* Debug stuff. */ + +/* How to renumber registers for dbx and gdb. */ +#define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)] + +/* Generate DWARF exception handling info. */ +#define DWARF2_UNWIND_INFO 1 + +/* Don't generate .loc operations. */ +#define DWARF2_ASM_LINE_DEBUG_INFO 0 + +/* The DWARF 2 CFA column which tracks the return address. */ +#define DWARF_FRAME_RETURN_COLUMN \ + (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM) + +/* Initial state of return address on entry to func = R15. + Actually, the RA is at R15+8, but gcc doesn't know how + to generate this. + NOTE: GDB has a workaround and expects this incorrect value. + If this is fixed, a corresponding fix to GDB is needed. */ +#define INCOMING_RETURN_ADDR_RTX \ + gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM) + +/* Use DWARF 2 debugging information by default. */ +#define DWARF2_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +/* Target machine storage layout */ + +#define BITS_BIG_ENDIAN 0 +#define BYTES_BIG_ENDIAN 1 +#define WORDS_BIG_ENDIAN 1 +#define BITS_PER_UNIT 8 +#define BITS_PER_WORD 32 +#define UNITS_PER_WORD 4 +#define MIN_UNITS_PER_WORD 4 +#define INT_TYPE_SIZE 32 +#define SHORT_TYPE_SIZE 16 +#define LONG_TYPE_SIZE 32 +#define LONG_LONG_TYPE_SIZE 64 +#define FLOAT_TYPE_SIZE 32 +#define DOUBLE_TYPE_SIZE 64 +#define LONG_DOUBLE_TYPE_SIZE 64 +#define POINTER_SIZE 32 +#define PARM_BOUNDARY 32 +#define FUNCTION_BOUNDARY 32 +#define EMPTY_FIELD_BOUNDARY 32 +#define STRUCTURE_SIZE_BOUNDARY 8 +#define BIGGEST_ALIGNMENT 32 +#define STRICT_ALIGNMENT 1 +#define PCC_BITFIELD_TYPE_MATTERS 1 + +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ + && (ALIGN) < BITS_PER_WORD \ + ? BITS_PER_WORD \ + : (ALIGN)) + +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ + && (TREE_CODE (TYPE) == ARRAY_TYPE \ + || TREE_CODE (TYPE) == UNION_TYPE \ + || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) + +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ + (((TREE_CODE (TYPE) == ARRAY_TYPE \ + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \ + && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)) + +#define WORD_REGISTER_OPERATIONS + +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND + +#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < 4) \ + (MODE) = SImode; + +/* Standard register usage. */ + +/* On the MicroBlaze, we have 32 integer registers */ + +#define FIRST_PSEUDO_REGISTER 36 + +#define FIXED_REGISTERS \ +{ \ + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ + 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1 \ +} + +#define CALL_USED_REGISTERS \ +{ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1 \ +} + +#define GP_REG_FIRST 0 +#define GP_REG_LAST 31 +#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) +#define GP_DBX_FIRST 0 + +#define ST_REG 32 +#define AP_REG_NUM 33 +#define RAP_REG_NUM 34 +#define FRP_REG_NUM 35 + +#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) +#define ST_REG_P(REGNO) ((REGNO) == ST_REG) + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode + MODE. In 32 bit mode, require that DImode and DFmode be in even + registers. For DImode, this makes some of the insns easier to + write, since you don't have to worry about a DImode value in + registers 3 & 4, producing a result in 4 & 5. + + To make the code simpler HARD_REGNO_MODE_OK now just references an + array built in override_options. Because machmodes.h is not yet + included before this file is processed, the MODE bound can't be + expressed here. */ +extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)] + +#define MODES_TIEABLE_P(MODE1, MODE2) \ + ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ + GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ + == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ + GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) + +#define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM) + +#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL) + +/* Base register for access to local variables of the function. We + pretend that the frame pointer is + MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it + to HARD_FRAME_POINTER_REGNUM. We can get away with this because + rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed + register(return address for interrupt), and will not be used for + anything else. */ + +#define FRAME_POINTER_REGNUM FRP_REG_NUM +#define HARD_FRAME_POINTER_REGNUM \ + (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM) +#define ARG_POINTER_REGNUM AP_REG_NUM +#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM +#define STATIC_CHAIN_REGNUM \ + (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM) + +/* registers used in prologue/epilogue code when the stack frame + is larger than 32K bytes. These registers must come from the + scratch register set, and not used for passing and returning + arguments and any other information used in the calling sequence + (such as pic). */ + +#define MICROBLAZE_TEMP1_REGNUM \ + (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM) + +#define MICROBLAZE_TEMP2_REGNUM \ + (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM) + +#define NO_FUNCTION_CSE 1 + +#define PIC_OFFSET_TABLE_REGNUM \ + (flag_pic ? (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM) : \ + INVALID_REGNUM) + +enum reg_class +{ + NO_REGS, /* no registers in set. */ + GR_REGS, /* integer registers. */ + ST_REGS, /* status register. */ + ALL_REGS, /* all registers. */ + LIM_REG_CLASSES /* max value + 1. */ +}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +#define GENERAL_REGS GR_REGS + +#define REG_CLASS_NAMES \ +{ \ + "NO_REGS", \ + "GR_REGS", \ + "ST_REGS", \ + "ALL_REGS" \ +} + +#define REG_CLASS_CONTENTS \ +{ \ + { 0x00000000, 0x00000000 }, /* no registers. */ \ + { 0xffffffff, 0x00000000 }, /* integer registers. */ \ + { 0x00000000, 0x00000001 }, /* status registers. */ \ + { 0xffffffff, 0x0000000f } /* all registers. */ \ +} + +extern enum reg_class microblaze_regno_to_class[]; + +#define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ] + +#define BASE_REG_CLASS GR_REGS + +#define INDEX_REG_CLASS GR_REGS + +#define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS) + +/* REGISTER AND CONSTANT CLASSES */ + +#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) +#define LARGE_INT(X) (INTVAL (X) >= 0x80000000 && INTVAL (X) <= 0xffffffff) +#define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT) +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ +#define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \ + || (GET_CODE (X) == REG && X != arg_pointer_rtx\ + && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \ + && REGNO (X) <= LAST_VIRTUAL_REGISTER))) + +/* True if VALUE is a signed 16-bit number. */ +#define SMALL_OPERAND(VALUE) \ + ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) + +/* Constant which cannot be loaded in one instruction. */ +#define LARGE_OPERAND(VALUE) \ + ((((VALUE) & ~0x0000ffff) != 0) \ + && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \ + && (((VALUE) & 0x0000ffff) != 0 \ + || (((VALUE) & ~2147483647) != 0 \ + && ((VALUE) & ~2147483647) != ~2147483647))) + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + ((CLASS) != ALL_REGS \ + ? (CLASS) \ + : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ + ? (GR_REGS) \ + : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ + || GET_MODE (X) == VOIDmode) \ + ? (GR_REGS) : (CLASS)))) + +#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ + (GET_MODE_CLASS (MODE) == MODE_INT) + +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((GET_MODE_SIZE (MODE) + (UNITS_PER_WORD) - 1) / (UNITS_PER_WORD)) + +/* Stack layout; function entry, exit and calling. */ + +#define STACK_GROWS_DOWNWARD + +/* Changed the starting frame offset to including the new link stuff */ +#define STARTING_FRAME_OFFSET \ + (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL)) + +/* The return address for the current frame is in r31 if this is a leaf + function. Otherwise, it is on the stack. It is at a variable offset + from sp/fp/ap, so we define a fake hard register rap which is a + poiner to the return address on the stack. This always gets eliminated + during reload to be either the frame pointer or the stack pointer plus + an offset. */ + +#define RETURN_ADDR_RTX(count, frame) \ + microblaze_return_addr(count,frame) + +extern struct microblaze_frame_info current_frame_info; + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \ + { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { RETURN_ADDRESS_POINTER_REGNUM, \ + GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \ + { RETURN_ADDRESS_POINTER_REGNUM, \ + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}} + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ + (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO)) + +#define ACCUMULATE_OUTGOING_ARGS 1 + +#define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) + +#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 + +#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) + +#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +#define STACK_BOUNDARY 32 + +#define NUM_OF_ARGS 6 + +#define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) + +#define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM) +#define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM) + +#define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + +#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) + +/* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ + +#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN) + +#define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) + +typedef struct microblaze_args +{ + int gp_reg_found; /* whether a gp register was found yet */ + int arg_number; /* argument number */ + int arg_words; /* # total words the arguments take */ + int fp_arg_words; /* # words for FP args */ + int last_arg_fp; /* nonzero if last arg was FP (EABI only) */ + int fp_code; /* Mode of FP arguments */ + int num_adjusts; /* number of adjustments made */ + /* Adjustments made to args pass in regs. */ + /* ??? The size is doubled to work around a bug in the code that sets the + adjustments in function_arg. */ + struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS * 2]; +} CUMULATIVE_ARGS; + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ + init_cumulative_args (&CUM, FNTYPE, LIBNAME) + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + function_arg_advance (&CUM, MODE, TYPE, NAMED) + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + function_arg( &CUM, MODE, TYPE, NAMED) + +#define NO_PROFILE_COUNTERS 1 + +#define FUNCTION_PROFILER(FILE, LABELNO) { \ + { \ + fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ + } \ + } + +#define EXIT_IGNORE_STACK 1 + +#define TRAMPOLINE_SIZE (32 + 8) + +#define TRAMPOLINE_ALIGNMENT 32 + +#define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +#define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +#ifndef REG_OK_STRICT +#define REG_STRICT_FLAG 0 +#else +#define REG_STRICT_FLAG 1 +#endif + +#define REG_OK_FOR_BASE_P(X) \ + microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG) + +#define REG_OK_FOR_INDEX_P(X) \ + microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG) + +#define MAX_REGS_PER_ADDRESS 2 + + +/* Identify valid constant addresses. Exclude if PIC addr which + needs scratch register. */ +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT \ + || (GET_CODE (X) == CONST \ + && ! (flag_pic && pic_address_needs_scratch (X)))) + +/* Define this, so that when PIC, reload won't try to reload invalid + addresses which require two reload registers. */ +#define LEGITIMATE_PIC_OPERAND_P(X) (!pic_address_needs_scratch (X)) + +/* At present, GAS doesn't understand li.[sd], so don't allow it + to be generated at present. */ +#define LEGITIMATE_CONSTANT_P(X) \ + (GET_CODE (X) != CONST_DOUBLE \ + || microblaze_const_double_ok (X, GET_MODE (X))) + +#define CASE_VECTOR_MODE (SImode) + +#ifndef DEFAULT_SIGNED_CHAR +#define DEFAULT_SIGNED_CHAR 1 +#endif + +#define MOVE_MAX 4 +#define MAX_MOVE_MAX 8 + +#define SLOW_BYTE_ACCESS 1 + +/* sCOND operations return 1. */ +#define STORE_FLAG_VALUE 1 + +#define SHIFT_COUNT_TRUNCATED 1 + +/* This results in inefficient code for 64 bit to 32 conversions. + Something needs to be done about this. Perhaps not use any 32 bit + instructions? Perhaps use PROMOTE_MODE? */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +#define Pmode SImode + +#define FUNCTION_MODE SImode + +/* Mode should alwasy be SImode */ +#define REGISTER_MOVE_COST(MODE, FROM, TO) \ + ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \ + : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \ + : 12) + +#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ + (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) + +#define BRANCH_COST(speed_p, predictable_p) 2 + +/* Control the assembler format that we output. */ +#define ASM_APP_ON " #APP\n" +#define ASM_APP_OFF " #NO_APP\n" + +#define REGISTER_NAMES { \ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ + "rmsr", "$ap", "$rap", "$frp" } + +#define ADDITIONAL_REGISTER_NAMES \ +{ \ + { "r0", 0 + GP_REG_FIRST }, \ + { "r1", 1 + GP_REG_FIRST }, \ + { "r2", 2 + GP_REG_FIRST }, \ + { "r3", 3 + GP_REG_FIRST }, \ + { "r4", 4 + GP_REG_FIRST }, \ + { "r5", 5 + GP_REG_FIRST }, \ + { "r6", 6 + GP_REG_FIRST }, \ + { "r7", 7 + GP_REG_FIRST }, \ + { "r8", 8 + GP_REG_FIRST }, \ + { "r9", 9 + GP_REG_FIRST }, \ + { "r10", 10 + GP_REG_FIRST }, \ + { "r11", 11 + GP_REG_FIRST }, \ + { "r12", 12 + GP_REG_FIRST }, \ + { "r13", 13 + GP_REG_FIRST }, \ + { "r14", 14 + GP_REG_FIRST }, \ + { "r15", 15 + GP_REG_FIRST }, \ + { "r16", 16 + GP_REG_FIRST }, \ + { "r17", 17 + GP_REG_FIRST }, \ + { "r18", 18 + GP_REG_FIRST }, \ + { "r19", 19 + GP_REG_FIRST }, \ + { "r20", 20 + GP_REG_FIRST }, \ + { "r21", 21 + GP_REG_FIRST }, \ + { "r22", 22 + GP_REG_FIRST }, \ + { "r23", 23 + GP_REG_FIRST }, \ + { "r24", 24 + GP_REG_FIRST }, \ + { "r25", 25 + GP_REG_FIRST }, \ + { "r26", 26 + GP_REG_FIRST }, \ + { "r27", 27 + GP_REG_FIRST }, \ + { "r28", 28 + GP_REG_FIRST }, \ + { "r29", 29 + GP_REG_FIRST }, \ + { "r30", 30 + GP_REG_FIRST }, \ + { "r31", 31 + GP_REG_FIRST }, \ + { "rmsr", ST_REG} \ +} + +#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE] + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) + +/* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL + + Unfortunately, we still need to set the section explicitly. Somehow, + our binutils assign .comm and .lcomm variables to the "current" section + in the assembly file, rather than where they implicitly belong. We need to + remove this explicit setting in GCC when binutils can understand sections + better. */ +#undef ASM_OUTPUT_ALIGNED_COMMON +#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ +do { \ + if (SIZE > 0 && SIZE <= microblaze_section_threshold \ + && TARGET_XLGPOPT) \ + { \ + switch_to_section (sbss_section); \ + } \ + else \ + { \ + switch_to_section (bss_section); \ + } \ + fprintf (FILE, "%s", COMMON_ASM_OP); \ + assemble_name ((FILE), (NAME)); \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ + (SIZE), (ALIGN) / BITS_PER_UNIT); \ + ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ +} while (0) + +#undef ASM_OUTPUT_ALIGNED_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ +do { \ + if (SIZE > 0 && SIZE <= microblaze_section_threshold \ + && TARGET_XLGPOPT) \ + { \ + switch_to_section (sbss_section); \ + } \ + else \ + { \ + switch_to_section (bss_section); \ + } \ + fprintf (FILE, "%s", LCOMMON_ASM_OP); \ + assemble_name ((FILE), (NAME)); \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ + (SIZE), (ALIGN) / BITS_PER_UNIT); \ + ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ +} while (0) + +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ +do { \ + ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ +} while (0) + +#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ +{ \ +} + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) + +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ + fprintf (STREAM, "\t%s\t%sL%d\n", \ + ".gpword", \ + LOCAL_LABEL_PREFIX, VALUE) + +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ +do { \ + if (flag_pic == 2) \ + fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \ + ".gpword", \ + LOCAL_LABEL_PREFIX, VALUE); \ + else \ + fprintf (STREAM, "\t%s\t%sL%d\n", \ + ".gpword", \ + LOCAL_LABEL_PREFIX, VALUE); \ +} while (0) + +#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ + fprintf (STREAM, "\t.align\t%d\n", (LOG)) + +#define ASM_OUTPUT_SKIP(STREAM,SIZE) \ + fprintf (STREAM, "\t.space\t%lu\n", (SIZE)) + +#define ASCII_DATA_ASM_OP "\t.ascii\t" +#define STRING_ASM_OP "\t.asciz\t" + +#define ASM_OUTPUT_IDENT(FILE, STRING) \ + microblaze_asm_output_ident (FILE, STRING) + +/* Default to -G 8 */ +#ifndef MICROBLAZE_DEFAULT_GVALUE +#define MICROBLAZE_DEFAULT_GVALUE 8 +#endif + +/* Given a decl node or constant node, choose the section to output it in + and select that section. */ + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +/* How to start an assembler comment. + The leading space is important (the microblaze assembler requires it). */ +#ifndef ASM_COMMENT_START +#define ASM_COMMENT_START " #" +#endif + +#define BSS_VAR 1 +#define SBSS_VAR 2 +#define DATA_VAR 4 +#define SDATA_VAR 5 +#define RODATA_VAR 6 +#define SDATA2_VAR 7 + +/* These definitions are used in with the shift_type flag in the rtl. */ +#define SHIFT_CONST 1 +#define SHIFT_REG 2 +#define USE_ADDK 3 + +/* Handle interrupt attribute. */ +extern int interrupt_handler; +extern int save_volatiles; + +#define INTERRUPT_HANDLER_NAME "_interrupt_handler" + +/* These #define added for C++. */ +#define UNALIGNED_SHORT_ASM_OP ".data16" +#define UNALIGNED_INT_ASM_OP ".data32" +#define UNALIGNED_DOUBLE_INT_ASM_OP ".data8" + +#define ASM_BYTE_OP ".data8" + +/* The following #defines are used in the headers files. Always retain these. */ + +/* Added for declaring size at the end of the function. */ +#undef ASM_DECLARE_FUNCTION_SIZE +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \ + fprintf (FILE, "%s", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } while (0) + +#define GLOBAL_ASM_OP "\t.globl\t" +#define TYPE_ASM_OP "\t.type\t" +#define SIZE_ASM_OP "\t.size\t" +#define COMMON_ASM_OP "\t.comm\t" +#define LCOMMON_ASM_OP "\t.lcomm\t" + +#define MAX_OFILE_ALIGNMENT (32768*8) + +#define TYPE_OPERAND_FMT "@%s" + +/* Write the extra assembler code needed to declare an object properly. */ +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "%s", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "%s", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + microblaze_declare_object (FILE, NAME, "", ":\n", 0); \ + } while (0) + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "%s", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fputc ( '\t', FILE); \ + assemble_name (FILE, LABEL1); \ + fputs ( " = ", FILE); \ + assemble_name (FILE, LABEL2); \ + fputc ( '\n', FILE); \ + } while (0) + +#define ASM_WEAKEN_LABEL(FILE,NAME) \ + do { fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + fputc ('\n', FILE); \ + } while (0) + +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) +#undef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) + +#undef TARGET_ASM_NAMED_SECTION +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section + +/* Define the strings to put out for each section in the object file. + + Note: For ctors/dtors, we want to give these sections the SHF_WRITE + attribute to allow shared libraries to patch/resolve addresses into + these locations. On Microblaze, there is no concept of shared libraries + yet, so this is for future use. */ +#define TEXT_SECTION_ASM_OP "\t.text" +#define DATA_SECTION_ASM_OP "\t.data" +#define READONLY_DATA_SECTION_ASM_OP \ + "\t.rodata" +#define BSS_SECTION_ASM_OP "\t.bss" +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" +#define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\"" +#define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\"" + +#define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */ +#define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */ +#define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */ +#define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */ + +#define HOT_TEXT_SECTION_NAME ".text.hot" +#define UNLIKELY_EXECUTED_TEXT_SECTION_NAME \ + ".text.unlikely" + +/* We do this to save a few 10s of code space that would be taken up + by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION + definition in crtstuff.c. */ +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm ( SECTION_OP "\n" \ + "\tbrlid r15, " #FUNC "\n\t nop\n" \ + TEXT_SECTION_ASM_OP); + +/* We need to group -lm as well, since some Newlib math functions + reference __errno! */ +#undef LIB_SPEC +#define LIB_SPEC \ +"%{!nostdlib: \ +%{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \ +%{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} " + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +#define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" +#define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s" +#define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s" +#define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s" +#define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \ +%{mno-clearbss: sim-crtinit.o%s}} \ +%{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}" + +#define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \ + { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \ + { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \ + { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \ + { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \ + { "startfile_default", STARTFILE_DEFAULT_SPEC }, + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "\ +%{Zxl-mode-executable : %(startfile_executable) ; \ + mxl-mode-executable : %(startfile_executable) ; \ + Zxl-mode-xmdstub : %(startfile_xmdstub) ; \ + mxl-mode-xmdstub : %(startfile_xmdstub) ; \ + Zxl-mode-bootstrap : %(startfile_bootstrap) ; \ + mxl-mode-bootstrap : %(startfile_bootstrap) ; \ + Zxl-mode-novectors : %(startfile_novectors) ; \ + mxl-mode-novectors : %(startfile_novectors) ; \ + Zxl-mode-xilkernel : %(startfile_xilkernel) ; \ + mxl-mode-xilkernel : %(startfile_xilkernel) ; \ + : %(startfile_default) \ +} \ +%(startfile_crtinit)" diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md new file mode 100644 index 00000000000..19b77f9bc21 --- /dev/null +++ b/gcc/config/microblaze/microblaze.md @@ -0,0 +1,2231 @@ +;; microblaze.md -- Machine description for Xilinx MicroBlaze processors. +;; Copyright 2009, 2010 Free Software Foundation, Inc. + +;; Contributed by Michael Eager <eager@eagercon.com>. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. */ + +(include "constraints.md") +(include "predicates.md") + +;;---------------------------------------------------- +;; Constants +;;---------------------------------------------------- +(define_constants [ + (R_SP 1) ;; Stack pointer reg + (R_SR 15) ;; Sub-routine return addr reg + (R_IR 14) ;; Interrupt return addr reg + (R_DR 16) ;; Debug trap return addr reg + (R_ER 17) ;; Exception return addr reg + (R_TMP 18) ;; Assembler temporary reg + (R_GOT 20) ;; GOT ptr reg + (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline + (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline + (UNSPEC_SET_GOT 101) ;; + (UNSPEC_GOTOFF 102) ;; GOT offset + (UNSPEC_PLT 103) ;; jump table + (UNSPEC_CMP 104) ;; signed compare + (UNSPEC_CMPU 105) ;; unsigned compare +]) + + +;;---------------------------------------------------- +;; Instruction Attributes +;;---------------------------------------------------- + +;; Classification of each insn. +;; branch conditional branch +;; jump unconditional jump +;; call unconditional call +;; load load instruction(s) +;; store store instruction(s) +;; move data movement within same register set +;; arith integer arithmetic instruction +;; darith double precision integer arithmetic instructions +;; imul integer multiply +;; idiv integer divide +;; icmp integer compare +;; Xfadd floating point add/subtract +;; Xfmul floating point multiply +;; Xfmadd floating point multiply-add +;; Xfdiv floating point divide +;; Xfabs floating point absolute value +;; Xfneg floating point negation +;; Xfcmp floating point compare +;; Xfcvt floating point convert +;; Xfsqrt floating point square root +;; multi multiword sequence (or user asm statements) +;; nop no operation +;; bshift Shift operations + +(define_attr "type" + "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt" + (const_string "unknown")) + +;; Main data type used by the insn +(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF" (const_string "unknown")) + +;; # instructions (4 bytes each) +(define_attr "length" "" (const_int 4)) + +;;---------------------------------------------------- +;; Attribute describing the processor. +;;---------------------------------------------------- + +;; Describe a user's asm statement. +(define_asm_attributes + [(set_attr "type" "multi")]) + +;; whether or not generating calls to position independent functions +(define_attr "abicalls" "no,yes" + (const (symbol_ref "microblaze_abicalls_attr"))) + +;;---------------------------------------------------------------- +;; Microblaze DFA Pipeline description +;;---------------------------------------------------------------- + +;;----------------------------------------------------------------- +/* + This is description of pipeline hazards based on DFA. The + following constructions can be used for this: + + o define_cpu_unit string [string]) describes a cpu functional unit + (separated by comma). + + 1st operand: Names of cpu function units. + 2nd operand: Name of automaton (see comments for + DEFINE_AUTOMATON). + + All define_reservations and define_cpu_units should have unique + names which can not be "nothing". + + o (exclusion_set string string) means that each CPU function unit + in the first string can not be reserved simultaneously with each + unit whose name is in the second string and vise versa. CPU + units in the string are separated by commas. For example, it is + useful for description CPU with fully pipelined floating point + functional unit which can execute simultaneously only single + floating point insns or only double floating point insns. + + o (presence_set string string) means that each CPU function unit in + the first string can not be reserved unless at least one of units + whose names are in the second string is reserved. This is an + asymmetric relation. CPU units in the string are separated by + commas. For example, it is useful for description that slot1 is + reserved after slot0 reservation for a VLIW processor. + + o (absence_set string string) means that each CPU function unit in + the first string can not be reserved only if each unit whose name + is in the second string is not reserved. This is an asymmetric + relation (actually exclusion set is analogous to this one but it + is symmetric). CPU units in the string are separated by commas. + For example, it is useful for description that slot0 can not be + reserved after slot1 or slot2 reservation for a VLIW processor. + + o (define_bypass number out_insn_names in_insn_names) names bypass with + given latency (the first number) from insns given by the first + string (see define_insn_reservation) into insns given by the + second string. Insn names in the strings are separated by + commas. + + o (define_automaton string) describes names of an automaton + generated and used for pipeline hazards recognition. The names + are separated by comma. Actually it is possibly to generate the + single automaton but unfortunately it can be very large. If we + use more one automata, the summary size of the automata usually + is less than the single one. The automaton name is used in + define_cpu_unit. All automata should have unique names. + + o (define_reservation string string) names reservation (the first + string) of cpu functional units (the 2nd string). Sometimes unit + reservations for different insns contain common parts. In such + case, you describe common part and use one its name (the 1st + parameter) in regular expression in define_insn_reservation. All + define_reservations, define results and define_cpu_units should + have unique names which can not be "nothing". + + o (define_insn_reservation name default_latency condition regexpr) + describes reservation of cpu functional units (the 3nd operand) + for instruction which is selected by the condition (the 2nd + parameter). The first parameter is used for output of debugging + information. The reservations are described by a regular + expression according the following syntax: + + regexp = regexp "," oneof + | oneof + + oneof = oneof "|" allof + | allof + + allof = allof "+" repeat + | repeat + + repeat = element "*" number + | element + + element = cpu_function_name + | reservation_name + | result_name + | "nothing" + | "(" regexp ")" + + 1. "," is used for describing start of the next cycle in + reservation. + + 2. "|" is used for describing the reservation described by the + first regular expression *or* the reservation described by + the second regular expression *or* etc. + + 3. "+" is used for describing the reservation described by the + first regular expression *and* the reservation described by + the second regular expression *and* etc. + + 4. "*" is used for convenience and simply means sequence in + which the regular expression are repeated NUMBER times with + cycle advancing (see ","). + + 5. cpu function unit name which means reservation. + + 6. reservation name -- see define_reservation. + + 7. string "nothing" means no units reservation. + +*/ +;;----------------------------------------------------------------- + + +;;---------------------------------------------------------------- +;; Microblaze 5-stage pipeline description (v5.00.a and later) +;;---------------------------------------------------------------- + +(define_automaton "mbpipe_5") +(define_cpu_unit "mb_issue,mb_iu,mb_wb,mb_fpu,mb_fpu_2,mb_mul,mb_mul_2,mb_div,mb_div_2,mb_bs,mb_bs_2" "mbpipe_5") + +(define_insn_reservation "mb-integer" 1 + (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_iu,mb_wb") + +(define_insn_reservation "mb-special-move" 2 + (and (eq_attr "type" "move") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_iu*2,mb_wb") + +(define_insn_reservation "mb-mem-load" 3 + (and (eq_attr "type" "load,no_delay_load") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_iu,mb_wb") + +(define_insn_reservation "mb-mem-store" 1 + (and (eq_attr "type" "store,no_delay_store") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_iu,mb_wb") + +(define_insn_reservation "mb-mul" 3 + (and (eq_attr "type" "imul,no_delay_imul") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_mul,mb_mul_2*2,mb_wb") + +(define_insn_reservation "mb-div" 34 + (and (eq_attr "type" "idiv") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_div,mb_div_2*33,mb_wb") + +(define_insn_reservation "mb-bs" 2 + (and (eq_attr "type" "bshift") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_bs,mb_bs_2,mb_wb") + +(define_insn_reservation "mb-fpu-add-sub-mul" 6 + (and (eq_attr "type" "fadd,frsub,fmul") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_fpu,mb_fpu_2*5,mb_wb") + +(define_insn_reservation "mb-fpu-fcmp" 3 + (and (eq_attr "type" "fcmp") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_fpu,mb_fpu*2,mb_wb") + +(define_insn_reservation "mb-fpu-div" 30 + (and (eq_attr "type" "fdiv") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_fpu,mb_fpu_2*29,mb_wb") + +(define_insn_reservation "mb-fpu-sqrt" 30 + (and (eq_attr "type" "fsqrt") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_fpu,mb_fpu_2*29,mb_wb") + +(define_insn_reservation "mb-fpu-fcvt" 4 + (and (eq_attr "type" "fcvt") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_5))) + "mb_issue,mb_fpu,mb_fpu_2*3,mb_wb") + +;;---------------------------------------------------------------- +;; Microblaze 3-stage pipeline description (for v4.00.a and earlier) +;;---------------------------------------------------------------- + +(define_automaton "mbpipe_3") +(define_cpu_unit "mb3_iu" "mbpipe_3") + +(define_insn_reservation "mb3-integer" 1 + (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-special-move" 2 + (and (eq_attr "type" "move") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu*2") + +(define_insn_reservation "mb3-mem-load" 2 + (and (eq_attr "type" "load,no_delay_load") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-mem-store" 1 + (and (eq_attr "type" "store,no_delay_store") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-mul" 3 + (and (eq_attr "type" "imul,no_delay_imul") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-div" 34 + (and (eq_attr "type" "idiv") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-bs" 2 + (and (eq_attr "type" "bshift") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-fpu-add-sub-mul" 6 + (and (eq_attr "type" "fadd,frsub,fmul") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-fpu-fcmp" 3 + (and (eq_attr "type" "fcmp") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-fpu-div" 30 + (and (eq_attr "type" "fdiv") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-fpu-sqrt" 30 + (and (eq_attr "type" "fsqrt") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(define_insn_reservation "mb3-fpu-fcvt" 4 + (and (eq_attr "type" "fcvt") + (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_3))) + "mb3_iu") + +(automata_option "v") +(automata_option "time") +(automata_option "progress") + +;;---------------------------------------------------------------- +;; Microblaze delay slot description +;;---------------------------------------------------------------- +(define_delay (eq_attr "type" "branch,call,jump") + [(and (eq_attr "type" "!branch,call,jump,icmp,multi,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,darith") + (ior (eq (symbol_ref "microblaze_no_unsafe_delay") (const_int 0)) + (eq_attr "type" "!fadd,frsub,fmul,fdiv,fcmp,store,load") + )) + (nil) (nil)]) + + +;;---------------------------------------------------------------- +;; Microblaze FPU +;;---------------------------------------------------------------- + +(define_insn "addsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (plus:SF (match_operand:SF 1 "register_operand" "d") + (match_operand:SF 2 "register_operand" "d")))] + "TARGET_HARD_FLOAT" + "fadd\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +(define_insn "subsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (minus:SF (match_operand:SF 1 "register_operand" "d") + (match_operand:SF 2 "register_operand" "d")))] + "TARGET_HARD_FLOAT" + "frsub\t%0,%2,%1" + [(set_attr "type" "frsub") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +(define_insn "mulsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (mult:SF (match_operand:SF 1 "register_operand" "d") + (match_operand:SF 2 "register_operand" "d")))] + "TARGET_HARD_FLOAT" + "fmul\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + + +(define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "register_operand" "d") + (match_operand:SF 2 "register_operand" "d")))] + "TARGET_HARD_FLOAT" + "fdiv\t%0,%2,%1" + [(set_attr "type" "fdiv") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +(define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" + "fsqrt\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +(define_insn "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (float:SF (match_operand:SI 1 "register_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "flt\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +(define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "fint\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +;;---------------------------------------------------------------- +;; Add +;;---------------------------------------------------------------- + +;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] +;; Leave carry as is +(define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") + (match_operand:SI 2 "arith_operand" "d,I,i")))] + "" + "@ + addk\t%0,%z1,%2 + addik\t%0,%z1,%2 + addik\t%0,%z1,%2" + [(set_attr "type" "arith,arith,no_delay_arith") + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,4,8")]) + +;;---------------------------------------------------------------- +;; Double Precision Additions +;;---------------------------------------------------------------- + +;; reg_DI_dest = reg_DI_src1 + DI_src2 + +;; Adding 2 DI operands in register or reg/imm + +(define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d") + (match_operand:DI 2 "arith_operand32" "d,P,N")))] + "" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 + addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0 + addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8,8,12")]) + +;;---------------------------------------------------------------- +;; Subtraction +;;---------------------------------------------------------------- + +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (minus:SI (match_operand:SI 1 "arith_operand" "d,d") + (match_operand:SI 2 "arith_operand" "d,n")))] + "" + "@ + rsubk\t%0,%2,%z1 + addik\t%0,%z1,-%2" + [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "SI") + (set_attr "length" "4,8")]) + + +;;---------------------------------------------------------------- +;; Double Precision Subtraction +;;---------------------------------------------------------------- + +(define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "arith_operand32" "d")))] + "" + "@ + rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + + +;;---------------------------------------------------------------- +;; Multiplication +;;---------------------------------------------------------------- + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") + (match_operand:SI 2 "arith_operand" "d,I,i")))] + "!TARGET_SOFT_MUL" + "@ + mul\t%0,%1,%2 + muli\t%0,%1,%2 + muli\t%0,%1,%2" + [(set_attr "type" "imul,imul,no_delay_imul") + (set_attr "mode" "SI") + (set_attr "length" "4,4,8")]) + +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (mult:DI + (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_insn "usmulsidi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_insn "*smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))) + (const_int 32))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mulh\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "*umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d")) +) + (const_int 32))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mulhu\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "*usmulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d")) +) + (const_int 32))))] + "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" + "mulhsu\t%0,%2,%1" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + + +;;---------------------------------------------------------------- +;; Division and remainder +;;---------------------------------------------------------------- +(define_expand "divsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + ] + "(!TARGET_SOFT_DIV) || (TARGET_BARREL_SHIFT && TARGET_SMALL_DIVIDES)" + { + if (TARGET_SOFT_DIV && TARGET_BARREL_SHIFT && TARGET_SMALL_DIVIDES) + { + microblaze_expand_divide (operands); + DONE; + } + else if (!TARGET_SOFT_DIV) + { + emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2])); + DONE; + } + } +) + + +(define_insn "divsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=d") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + ] + "!TARGET_SOFT_DIV" + "idiv\t%0,%2,%1" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +(define_insn "udivsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + ] + "!TARGET_SOFT_DIV" + "idivu\t%0,%2,%1" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + + +;;---------------------------------------------------------------- +;; Negation and one's complement +;;---------------------------------------------------------------- + +(define_insn "negsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (neg:SI (match_operand:SI 1 "register_operand" "d")))] + "" + "rsubk\t%0,%1,r0" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] + "" + "rsub\t%L0,%L1,r0\;rsubc\t%M0,%M1,r0" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (match_operand:SI 1 "register_operand" "d")))] + "" + "xori\t%0,%1,-1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "*one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] + "" + "nor\t%M0,r0,%M1\;nor\t%L0,r0,%L1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")] +) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] + "") + + +;;---------------------------------------------------------------- +;; Logical +;;---------------------------------------------------------------- + +(define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") + (match_operand:SI 2 "arith_operand" "d,I,i,M")))] + "" + "@ + and\t%0,%1,%2 + andi\t%0,%1,%2 #and1 + andi\t%0,%1,%2 #and2 + andi\t%0,%1,%2 #and3" + [(set_attr "type" "arith,arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + + +(define_insn "anddi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] + "" + "and\t%M0,%M1,%M2\;and\t%L0,%L1,%L2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4)))] + "") + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") + (match_operand:SI 2 "arith_operand" "d,I,M,i")))] + "" + "@ + or\t%0,%1,%2 + ori\t%0,%1,%2 + ori\t%0,%1,%2 + ori\t%0,%1,%2" + [(set_attr "type" "arith,no_delay_arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + + +(define_insn "iordi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (ior:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] + "" + "or\t%M0,%M1,%M2\;or\t%L0,%L1,%L2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")] +) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ior:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4)))] + "") + +(define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") + (match_operand:SI 2 "arith_operand" "d,I,i")))] + "" + "@ + xor\t%0,%1,%2 + xori\t%0,%1,%2 + xori\t%0,%1,%2" + [(set_attr "type" "arith,arith,no_delay_arith") + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,8,8")]) + +(define_insn "xordi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (xor:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] + "" + "xor\t%M0,%M1,%M2\;xor\t%L0,%L1,%L2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "8")] +) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4)))] + "") + +;;---------------------------------------------------------------- +;; Zero extension +;;---------------------------------------------------------------- + +(define_insn "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] + "" + "@ + andi\t%0,%1,0xffff + lhu%i1\t%0,%1 + lhu%i1\t%0,%1" + [(set_attr "type" "no_delay_arith,load,no_delay_load") + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "8,4,8")]) + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=d,d,d") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] + "" + "@ + andi\t%0,%1,0x00ff + lbu%i1\t%0,%1 + lbu%i1\t%0,%1" + [(set_attr "type" "arith,load,no_delay_load") + (set_attr "mode" "HI") + (set_attr "length" "4,4,8")]) + +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] + "" + "@ + andi\t%0,%1,0x00ff + lbu%i1\t%0,%1 + lbu%i1\t%0,%1" + [(set_attr "type" "arith,load,no_delay_load") + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,4,8")]) + +;;---------------------------------------------------------------- +;; Sign extension +;;---------------------------------------------------------------- + +;; basic Sign Extend Operations + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:QI 1 "register_operand" "d")))] + "" + "sext8\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] + "" + "sext16\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +;; Those for integer source operand are ordered +;; widest source type first. + +(define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] + "" + { + if (which_alternative == 0) + output_asm_insn ("addk\t%D0,r0,%1", operands); + else + output_asm_insn ("lw%i1\t%D0,%1", operands); + + output_asm_insn ("add\t%0,%D0,%D0", operands); + output_asm_insn ("addc\t%0,r0,r0", operands); + output_asm_insn ("beqi\t%0,.+8", operands); + return "addi\t%0,r0,0xffffffff"; + } + [(set_attr "type" "multi,multi,multi") + (set_attr "mode" "DI") + (set_attr "length" "20,20,20")]) + +;;---------------------------------------------------------------- +;; Data movement +;;---------------------------------------------------------------- + +;; 64-bit integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. + +(define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + { + /* If operands[1] is a constant address illegal for pic, then we need to + handle it just like microblaze_legitimize_address does. */ + if (flag_pic && pic_address_needs_scratch (operands[1])) + { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); + DONE; + } + + + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], DImode) + && !register_operand (operands[1], DImode) + && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (DImode)))) + { + + rtx temp = force_reg (DImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } + } +) + + + +(define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m") + (match_operand:DI 1 "general_operand" " d,i,J,R,m,d,d"))] + "" + { + switch (which_alternative) + { + case 0: + return "addk\t%0,%1\n\taddk\t%D0,%d1"; + case 1: + return "addik\t%0,r0,%h1\n\taddik\t%D0,r0,%j1 #li => la"; + case 2: + return "addk\t%0,r0,r0\n\taddk\t%D0,r0,r0"; + case 3: + case 4: + if (reg_mentioned_p (operands[0], operands[1])) + return "lwi\t%D0,%o1\n\tlwi\t%0,%1"; + else + return "lwi\t%0,%1\n\tlwi\t%D0,%o1"; + case 5: + case 6: + return "swi\t%1,%0\n\tswi\t%D1,%o0"; + } + return "unreachable"; + } + [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") + (set_attr "mode" "DI") + (set_attr "length" "8,8,8,8,12,8,12")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" ""))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" + + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" ""))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. + +(define_expand "movsi" + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + { + if (microblaze_expand_move (SImode, operands)) DONE; + } +) + +;; Added for status resgisters +(define_insn "movsi_status" + [(set (match_operand:SI 0 "register_operand" "=d,d,z") + (match_operand:SI 1 "register_operand" "z,d,d"))] + "interrupt_handler" + "@ + mfs\t%0,%1 #mfs + addk\t%0,%1,r0 #add movsi + mts\t%0,%1 #mts" + [(set_attr "type" "move") + (set_attr "mode" "SI") + (set_attr "length" "12")]) + +;; This move will be not be moved to delay slot. +(define_insn "*movsi_internal3" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d") + (match_operand:SI 1 "immediate_operand" "J,I,Mnis"))] + "(register_operand (operands[0], SImode) && + (GET_CODE (operands[1]) == CONST_INT && + (INTVAL (operands[1]) <= 32767 && INTVAL (operands[1]) >= -32768)))" + "@ + addk\t%0,r0,r0 + addik\t%0,r0,%1\t# %X1 + addik\t%0,r0,%1\t# %X1" + [(set_attr "type" "arith,arith,no_delay_arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +;; This move may be used for PLT label operand +(define_insn "*movsi_internal5_pltop" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (match_operand:SI 1 "call_insn_operand" ""))] + "(register_operand (operands[0], Pmode) && + PLT_ADDR_P (operands[1]))" + { + gcc_unreachable (); + } + [(set_attr "type" "load") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "*movsi_internal2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d, d,d,R, T") + (match_operand:SI 1 "move_operand" " d,I,Mnis,R,m,dJ,dJ"))] + "(register_operand (operands[0], SImode) + || register_operand (operands[1], SImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)) + && (flag_pic != 2 || (GET_CODE (operands[1]) != SYMBOL_REF + && GET_CODE (operands[1]) != LABEL_REF))" + "@ + addk\t%0,%1,r0 + addik\t%0,r0,%1\t# %X1 + addik\t%0,%a1 + lw%i1\t%0,%1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 + sw%i0\t%z1,%0" + [(set_attr "type" "load,load,no_delay_load,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SI") + (set_attr "length" "4,4,8,4,8,4,8")]) + + +;; 16-bit Integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. +;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined + +(define_expand "movhi" + [(set (match_operand:HI 0 "nonimmediate_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + { + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], HImode) + && !register_operand (operands[1], HImode) + && ((GET_CODE (operands[1]) != CONST_INT + || INTVAL (operands[1]) != 0))) + { + rtx temp = force_reg (HImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } + } +) + +(define_insn "*movhi_internal2" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m") + (match_operand:HI 1 "general_operand" "I,d,R,m,dJ,dJ"))] + "" + "@ + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 + lhui\t%0,%1 + lhui\t%0,%1 + sh%i0\t%z1,%0 + sh%i0\t%z1,%0" + [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "HI") + (set_attr "length" "4,4,4,8,8,8")]) + +;; 8-bit Integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. +;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined + +(define_expand "movqi" + [(set (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + { + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], QImode) + && !register_operand (operands[1], QImode) + && ((GET_CODE (operands[1]) != CONST_INT + || INTVAL (operands[1]) != 0))) + { + rtx temp = force_reg (QImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } + } +) + +(define_insn "*movqi_internal2" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m") + (match_operand:QI 1 "general_operand" "J,I,d,R,m,dJ,dJ"))] + "" + "@ + addk\t%0,r0,%z1 + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 + lbu%i1\t%0,%1 + lbu%i1\t%0,%1 + sb%i0\t%z1,%0 + sbi\t%z1,%0" + [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "QI") + (set_attr "length" "4,4,8,4,8,4,8")]) + +;; Block moves, see microblaze.c for more details. +;; Argument 0 is the destination +;; Argument 1 is the source +;; Argument 2 is the length +;; Argument 3 is the alignment + +(define_expand "movmemsi" + [(parallel [(set (match_operand:BLK 0 "general_operand") + (match_operand:BLK 1 "general_operand")) + (use (match_operand:SI 2 "")) + (use (match_operand:SI 3 "const_int_operand"))])] + "" + { + if (microblaze_expand_block_move (operands[0], operands[1], + operands[2], operands[3])) + DONE; + else + FAIL; + } +) + +;; 32-bit floating point moves + +(define_expand "movsf" + [(set (match_operand:SF 0 "nonimmediate_operand" "") + (match_operand:SF 1 "general_operand" ""))] + "" + { + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], SFmode) + && !register_operand (operands[1], SFmode) + && ( ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (SFmode)))) + { + rtx temp = force_reg (SFmode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } + } +) + +;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT +;; +(define_insn "*movsf_internal" + [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,d,d,R,m") + (match_operand:SF 1 "general_operand" "G,d,R,F,m,d,d"))] + "(register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode) + || operands[1] == CONST0_RTX (SFmode))" + "@ + addk\t%0,r0,r0 + addk\t%0,%1,r0 + lw%i1\t%0,%1 + addik\t%0,r0,%F1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 + swi\t%z1,%0" + [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SF") + (set_attr "length" "4,4,4,4,4,4,4")]) + +;; 64-bit floating point moves +(define_expand "movdf" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + { + if (flag_pic == 2) { + if (GET_CODE (operands[1]) == MEM + && !microblaze_legitimate_address_p (DFmode, XEXP (operands[1],0), 0)) + { + rtx ptr_reg; + rtx result; + ptr_reg = force_reg (Pmode, XEXP (operands[1],0)); + result = gen_rtx_MEM (DFmode, ptr_reg); + emit_move_insn (operands[0], result); + DONE; + } + } + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], DFmode) + && !register_operand (operands[1], DFmode) + && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (DFmode)))) + { + rtx temp = force_reg (DFmode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } + } +) + +;; movdf_internal +;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT +;; +(define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,To") + (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] + "" + { + switch (which_alternative) + { + case 0: + return "addk\t%0,r0,r0\n\taddk\t%D0,r0,r0"; + case 1: + case 3: + if (reg_mentioned_p (operands[0], operands[1])) + return "lwi\t%D0,%o1\n\tlwi\t%0,%1"; + else + return "lwi\t%0,%1\n\tlwi\t%D0,%o1"; + case 2: + { + return "addik\t%0,r0,%h1 \n\taddik\t%D0,r0,%j1 #Xfer Lo"; + } + case 4: + return "swi\t%1,%0\n\tswi\t%D1,%o0"; + } + gcc_unreachable (); + } + [(set_attr "type" "no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") + (set_attr "mode" "DF") + (set_attr "length" "4,8,8,16,8")]) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + +;;---------------------------------------------------------------- +;; Shifts +;;---------------------------------------------------------------- + +;;---------------------------------------------------------------- +;; 32-bit left shifts +;;---------------------------------------------------------------- +(define_expand "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "")))] + "" + { + /* Avoid recursion for trivial cases. */ + if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1))) + if (microblaze_expand_shift (operands)) + DONE; + } +) + +;; Irrespective of if we have a barrel-shifter or not, we want to match +;; shifts by 1 with a special pattern. When a barrel shifter is present, +;; saves a cycle. If not, allows us to annotate the instruction for delay +;; slot optimization +(define_insn "*ashlsi3_byone" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "I")))] + "(INTVAL (operands[2]) == 1)" + "addk\t%0,%1,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +;; Barrel shift left +(define_insn "ashlsi3_bshift" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ashift:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "arith_operand" "I,d")))] + "TARGET_BARREL_SHIFT" + "@ + bslli\t%0,%1,%2 + bsll\t%0,%1,%2" + [(set_attr "type" "bshift,bshift") + (set_attr "mode" "SI,SI") + (set_attr "length" "4,4")] +) + +;; The following patterns apply when there is no barrel shifter present + +(define_insn "*ashlsi3_with_mul_delay" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL + && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" + "muli\t%0,%1,%m2" + ;; This MUL will not generate an imm. Can go into a delay slot. + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +(define_insn "*ashlsi3_with_mul_nodelay" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL" + "muli\t%0,%1,%m2" + ;; This MUL will generate an IMM. Cannot go into a delay slot + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "SI") + (set_attr "length" "8")] +) + +(define_insn "*ashlsi3_with_size_opt" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "(INTVAL (operands[2]) > 5 && optimize_size)" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + + output_asm_insn ("ori\t%3,r0,%2", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,%1,r0", operands); + + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "addk\t%0,%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "20")] +) + +(define_insn "*ashlsi3_with_rotate" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "(INTVAL (operands[2]) > 17 && !optimize_size)" + { + int i, nshift; + + nshift = INTVAL (operands[2]); + operands[3] = gen_int_mode (0xFFFFFFFF << nshift, SImode); + + /* We do one extra shift so that the first bit (carry) coming into the MSB + will be masked out */ + output_asm_insn ("src\t%0,%1", operands); + for (i = 0; i < (32 - nshift); i++) + output_asm_insn ("src\t%0,%0", operands); + + return "andi\t%0,%0,%3"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "80")] +) + +(define_insn "*ashlsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "" + { + int i; + int nshift = INTVAL (operands[2]); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + output_asm_insn ("addk\t%0,%1,%1", operands); + for (i = 0; i < (nshift - 2); i++) + output_asm_insn ("addk\t%0,%0,%0", operands); + return "addk\t%0,%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "124")] +) + +(define_insn "*ashlsi_reg" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + output_asm_insn ("andi\t%3,%2,31", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + /* Exit the loop if zero shift. */ + output_asm_insn ("beqid\t%3,.+20", operands); + /* Emit the loop. */ + output_asm_insn ("addk\t%0,%0,r0", operands); + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "addk\t%0,%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "28")] +) + + +;;---------------------------------------------------------------- +;; 32-bit right shifts +;;---------------------------------------------------------------- +(define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "")))] + "" + { + /* Avoid recursion for trivial cases. */ + if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1))) + if (microblaze_expand_shift (operands)) + DONE; + } +) + +;; Irrespective of if we have a barrel-shifter or not, we want to match +;; shifts by 1 with a special pattern. When a barrel shifter is present, +;; saves a cycle. If not, allows us to annotate the instruction for delay +;; slot optimization +(define_insn "*ashrsi3_byone" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "I")))] + "(INTVAL (operands[2]) == 1)" + "sra\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +;; Barrel shift right logical +(define_insn "*ashrsi3_bshift" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "arith_operand" "I,d")))] + "TARGET_BARREL_SHIFT" + "@ + bsrai\t%0,%1,%2 + bsra\t%0,%1,%2" + [(set_attr "type" "bshift,bshift") + (set_attr "mode" "SI,SI") + (set_attr "length" "4,4")] +) + +(define_insn "*ashrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "" + { + int i; + int nshift = INTVAL (operands[2]); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + output_asm_insn ("sra\t%0,%1", operands); + for (i = 0; i < (nshift - 2); i++) + output_asm_insn ("sra\t%0,%0", operands); + return "sra\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "124")] +) + +(define_insn "*ashlri_reg" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + output_asm_insn ("andi\t%3,%2,31", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + /* Exit the loop if zero shift. */ + output_asm_insn ("beqid\t%3,.+20", operands); + /* Emit the loop. */ + output_asm_insn ("addk\t%0,%0,r0", operands); + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "sra\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "28")] +) + +;;---------------------------------------------------------------- +;; 32-bit right shifts (logical) +;;---------------------------------------------------------------- + +(define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "")))] + "" + { + /* Avoid recursion for trivial cases. */ + if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1))) + if (microblaze_expand_shift (operands)) + DONE; + } +) + +;; Irrespective of if we have a barrel-shifter or not, we want to match +;; shifts by 1 with a special pattern. When a barrel shifter is present, +;; saves a cycle. If not, allows us to annotate the instruction for delay +;; slot optimization +(define_insn "*lshrsi3_byone" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "I")))] + "(INTVAL (operands[2]) == 1)" + "srl\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +;; Barrel shift right logical +(define_insn "*lshrsi3_bshift" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "arith_operand" "I,d")))] + "TARGET_BARREL_SHIFT" + "@ + bsrli\t%0,%1,%2 + bsrl\t%0,%1,%2" + [(set_attr "type" "bshift,bshift") + (set_attr "mode" "SI,SI") + (set_attr "length" "4,4")] +) + +(define_insn "*lshrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "" + { + int i; + int nshift = INTVAL (operands[2]); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + output_asm_insn ("srl\t%0,%1", operands); + for (i = 0; i < (nshift - 2); i++) + output_asm_insn ("srl\t%0,%0", operands); + return "srl\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "124")] +) + +(define_insn "*lshlri_reg" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + output_asm_insn ("andi\t%3,%2,31", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,r0,%1", operands); + /* Exit the loop if zero shift. */ + output_asm_insn ("beqid\t%3,.+20", operands); + /* Emit the loop. */ + output_asm_insn ("addk\t%0,%0,r0", operands); + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "srl\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "28")] +) + +;;---------------------------------------------------------------- +;; Setting a register from an integer comparison. +;;---------------------------------------------------------------- +(define_expand "cstoresi4" + [(set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand")]))] + "TARGET_PATTERN_COMPARE" + "if (GET_CODE (operand1) != EQ && GET_CODE (operand1) != NE) + FAIL; + " +) + +(define_insn "seq_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI + (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_PATTERN_COMPARE" + "pcmpeq\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +(define_insn "sne_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (ne:SI + (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_PATTERN_COMPARE" + "pcmpne\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")] +) + +(define_insn "signed_compare" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))] + "" + "cmp\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +(define_insn "unsigned_compare" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))] + "" + "cmpu\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +;;---------------------------------------------------------------- +;; Setting a register from an floating point comparison. +;;---------------------------------------------------------------- +(define_insn "cstoresf4" + [(set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:SF 2 "register_operand") + (match_operand:SF 3 "register_operand")]))] + "TARGET_HARD_FLOAT" + "fcmp.%C1\t%0,%3,%2" + [(set_attr "type" "fcmp") + (set_attr "mode" "SF") + (set_attr "length" "4")] +) + +;;---------------------------------------------------------------- +;; Conditional branches +;;---------------------------------------------------------------- + +(define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand") + (match_operand:SI 2 "arith_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +{ + microblaze_expand_conditional_branch (SImode, operands); + DONE; +}) + +(define_expand "cbranchsf4" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" + [(match_operand:SF 1 "register_operand") + (match_operand:SF 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "TARGET_HARD_FLOAT" +{ + microblaze_expand_conditional_branch_sf (operands); + DONE; + +}) + +;; Used to implement comparison instructions +(define_expand "condjump" + [(set (pc) + (if_then_else (match_operand 0) + (label_ref (match_operand 1)) + (pc)))]) + +(define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand" "d") + (const_int 0)]) + (match_operand:SI 2 "pc_or_label_operand" "") + (match_operand:SI 3 "pc_or_label_operand" ""))) + ] + "" + { + if (operands[3] == pc_rtx) + return "b%C0i%?\t%z1,%2"; + else + return "b%N0i%?\t%z1,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "4")] +) + +;;---------------------------------------------------------------- +;; Unconditional branches +;;---------------------------------------------------------------- +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + { + if (GET_CODE (operands[0]) == REG) + return "br%?\t%0"; + else + return "bri%?\t%l0"; + } + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_expand "indirect_jump" + [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + { + rtx dest = operands[0]; + if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) + operands[0] = copy_to_mode_reg (Pmode, dest); + + emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); + DONE; + } +) + +;; Indirect jumps. Jump to register values. Assuming absolute jumps + +(define_insn "indirect_jump_internal1" + [(set (pc) (match_operand:SI 0 "register_operand" "d"))] + "" + "bra%?\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_expand "tablejump" + [(set (pc) + (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + { + gcc_assert (GET_MODE (operands[0]) == Pmode); + + if (!flag_pic) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); + else + emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); + DONE; + } +) + +(define_insn "tablejump_internal1" + [(set (pc) + (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_expand "tablejump_internal3" + [(parallel [(set (pc) + (plus:SI (match_operand:SI 0 "register_operand" "d") + (label_ref:SI (match_operand:SI 1 "" "")))) + (use (label_ref:SI (match_dup 1)))])] + "" + "" +) + +;; need to change for MicroBlaze PIC +(define_insn "" + [(set (pc) + (plus:SI (match_operand:SI 0 "register_operand" "d") + (label_ref:SI (match_operand 1 "" "")))) + (use (label_ref:SI (match_dup 1)))] + "next_active_insn (insn) != 0 + && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC + && PREV_INSN (next_active_insn (insn)) == operands[1] + && flag_pic" + { + output_asm_insn ("addk\t%0,%0,r20",operands); + return "bra%?\t%0"; +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_expand "tablejump_internal4" + [(parallel [(set (pc) + (plus:DI (match_operand:DI 0 "register_operand" "d") + (label_ref:DI (match_operand:SI 1 "" "")))) + (use (label_ref:DI (match_dup 1)))])] + "" + "" +) + +;;---------------------------------------------------------------- +;; Function prologue/epilogue and stack allocation +;;---------------------------------------------------------------- +(define_expand "prologue" + [(const_int 1)] + "" + { + microblaze_expand_prologue (); + DONE; + } +) + +(define_expand "epilogue" + [(use (const_int 0))] + "" + { + microblaze_expand_epilogue (); + DONE; + } +) + +;; An insn to allocate new stack space for dynamic use (e.g., alloca). +;; We copy the return address, decrement the stack pointer and save the +;; return address again at the new stack top + +(define_expand "allocate_stack" + [(set (match_operand 0 "register_operand" "=r") + (minus (reg 1) (match_operand 1 "register_operand" ""))) + (set (reg 1) + (minus (reg 1) (match_dup 1)))] + "" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx rtmp = gen_rtx_REG (SImode, R_TMP); + rtx neg_op0; + + emit_move_insn (rtmp, retaddr); + if (GET_CODE (operands[1]) != CONST_INT) + { + neg_op0 = gen_reg_rtx (Pmode); + emit_insn (gen_negsi2 (neg_op0, operands[1])); + } else + neg_op0 = GEN_INT (- INTVAL (operands[1])); + + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); + emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp); + emit_move_insn (operands[0], virtual_stack_dynamic_rtx); + emit_insn (gen_rtx_CLOBBER (SImode, rtmp)); + DONE; + } +) + +;; Trivial return. Make it look like a normal return insn as that +;; allows jump optimizations to work better . +(define_insn "return" + [(return)] + "microblaze_can_use_return_insn ()" + { + if (microblaze_is_interrupt_handler ()) + return "rtid\tr14, 0\;%#"; + else + return "rtsd\tr15, 8\;%#"; + } + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +;; Normal return. +;; We match any mode for the return address, so that this will work with +;; both 32 bit and 64 bit targets. + +(define_insn "return_internal" + [(parallel [(use (match_operand:SI 0 "register_operand" "")) + (return)])] + "" + { + if (microblaze_is_interrupt_handler ()) + return "rtid\tr14,0 \;%#"; + else + return "rtsd\tr15,8 \;%#"; + } + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "4")]) + + +;; Block any insns from across this point +;; Useful to group sequences together. +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "" + [(set_attr "type" "unknown") + (set_attr "mode" "none") + (set_attr "length" "0")]) + + +;;---------------------------------------------------------------- +;; Function calls +;;---------------------------------------------------------------- + +(define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) + (clobber (reg:SI R_SR)) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" ""))])] + "" + { + rtx addr = XEXP (operands[0], 0); + + if (flag_pic == 2 && GET_CODE (addr) == SYMBOL_REF + && !SYMBOL_REF_LOCAL_P (addr)) + { + rtx temp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PLT); + XEXP (operands[0], 0) = temp; + } + + if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr)) + || !call_insn_operand (addr, VOIDmode)) + XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); + + if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) + emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], + gen_rtx_REG (SImode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_internal0 (operands[0], operands[1], + gen_rtx_REG (SImode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; + } +) + +(define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) + (clobber (match_operand:SI 2 "" ""))])] + "" + { + } +) + +(define_expand "call_internal_plt0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) + (clobber (match_operand:SI 2 "" "")) + (use (match_operand:SI 3 "" ""))])] + "" + { + } +) + +(define_insn "call_internal_plt" + [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) + (match_operand:SI 1 "" "i")) + (clobber (reg:SI R_SR)) + (use (reg:SI R_GOT))] + "flag_pic" + { + register rtx target2 = gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); + gen_rtx_CLOBBER (VOIDmode, target2); + return "brlid\tr15,%0\;%#"; + } + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_insn "call_internal1" + [(call (mem (match_operand:SI 0 "call_insn_operand" "ri")) + (match_operand:SI 1 "" "i")) + (clobber (reg:SI R_SR))] + "" + { + register rtx target = operands[0]; + register rtx target2 = gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); + if (GET_CODE (target) == SYMBOL_REF) { + gen_rtx_CLOBBER (VOIDmode, target2); + return "brlid\tr15,%0\;%#"; + } else if (GET_CODE (target) == CONST_INT) + return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; + else if (GET_CODE (target) == REG) + return "brald\tr15,%0\;%#"; + else { + fprintf (stderr,"Unsupported call insn\n"); + return NULL; + } + } + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +;; calls.c now passes a fourth argument, make saber happy + +(define_expand "call_value" + [(parallel [(set (match_operand 0 "register_operand" "=d") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) + (clobber (reg:SI R_SR)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + { + rtx addr = XEXP (operands[1], 0); + + if (flag_pic == 2 && GET_CODE (addr) == SYMBOL_REF + && !SYMBOL_REF_LOCAL_P (addr)) + { + rtx temp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PLT); + XEXP (operands[1], 0) = temp; + } + + if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr)) + || !call_insn_operand (addr, VOIDmode)) + XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); + + if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) + emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], + operands[2], + gen_rtx_REG (SImode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_value_internal (operands[0], operands[1], + operands[2], + gen_rtx_REG (SImode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; + } +) + + +(define_expand "call_value_internal" + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) + (clobber (match_operand:SI 3 "" "")) + ])] + "" + {} +) + +(define_expand "call_value_intern_plt0" + [(parallel[(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) + (clobber (match_operand:SI 3 "" "")) + (use (match_operand:SI 4 "" ""))])] + "flag_pic" + {} +) + +(define_insn "call_value_intern_plt" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) + (match_operand:SI 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d")) + (use (match_operand:SI 4 "register_operand"))] + "flag_pic" + { + register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); + + gen_rtx_CLOBBER (VOIDmode,target2); + return "brlid\tr15,%1\;%#"; + } + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +(define_insn "call_value_intern" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) + (match_operand:SI 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "" + { + register rtx target = operands[1]; + register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); + + if (GET_CODE (target) == SYMBOL_REF){ + gen_rtx_CLOBBER (VOIDmode,target2); + return "brlid\tr15,%1\;%#"; + } + else if (GET_CODE (target) == CONST_INT) + return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; + else if (GET_CODE (target) == REG) + return "brald\tr15,%1\;%#"; + else + return "Unsupported call insn\n"; + } + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "4")]) + + +;; Call subroutine returning any type. +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + { + if (operands[0]) /* silence statement not reached warnings */ + { + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + emit_insn (gen_blockage ()); + DONE; + } + } +) + +;;---------------------------------------------------------------- +;; Misc. +;;---------------------------------------------------------------- + +(define_insn "nop" + [(const_int 0)] + "" + "nop" + [(set_attr "type" "nop") + (set_attr "mode" "none") + (set_attr "length" "4")]) + +;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference +;; between "mfs" and "addik" instructions. +(define_insn "set_got" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] + "" + "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" + [(set_attr "type" "multi") + (set_attr "length" "12")]) + diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt new file mode 100644 index 00000000000..45b2b170bc9 --- /dev/null +++ b/gcc/config/microblaze/microblaze.opt @@ -0,0 +1,97 @@ +; Options for the MicroBlaze port of the compiler +; +; Copyright 2009, 2010 Free Software Foundation, Inc. +; +; Contributed by Michael Eager <eager@eagercon.com>. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT +; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +; License for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. */ + +msoft-float +Target Report RejectNegative Mask(SOFT_FLOAT) +Use software emulation for floating point (default) + +mhard-float +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Use hardware floating point instructions + +msmall-divides +Target Mask(SMALL_DIVIDES) +Use table lookup optimization for small signed integer divisions + +mcpu= +Target RejectNegative Joined Var(microblaze_select_cpu) +-mcpu=PROCESSOR Use features of and schedule code for given CPU + +mmemcpy +Target Mask(MEMCPY) +Don't optimize block moves, use memcpy + +mxl-soft-mul +Target Mask(SOFT_MUL) +Use the soft multiply emulation (default) + +mxl-soft-div +Target Mask(SOFT_DIV) +Use the software emulation for divides (default) + +mxl-barrel-shift +Target Mask(BARREL_SHIFT) +Use the hardware barrel shifter instead of emulation + +mxl-pattern-compare +Target Mask(PATTERN_COMPARE) +Use pattern compare instructions + +mxl-stack-check +Target Mask(STACK_CHECK) +Check for stack overflow at runtime + +mxl-gp-opt +Target Mask(XLGPOPT) +Use GP relative sdata/sbss sections + +mno-clearbss +Target RejectNegative +Clear the BSS to zero and place zero initialized in BSS + +mxl-multiply-high +Target Mask(MULTIPLY_HIGH) +Use multiply high instructions for high part of 32x32 multiply + +mxl-float-convert +Target Mask(FLOAT_CONVERT) +Use hardware floating point converstion instructions + +mxl-float-sqrt +Target Mask(FLOAT_SQRT) +Use hardware floating point square root instruction + +mxl-mode-executable +Target Mask(XL_MODE_EXECUTABLE) +Description for mxl-mode-executable + +mxl-mode-xmdstub +Target Mask(XL_MODE_XMDSTUB) +Description for mxl-mode-xmdstub + +mxl-mode-bootstrap +Target Mask(XL_MODE_BOOTSTRAP) +Description for mxl-mode-bootstrap + +mxl-mode-novectors +Target Mask(XL_MODE_NOVECTORS) +Description for mxl-mode-novectors diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md new file mode 100644 index 00000000000..ea2f1f0805f --- /dev/null +++ b/gcc/config/microblaze/predicates.md @@ -0,0 +1,64 @@ +;; Predicate definitions for Xilinx MicroBlaze +;; Copyright 2009, 2010 Free Software Foundation, Inc. +;; +;; Contributed by Michael Eager <eager@eagercon.com>. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + + +;; Return whether OP can be used as an operands in arithmetic. +(define_predicate "arith_operand" + (ior (match_code "const_int,const_double") + (match_operand 0 "register_operand"))) + +(define_predicate "arith_operand32" + (ior (match_operand 0 "register_operand") + (and (match_code "const_int,const_double") + (match_test "LARGE_INT (op)")))) + +(define_predicate "const_0_operand" + (and (match_code "const_int,const_double") + (match_test "op == CONST0_RTX (GET_MODE (op))"))) + +;; Return whether OP is a register or the constant 0. +(define_predicate "reg_or_0_operand" + (ior (match_operand 0 "const_0_operand") + (match_operand 0 "register_operand"))) + +;; Return if the operand is either the PC or a label_ref. +(define_special_predicate "pc_or_label_operand" + (ior (match_code "pc,label_ref") + (and (match_code "symbol_ref") + (match_test "!(strcmp ((XSTR (op, 0)), \"_stack_overflow_exit\"))")))) + +;; Test for valid call operand +(define_predicate "call_insn_operand" + (match_test "CALL_INSN_OP (op)")) + +;; Return if OPERAND is valid as a source operand for a move instruction. +(define_predicate "move_operand" + (and ( + not ( + and (match_code "plus") + (not (match_test "(GET_CODE (XEXP (op, 0)) == REG) ^ (GET_CODE (XEXP (op,1)) == REG)")) + ) + ) + (match_operand 0 "general_operand"))) + +;; Test for valid PIC call operand +(define_predicate "call_insn_plt_operand" + (match_test "PLT_ADDR_P (op)")) diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze new file mode 100644 index 00000000000..021dbbe3e76 --- /dev/null +++ b/gcc/config/microblaze/t-microblaze @@ -0,0 +1,33 @@ +# For C++ crtstuff +EXTRA_MULTILIB_PARTS = crtbegin$(objext) crtend$(objext) + +EXTRA_PARTS += crti$(objext) crtn$(objext) + +MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high +MULTILIB_DIRNAMES = bs m mh +MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + +# Extra files +microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ + $(srcdir)/config/microblaze/microblaze-protos.h \ + $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) $(TM_P_H) $(TREE_H) errors.h $(TM_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/microblaze/microblaze-c.c + +# Build soft FP routines. +FPBIT = fp-bit.c +DPBIT = dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +# Assemble startup files +$(T)crti$(objext): $(srcdir)/config/microblaze/crti.s + $(GCC_FOR_TARGET) -c $(srcdir)/config/microblaze/crti.s -o $(T)crti$(objext) + +$(T)crtn$(objext): $(srcdir)/config/microblaze/crtn.s + $(GCC_FOR_TARGET) -c $(srcdir)/config/microblaze/crtn.s -o $(T)crtn$(objext) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 56e4f2da16f..95994cfc7a9 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -15442,11 +15442,6 @@ mips_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - case OPT_mabi_: if (strcmp (arg, "32") == 0) mips_abi = ABI_32; @@ -15527,7 +15522,7 @@ mips_option_override (void) TARGET_INTERLINK_MIPS16 = 1; /* Set the small data limit. */ - mips_small_data_threshold = (g_switch_set + mips_small_data_threshold = (global_options_set.x_g_switch_value ? g_switch_value : MIPS_DEFAULT_GVALUE); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 4f44130c5a5..23dba7c7153 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -26,6 +26,12 @@ along with GCC; see the file COPYING3. If not see #include "config/vxworks-dummy.h" +#ifdef GENERATOR_FILE +/* This is used in some insn conditions, so needs to be declared, but + does not need to be defined. */ +extern int target_flags_explicit; +#endif + /* MIPS external variables defined in mips.c. */ /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), @@ -1736,6 +1742,9 @@ enum mips_code_readable_setting { #define HARD_FRAME_POINTER_REGNUM \ (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) +#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 +#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 + /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h index 5908a754284..b4fc856fbaa 100644 --- a/gcc/config/mmix/mmix.h +++ b/gcc/config/mmix/mmix.h @@ -140,8 +140,6 @@ struct GTY(()) machine_function } \ while (0) -extern int target_flags; - #define TARGET_DEFAULT \ (MASK_BRANCH_PREDICT | MASK_BASE_ADDRESSES | MASK_USE_RETURN_INSN) diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 754d27adc06..e114dd1fc14 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -520,7 +520,7 @@ pa_option_override (void) call frame information. There is no benefit in using this optimization on PA8000 and later processors. */ if (pa_cpu >= PROCESSOR_8000 - || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) + || (targetm.except_unwind_info () == UI_DWARF2 && flag_exceptions) || flag_unwind_tables) target_flags &= ~MASK_JUMP_IN_DELAY; @@ -5762,7 +5762,7 @@ static reg_class_t pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, enum machine_mode mode, secondary_reload_info *sri) { - int is_symbolic, regno; + int regno; enum reg_class rclass = (enum reg_class) rclass_i; /* Handle the easy stuff first. */ @@ -5796,6 +5796,23 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, return NO_REGS; } + /* Secondary reloads of symbolic operands require %r1 as a scratch + register when we're generating PIC code and when the operand isn't + readonly. */ + if (symbolic_expression_p (x)) + { + if (GET_CODE (x) == HIGH) + x = XEXP (x, 0); + + if (flag_pic || !read_only_operand (x, VOIDmode)) + { + gcc_assert (mode == SImode || mode == DImode); + sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 + : CODE_FOR_reload_indi_r1); + return NO_REGS; + } + } + /* Profiling showed the PA port spends about 1.3% of its compilation time in true_regnum from calls inside pa_secondary_reload_class. */ if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) @@ -5858,51 +5875,9 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER && (REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (rclass))) - { - sri->icode = (in_p - ? direct_optab_handler (reload_in_optab, mode) - : direct_optab_handler (reload_out_optab, mode)); - return NO_REGS; - } - - /* Secondary reloads of symbolic operands require %r1 as a scratch - register when we're generating PIC code and when the operand isn't - readonly. */ - if (GET_CODE (x) == HIGH) - x = XEXP (x, 0); - - /* Profiling has showed GCC spends about 2.6% of its compilation - time in symbolic_operand from calls inside pa_secondary_reload_class. - So, we use an inline copy to avoid useless work. */ - switch (GET_CODE (x)) - { - rtx op; - - case SYMBOL_REF: - is_symbolic = !SYMBOL_REF_TLS_MODEL (x); - break; - case LABEL_REF: - is_symbolic = 1; - break; - case CONST: - op = XEXP (x, 0); - is_symbolic = (GET_CODE (op) == PLUS - && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF - && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) - || GET_CODE (XEXP (op, 0)) == LABEL_REF) - && GET_CODE (XEXP (op, 1)) == CONST_INT); - break; - default: - is_symbolic = 0; - break; - } - - if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode))) - { - gcc_assert (mode == SImode || mode == DImode); - sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 - : CODE_FOR_reload_indi_r1); - } + sri->icode = (in_p + ? direct_optab_handler (reload_in_optab, mode) + : direct_optab_handler (reload_out_optab, mode)); return NO_REGS; } diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index 332e99db245..a1a96a17677 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -767,7 +767,6 @@ extern int may_call_alloca; pdp11_register_move_cost (CLASS1, CLASS2) /* Tell emit-rtl.c how to initialize special values on a per-function base. */ -extern int optimize; extern struct rtx_def *cc0_reg_rtx; #define CC_STATUS_MDEP rtx diff --git a/gcc/config/picochip/picochip.c b/gcc/config/picochip/picochip.c index 9bd2382915b..50748edc898 100644 --- a/gcc/config/picochip/picochip.c +++ b/gcc/config/picochip/picochip.c @@ -358,6 +358,11 @@ picochip_option_override (void) if (optimize >= 1) flag_section_anchors = 1; + /* Exception flags are irrelevant to picochip. It causes failure in libgcc + functions. */ + flag_non_call_exceptions = 0; + flag_exceptions = 0; + /* Turn off the second scheduling pass, and move it to picochip_reorg, to avoid having the second jump optimisation trash the instruction modes (e.g., instructions are changed to @@ -1637,6 +1642,18 @@ picochip_output_internal_label (FILE * stream, const char *prefix, sprintf (picochip_current_vliw_state.lm_label_name, "picoMark_%s%ld", prefix, num); } + else if (picochip_schedule_type == DFA_TYPE_SPEED && + (strcmp (prefix, "LCFI")) == 0 && picochip_vliw_continuation) + { + if (picochip_current_vliw_state.num_cfi_labels_deferred == 2) + { + internal_error ("LCFI labels have already been deferred."); + } + sprintf(picochip_current_vliw_state.cfi_label_name[ + picochip_current_vliw_state.num_cfi_labels_deferred], + "picoMark_%s%ld", prefix, num); + picochip_current_vliw_state.num_cfi_labels_deferred++; + } else { /* Marker label. */ diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 0bf781e853f..b4134e6214e 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -24,6 +24,10 @@ #undef TARGET_AIX #define TARGET_AIX 1 +/* Linux64.h wants to redefine TARGET_AIX based on -m64, but it can't be used + in the #if conditional in options-default.h, so provide another macro. */ +#define TARGET_AIX_OS 1 + /* AIX always has a TOC. */ #define TARGET_NO_TOC 0 #define TARGET_TOC 1 @@ -207,13 +211,6 @@ /* And similarly for general purpose registers. */ #define GP_SAVE_INLINE(FIRST_REG) ((FIRST_REG) < 32) -/* __throw will restore its own return address to be the same as the - return address of the function that the throw is being made to. - This is unfortunate, because we want to check the original - return address to see if we need to restore the TOC. - So we have to squirrel it away with this. */ -#define SETUP_FRAME_ADDRESSES() rs6000_aix_emit_builtin_unwind_init () - /* If the current unwind info (FS) does not contain explicit info saving R2, then we have to do a minor amount of code reading to figure out if it was saved. The big problem here is that the diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 62eed2edc28..b233261286c 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -305,14 +305,6 @@ extern enum rs6000_cmodel cmodel; #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ (!(FIRST) ? upward : FUNCTION_ARG_PADDING (MODE, TYPE)) -/* __throw will restore its own return address to be the same as the - return address of the function that the throw is being made to. - This is unfortunate, because we want to check the original - return address to see if we need to restore the TOC. - So we have to squirrel it away with this. */ -#define SETUP_FRAME_ADDRESSES() \ - do { if (TARGET_64BIT) rs6000_aix_emit_builtin_unwind_init (); } while (0) - /* Override svr4.h */ #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index 7e117d731da..eb39e0d02d2 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -27,7 +27,7 @@ /* This header needs to be included after any other headers affecting TARGET_DEFAULT. */ -#if TARGET_AIX +#if TARGET_AIX_OS #define OPT_64 "maix64" #define OPT_32 "maix32" #else diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index a5e055ed3cf..0678fc0d189 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -163,7 +163,6 @@ extern int rs6000_trampoline_size (void); extern alias_set_type get_TOC_alias_set (void); extern void rs6000_emit_prologue (void); extern void rs6000_emit_load_toc_table (int); -extern void rs6000_aix_emit_builtin_unwind_init (void); extern unsigned int rs6000_dbx_register_number (unsigned int); extern void rs6000_emit_epilogue (int); extern void rs6000_emit_eh_reg_restore (rtx, rtx); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5a3e333ffbe..030bb615f0c 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3996,11 +3996,6 @@ rs6000_handle_option (size_t code, const char *arg, int value) switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - break; - case OPT_mno_power: target_flags &= ~(MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING); @@ -4425,7 +4420,7 @@ rs6000_file_start (void) if (rs6000_sdata && g_switch_value) { - fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, + fprintf (file, "%s -G %d", start, g_switch_value); start = ""; } @@ -5416,7 +5411,7 @@ small_data_operand (rtx op ATTRIBUTE_UNUSED, /* We have to be careful here, because it is the referenced address that must be 32k from _SDA_BASE_, not just the symbol. */ summand = INTVAL (XEXP (sum, 1)); - if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) + if (summand < 0 || summand > g_switch_value) return 0; sym_ref = XEXP (sum, 0); @@ -18916,42 +18911,6 @@ rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label) fprintf (asm_out_file, "\t.ref %s\n", TARGET_STRIP_NAME_ENCODING (frame_table_label)); } - -/* If _Unwind_* has been called from within the same module, - toc register is not guaranteed to be saved to 40(1) on function - entry. Save it there in that case. */ - -void -rs6000_aix_emit_builtin_unwind_init (void) -{ - rtx mem; - rtx stack_top = gen_reg_rtx (Pmode); - rtx opcode_addr = gen_reg_rtx (Pmode); - rtx opcode = gen_reg_rtx (SImode); - rtx tocompare = gen_reg_rtx (SImode); - rtx no_toc_save_needed = gen_label_rtx (); - - mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx); - emit_move_insn (stack_top, mem); - - mem = gen_frame_mem (Pmode, - gen_rtx_PLUS (Pmode, stack_top, - GEN_INT (2 * GET_MODE_SIZE (Pmode)))); - emit_move_insn (opcode_addr, mem); - emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); - emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 - : 0xE8410028, SImode)); - - do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, - SImode, NULL_RTX, NULL_RTX, - no_toc_save_needed, -1); - - mem = gen_frame_mem (Pmode, - gen_rtx_PLUS (Pmode, stack_top, - GEN_INT (5 * GET_MODE_SIZE (Pmode)))); - emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); - emit_label (no_toc_save_needed); -} /* This ties together stack memory (MEM with an alias set of frame_alias_set) and the change to the stack pointer. */ @@ -20237,22 +20196,6 @@ rs6000_emit_prologue (void) { unsigned int i, regno; - /* In AIX ABI we need to pretend we save r2 here. */ - if (TARGET_AIX) - { - rtx addr, reg, mem; - - reg = gen_rtx_REG (reg_mode, 2); - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (sp_offset + 5 * reg_size)); - mem = gen_frame_mem (reg_mode, addr); - - insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, - NULL_RTX, NULL_RTX); - PATTERN (insn) = gen_blockage (); - } - for (i = 0; ; ++i) { regno = EH_RETURN_DATA_REGNO (i); @@ -20266,6 +20209,53 @@ rs6000_emit_prologue (void) } } + /* In AIX ABI we need to make sure r2 is really saved. */ + if (TARGET_AIX && crtl->calls_eh_return) + { + rtx tmp_reg, tmp_reg_si, compare_result, toc_save_done, jump; + long toc_restore_insn; + + gcc_assert (frame_reg_rtx == frame_ptr_rtx + || frame_reg_rtx == sp_reg_rtx); + tmp_reg = gen_rtx_REG (Pmode, 11); + tmp_reg_si = gen_rtx_REG (SImode, 11); + if (using_static_chain_p) + emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg); + gcc_assert (saving_GPRs_inline && saving_FPRs_inline); + emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO)); + /* Peek at instruction to which this function returns. If it's + restoring r2, then we know we've already saved r2. We can't + unconditionally save r2 because the value we have will already + be updated if we arrived at this function via a plt call or + toc adjusting stub. */ + emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg)); + toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028; + toc_restore_insn = (toc_restore_insn ^ 0x80000000) - 0x80000000; + emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, + GEN_INT (toc_restore_insn & ~0xffff))); + compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO); + validate_condition_mode (EQ, CCUNSmode); + emit_insn (gen_rtx_SET (VOIDmode, compare_result, + gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, + GEN_INT (toc_restore_insn + & 0xffff)))); + toc_save_done = gen_label_rtx (); + jump = gen_rtx_IF_THEN_ELSE (VOIDmode, + gen_rtx_EQ (VOIDmode, compare_result, + const0_rtx), + gen_rtx_LABEL_REF (VOIDmode, toc_save_done), + pc_rtx); + jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump)); + JUMP_LABEL (jump) = toc_save_done; + LABEL_NUSES (toc_save_done) += 1; + + emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, 2, + sp_offset + 5 * reg_size, info->total_size); + emit_label (toc_save_done); + if (using_static_chain_p) + emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0)); + } + /* Save CR if we use any that must be preserved. */ if (!WORLD_SAVE_P (info) && info->cr_save_p) { @@ -24839,7 +24829,7 @@ rs6000_elf_in_small_data_p (const_tree decl) HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); if (size > 0 - && (unsigned HOST_WIDE_INT) size <= g_switch_value + && size <= g_switch_value /* If it's not public, and we're not going to reference it there, there's no need to put it in the small data section. */ && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 24edf6cb98c..c2f47f2c12c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -46,6 +46,10 @@ #define TARGET_AIX 0 #endif +#ifndef TARGET_AIX_OS +#define TARGET_AIX_OS 0 +#endif + /* Control whether function entry points use a "dot" symbol when ABI_AIX. */ #define DOT_SYMBOLS 1 @@ -471,7 +475,6 @@ extern int rs6000_float_gprs; extern int rs6000_alignment_flags; extern const char *rs6000_sched_insert_nops_str; extern enum rs6000_nop_insertion rs6000_sched_insert_nops; -extern int rs6000_xilinx_fpu; /* Describe which vector unit to use for a given machine mode. */ enum rs6000_vector { @@ -2417,9 +2420,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ /* #define MACHINE_no_sched_speculative_load */ /* General flags. */ -extern int flag_pic; -extern int optimize; -extern int flag_expensive_optimizations; extern int frame_pointer_needed; /* Classification of the builtin functions to properly set the declaration tree diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 659bcb6d324..bdfbf782c45 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -188,7 +188,7 @@ msched-epilog Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) msched-prolog -Target Report Var(TARGET_SCHED_PROLOG) VarExists +Target Report Var(TARGET_SCHED_PROLOG) Schedule the start and end of the procedure maix-struct-return @@ -196,7 +196,7 @@ Target Report RejectNegative Var(aix_struct_return) Return all structures in memory (AIX default) msvr4-struct-return -Target Report RejectNegative Var(aix_struct_return,0) VarExists +Target Report RejectNegative Var(aix_struct_return,0) Return small structures in registers (SVR4 default) mxl-compat @@ -228,7 +228,7 @@ Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Do not place symbol+offset constants in TOC msum-in-toc -Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists +Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Place symbol+offset constants in TOC ; Output only one TOC entry per module. Normally linking fails if diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 69e9e82f570..25584b2f502 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -81,7 +81,7 @@ extern const char *rs6000_tls_size_string; /* For -mtls-size= */ #define SUBTARGET_OVERRIDE_OPTIONS \ do { \ - if (!g_switch_set) \ + if (!global_options_set.x_g_switch_value) \ g_switch_value = SDATA_DEFAULT_SIZE; \ \ if (rs6000_abi_name == NULL) \ diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 1b23835959f..007d8708818 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Vxworks PowerPC version. - Copyright (C) 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2009 + Copyright (C) 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2009, 2010 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. @@ -37,8 +37,6 @@ along with GCC; see the file COPYING3. If not see builtin_define ("__PPC__"); \ builtin_define ("__EABI__"); \ builtin_define ("__ELF__"); \ - builtin_define ("__vxworks"); \ - builtin_define ("__VXWORKS__"); \ if (!TARGET_SOFT_FLOAT) \ builtin_define ("__hardfp"); \ \ @@ -141,7 +139,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC rs6000_float_gprs = 1; \ } \ \ - if (!g_switch_set) \ + if (!global_options_set.x_g_switch_value) \ g_switch_value = SDATA_DEFAULT_SIZE; \ VXWORKS_OVERRIDE_OPTIONS; \ } while (0) diff --git a/gcc/config/s390/2084.md b/gcc/config/s390/2084.md index bedc5c322ba..bd0e27194b5 100644 --- a/gcc/config/s390/2084.md +++ b/gcc/config/s390/2084.md @@ -168,12 +168,12 @@ (define_insn_reservation "x_fsimpdf" 6 (and (eq_attr "cpu" "z990,z9_109") - (eq_attr "type" "fsimpdf,fmuldf,fhex")) + (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex")) "x_e1_t,x-wr-fp") (define_insn_reservation "x_fsimpsf" 6 (and (eq_attr "cpu" "z990,z9_109") - (eq_attr "type" "fsimpsf,fmulsf,fhex")) + (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex")) "x_e1_t,x-wr-fp") diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md index fa61038e763..d138ebb4d3e 100644 --- a/gcc/config/s390/2097.md +++ b/gcc/config/s390/2097.md @@ -463,12 +463,12 @@ (define_insn_reservation "z10_fsimpdf" 6 (and (eq_attr "cpu" "z10") - (eq_attr "type" "fsimpdf,fmuldf")) + (eq_attr "type" "fsimpdf,fmuldf,fmadddf")) "z10_e1_BOTH, z10_Gate_FP") (define_insn_reservation "z10_fsimpsf" 6 (and (eq_attr "cpu" "z10") - (eq_attr "type" "fsimpsf,fmulsf")) + (eq_attr "type" "fsimpsf,fmulsf,fmaddsf")) "z10_e1_BOTH, z10_Gate_FP") (define_insn_reservation "z10_fmultf" 52 diff --git a/gcc/config/s390/2817.md b/gcc/config/s390/2817.md new file mode 100644 index 00000000000..9bd4e1a449c --- /dev/null +++ b/gcc/config/s390/2817.md @@ -0,0 +1,313 @@ +;; Scheduling description for z196 (cpu 2817). +;; Copyright (C) 2010 +;; Free Software Foundation, Inc. +;; Contributed by Christian Borntraeger (Christian.Borntraeger@de.ibm.com) +;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "z196_ipu") + +;; Fetch + Decoder +(define_cpu_unit "z196_g1" "z196_ipu") +(define_cpu_unit "z196_g2" "z196_ipu") +(define_cpu_unit "z196_g3" "z196_ipu") +(define_cpu_unit "z196_cr1" "z196_ipu") +(define_cpu_unit "z196_cr2" "z196_ipu") +(define_cpu_unit "z196_cr3" "z196_ipu") + +(final_presence_set "z196_g2" "z196_g1") +(final_presence_set "z196_g3" "z196_g2") +(final_presence_set "z196_cr2" "z196_cr1") +(final_presence_set "z196_cr3" "z196_cr2") +(exclusion_set "z196_g1" "z196_cr1") + +;; Instructions can be groupable, end a group, or be alone in a group. +(define_reservation "z196_simple" "( z196_g1 | z196_g2 | z196_g3 )") +(define_reservation "z196_ends" "( z196_g3 | ( z196_g2 + z196_g3 ) | ( z196_g1 + z196_g2 + z196_g3 ) )") + +;; Try to keep cracked and alone ops together in a clump. +(define_reservation "z196_crack" "( z196_cr1 | z196_cr2 | z196_cr3 )") +(define_reservation "z196_alone" "( z196_cr1 | z196_cr2 | z196_cr3 )") + +;; Most simple instruction a fast enough to be handled by OOO even with +;; latency == 0. This reduces life ranges and spilling. We want to increase +;; life range for longer running ops, though, thats why we do not use +;; -fno-schedule-insns. +(define_insn_reservation "z196_simple_LSU" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "load,store,lr") + (eq_attr "z196prop" "none"))) + "z196_simple") + +(define_insn_reservation "z196_simple_FXU" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "integer,la,larl,other") + (and (eq_attr "z196prop" "none") + (eq_attr "op_type" "RR")))) + "z196_simple") + +(define_insn_reservation "z196_simple_DUAL" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "integer,la,larl,other") + (and (eq_attr "z196prop" "none") + (eq_attr "op_type" "!RR")))) + "z196_simple") + +(define_insn_reservation "z196_cracked" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "integer,la,larl,load,lr,store,other") + (eq_attr "z196prop" "z196_cracked"))) + "z196_crack") + +(define_insn_reservation "z196_alone" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "integer,la,larl,load,lr,store,other") + (eq_attr "z196prop" "z196_alone"))) + "z196_alone") + +(define_insn_reservation "z196_ends" 0 + (and (eq_attr "cpu" "z196") + (and (eq_attr "type" "integer,la,larl,load,lr,store,other") + (eq_attr "z196prop" "z196_ends"))) + "z196_ends") + +(define_insn_reservation "z196_branch" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "branch")) + "z196_ends") + +(define_insn_reservation "z196_call" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "jsr")) + "z196_ends") + +(define_insn_reservation "z196_mul_hi" 10 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "imulhi")) + "z196_simple") + +(define_insn_reservation "z196_mul_si" 12 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "imulsi")) + "z196_simple") + +(define_insn_reservation "z196_mul_di" 14 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "imuldi")) + "z196_simple") + +(define_insn_reservation "z196_div" 73 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "idiv")) + "z196_alone") + +(define_insn_reservation "z196_sem" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "sem")) + "z196_crack") + +(define_insn_reservation "z196_cs" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "cs")) + "z196_crack") + +(define_insn_reservation "z196_vs" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "vs")) + "z196_alone") + +(define_insn_reservation "z196_lm_stm" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "stm,lm")) + "z196_crack") + + +;; +;; Binary Floating Point +;; + +(define_insn_reservation "z196_fsimptf" 18 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimptf,fhex")) + "z196_alone") + +(define_insn_reservation "z196_fmultf" 47 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fmultf")) + "z196_alone") + +(define_insn_reservation "z196_fsimpdf" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimpdf,fmuldf,fhex")) + "z196_simple") + +(define_insn_reservation "z196_fmadddf" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fmadddf")) + "z196_alone") + +(define_insn_reservation "z196_fsimpsf" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimpsf,fmulsf,fhex")) + "z196_simple") + +(define_insn_reservation "z196_fmaddsf" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fmaddsf")) + "z196_alone") + +(define_insn_reservation "z196_fdivtf" 108 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fdivtf,fsqrttf")) + "z196_alone") + +(define_insn_reservation "z196_fdivdf" 36 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fdivdf,fsqrtdf")) + "z196_simple") + +(define_insn_reservation "z196_fdivsf" 29 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fdivsf,fsqrtsf")) + "z196_simple") + + +;; Loads and stores are cheap as well. +(define_insn_reservation "z196_floaddf" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "floaddf")) + "z196_simple") + +(define_insn_reservation "z196_floadsf" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "floadsf")) + "z196_simple") + +(define_insn_reservation "z196_fstoredf" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fstoredf")) + "z196_simple") + +(define_insn_reservation "z196_fstoresf" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fstoresf")) + "z196_simple") + + +(define_insn_reservation "z196_ftrunctf" 9 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftrunctf")) + "z196_simple") + +(define_insn_reservation "z196_ftruncdf" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftruncdf")) + "z196_simple") + + +(define_insn_reservation "z196_ftoi" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftoi")) + "z196_crack") + +(define_insn_reservation "z196_itof" 7 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "itoftf,itofdf,itofsf")) + "z196_crack") + +;; +;; Decimal Floating Point +;; + +;; DDTR +(define_insn_reservation "z196_fdivdd" 33 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fdivdd")) + "z196_simple") + +;; DXTR +(define_insn_reservation "z196_fdivtd" 35 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fdivtd")) + "z196_alone") + +;; LEDTR +(define_insn_reservation "z196_ftruncsd" 34 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftruncsd")) + "z196_simple") + +;; LDXTR +(define_insn_reservation "z196_ftruncdd" 36 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftruncdd")) + "z196_simple") + +;; These are normal fp loads/stores - which are cheap. +(define_insn_reservation "z196_floadsddd" 0 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "floadsd,floaddd,fstoredd,fstoresd")) + "z196_simple") + +;; MDTR +(define_insn_reservation "z196_fmuldd" 23 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fmuldd")) + "z196_simple") + +;; MXTR +(define_insn_reservation "z196_fmultd" 25 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fmultd")) + "z196_alone") + +;; multiple different isns like add, sub etc. +;; Just use the same defaults as z10. +(define_insn_reservation "z196_fsimpsd" 17 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimpsd")) + "z196_simple") +(define_insn_reservation "z196_fsimpdd" 17 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimpdd")) + "z196_simple") +(define_insn_reservation "z196_fsimptd" 18 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "fsimptd")) + "z196_alone") + +;; CDGTR +(define_insn_reservation "z196_itofdd" 45 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "itofdd")) + "z196_crack") + +;; CXGTR +(define_insn_reservation "z196_itoftd" 33 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "itoftd")) + "z196_crack") + +;; CGXTR, CGDTR +(define_insn_reservation "z196_ftoidfp" 33 + (and (eq_attr "cpu" "z196") + (eq_attr "type" "ftoidfp")) + "z196_crack") + + + diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 11e9fe2e724..7fec1b9bcc2 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -223,6 +223,38 @@ struct processor_costs z10_cost = COSTS_N_INSNS (71), /* DSGR */ }; +static const +struct processor_costs z196_cost = +{ + COSTS_N_INSNS (7), /* M */ + COSTS_N_INSNS (5), /* MGHI */ + COSTS_N_INSNS (5), /* MH */ + COSTS_N_INSNS (5), /* MHI */ + COSTS_N_INSNS (7), /* ML */ + COSTS_N_INSNS (7), /* MR */ + COSTS_N_INSNS (6), /* MS */ + COSTS_N_INSNS (8), /* MSG */ + COSTS_N_INSNS (6), /* MSGF */ + COSTS_N_INSNS (6), /* MSGFR */ + COSTS_N_INSNS (8), /* MSGR */ + COSTS_N_INSNS (6), /* MSR */ + COSTS_N_INSNS (1) , /* multiplication in DFmode */ + COSTS_N_INSNS (40), /* MXBR B+40 */ + COSTS_N_INSNS (100), /* SQXBR B+100 */ + COSTS_N_INSNS (42), /* SQDBR B+42 */ + COSTS_N_INSNS (28), /* SQEBR B+28 */ + COSTS_N_INSNS (1), /* MADBR B */ + COSTS_N_INSNS (1), /* MAEBR B */ + COSTS_N_INSNS (101), /* DXBR B+101 */ + COSTS_N_INSNS (29), /* DDBR */ + COSTS_N_INSNS (22), /* DEBR */ + COSTS_N_INSNS (160), /* DLGR cracked */ + COSTS_N_INSNS (160), /* DLR cracked */ + COSTS_N_INSNS (160), /* DR expanded */ + COSTS_N_INSNS (160), /* DSGFR cracked */ + COSTS_N_INSNS (160), /* DSGR cracked */ +}; + extern int reload_completed; /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */ @@ -350,8 +382,8 @@ struct GTY(()) machine_function (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1)) /* That's the read ahead of the dynamic branch prediction unit in - bytes on a z10 CPU. */ -#define Z10_PREDICT_DISTANCE 384 + bytes on a z10 (or higher) CPU. */ +#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) static enum machine_mode s390_libgcc_cmp_return_mode (void) @@ -1506,7 +1538,9 @@ s390_handle_arch_option (const char *arg, {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP }, {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH - | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10}, + | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10}, + {"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH + | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 }, }; size_t i; @@ -1624,6 +1658,8 @@ s390_option_override (void) break; case PROCESSOR_2097_Z10: s390_cost = &z10_cost; + case PROCESSOR_2817_Z196: + s390_cost = &z196_cost; break; default: s390_cost = &z900_cost; @@ -1648,7 +1684,8 @@ s390_option_override (void) target_flags |= MASK_LONG_DOUBLE_128; #endif - if (s390_tune == PROCESSOR_2097_Z10) + if (s390_tune == PROCESSOR_2097_Z10 + || s390_tune == PROCESSOR_2817_Z196) { if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS)) set_param_value ("max-unrolled-insns", 100); @@ -2782,7 +2819,9 @@ s390_cannot_force_const_mem (rtx x) operand during and after reload. The difference to legitimate_constant_p is that this function will not accept a constant that would need to be forced to the literal pool - before it can be used as operand. */ + before it can be used as operand. + This function accepts all constants which can be loaded directly + into a GPR. */ bool legitimate_reload_constant_p (rtx op) @@ -2836,6 +2875,24 @@ legitimate_reload_constant_p (rtx op) return false; } +/* Returns true if the constant value OP is a legitimate fp operand + during and after reload. + This function accepts all constants which can be loaded directly + into an FPR. */ + +static bool +legitimate_reload_fp_constant_p (rtx op) +{ + /* Accept floating-point zero operands if the load zero instruction + can be used. */ + if (TARGET_Z196 + && GET_CODE (op) == CONST_DOUBLE + && s390_float_const_zero_p (op)) + return true; + + return false; +} + /* Given an rtx OP being reloaded into a reg required to be in class RCLASS, return the class of reg to actually use. */ @@ -2854,8 +2911,10 @@ s390_preferred_reload_class (rtx op, enum reg_class rclass) else if (reg_class_subset_p (ADDR_REGS, rclass) && legitimate_reload_constant_p (op)) return ADDR_REGS; - else - return NO_REGS; + else if (reg_class_subset_p (FP_REGS, rclass) + && legitimate_reload_fp_constant_p (op)) + return FP_REGS; + return NO_REGS; /* If a symbolic constant or a PLUS is reloaded, it is most likely being used as an address, so @@ -3218,6 +3277,11 @@ preferred_la_operand_p (rtx op1, rtx op2) if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx))) return false; + /* Avoid LA instructions with index register on z196; it is + preferable to use regular add instructions when possible. */ + if (addr.indx && s390_tune == PROCESSOR_2817_Z196) + return false; + if (!TARGET_64BIT && !addr.pointer) return false; @@ -5398,8 +5462,6 @@ s390_agen_dep_p (rtx dep_insn, rtx insn) A STD instruction should be scheduled earlier, in order to use the bypass. */ - - static int s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) { @@ -5408,7 +5470,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) if (s390_tune != PROCESSOR_2084_Z990 && s390_tune != PROCESSOR_2094_Z9_109 - && s390_tune != PROCESSOR_2097_Z10) + && s390_tune != PROCESSOR_2097_Z10 + && s390_tune != PROCESSOR_2817_Z196) return priority; switch (s390_safe_attr_type (insn)) @@ -5437,6 +5500,7 @@ s390_issue_rate (void) { case PROCESSOR_2084_Z990: case PROCESSOR_2094_Z9_109: + case PROCESSOR_2817_Z196: return 3; case PROCESSOR_2097_Z10: return 2; @@ -9859,13 +9923,13 @@ s390_optimize_prologue (void) } } -/* On z10 the dynamic branch prediction must see the backward jump in - a window of 384 bytes. If not it falls back to the static - prediction. This function rearranges the loop backward branch in a - way which makes the static prediction always correct. The function - returns true if it added an instruction. */ +/* On z10 and later the dynamic branch prediction must see the + backward jump within a certain windows. If not it falls back to + the static prediction. This function rearranges the loop backward + branch in a way which makes the static prediction always correct. + The function returns true if it added an instruction. */ static bool -s390_z10_fix_long_loop_prediction (rtx insn) +s390_fix_long_loop_prediction (rtx insn) { rtx set = single_set (insn); rtx code_label, label_ref, new_label; @@ -9891,11 +9955,11 @@ s390_z10_fix_long_loop_prediction (rtx insn) if (INSN_ADDRESSES (INSN_UID (code_label)) == -1 || INSN_ADDRESSES (INSN_UID (insn)) == -1 || (INSN_ADDRESSES (INSN_UID (insn)) - - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE)) + - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE)) return false; for (distance = 0, cur_insn = PREV_INSN (insn); - distance < Z10_PREDICT_DISTANCE - 6; + distance < PREDICT_DISTANCE - 6; distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn)) if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn)) return false; @@ -10195,8 +10259,9 @@ s390_reorg (void) /* Try to optimize prologue and epilogue further. */ s390_optimize_prologue (); - /* Walk over the insns and do some z10 specific changes. */ - if (s390_tune == PROCESSOR_2097_Z10) + /* Walk over the insns and do some >=z10 specific changes. */ + if (s390_tune == PROCESSOR_2097_Z10 + || s390_tune == PROCESSOR_2817_Z196) { rtx insn; bool insn_added_p = false; @@ -10211,10 +10276,11 @@ s390_reorg (void) continue; if (JUMP_P (insn)) - insn_added_p |= s390_z10_fix_long_loop_prediction (insn); + insn_added_p |= s390_fix_long_loop_prediction (insn); - if (GET_CODE (PATTERN (insn)) == PARALLEL - || GET_CODE (PATTERN (insn)) == SET) + if ((GET_CODE (PATTERN (insn)) == PARALLEL + || GET_CODE (PATTERN (insn)) == SET) + && s390_tune == PROCESSOR_2097_Z10) insn_added_p |= s390_z10_optimize_cmp (insn); } @@ -10360,8 +10426,9 @@ check_dpu (rtx *x, unsigned *mem_count) } /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates - a new number struct loop *loop should be unrolled if tuned for the z10 - cpu. The loop is analyzed for memory accesses by calling check_dpu for + a new number struct loop *loop should be unrolled if tuned for cpus with + a built-in stride prefetcher. + The loop is analyzed for memory accesses by calling check_dpu for each rtx of the loop. Depending on the loop_depth and the amount of memory accesses a new number <=nunroll is returned to improve the behaviour of the hardware prefetch unit. */ @@ -10373,8 +10440,7 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) unsigned i; unsigned mem_count = 0; - /* Only z10 needs special handling. */ - if (s390_tune != PROCESSOR_2097_Z10) + if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196) return nunroll; /* Count the number of memory references within the loop body. */ diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index fcc63b0d332..ca04a7c5587 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -36,6 +36,7 @@ enum processor_type PROCESSOR_2084_Z990, PROCESSOR_2094_Z9_109, PROCESSOR_2097_Z10, + PROCESSOR_2817_Z196, PROCESSOR_max }; @@ -48,7 +49,8 @@ enum processor_flags PF_LONG_DISPLACEMENT = 4, PF_EXTIMM = 8, PF_DFP = 16, - PF_Z10 = 32 + PF_Z10 = 32, + PF_Z196 = 64 }; extern enum processor_type s390_tune; @@ -77,6 +79,8 @@ extern int s390_arch_flags; (s390_arch_flags & PF_DFP) #define TARGET_CPU_Z10 \ (s390_arch_flags & PF_Z10) +#define TARGET_CPU_Z196 \ + (s390_arch_flags & PF_Z196) /* These flags indicate that the generated code should run on a cpu providing the respective hardware facility when run in @@ -90,6 +94,11 @@ extern int s390_arch_flags; (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) #define TARGET_Z10 \ (TARGET_ZARCH && TARGET_CPU_Z10) +#define TARGET_Z196 \ + (TARGET_ZARCH && TARGET_CPU_Z196) + + +#define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) /* Run-time target specification. */ @@ -869,8 +878,6 @@ do { \ /* Position independent code. */ -extern int flag_pic; - #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 80cb43ad2e3..6d03923a542 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -107,6 +107,10 @@ ; Test Data Class (TDC) (UNSPEC_TDC_INSN 800) + + ; Population Count + (UNSPEC_POPCNT 900) + (UNSPEC_COPYSIGN 901) ]) ;; @@ -133,6 +137,7 @@ ; Atomic Support (UNSPECV_CAS 700) + (UNSPECV_ATOMIC_OP 701) ]) ;; @@ -203,6 +208,7 @@ floadtf,floaddf,floadsf,fstoredf,fstoresf, fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, ftoi,fsqrttf,fsqrtdf,fsqrtsf, + fmadddf,fmaddsf, ftrunctf,ftruncdf, ftruncsd, ftruncdd, itoftf, itofdf, itofsf, itofdd, itoftd, fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, @@ -244,6 +250,14 @@ z10_c" (const_string "none")) +;; Properties concerning Z196 decoding +;; z196_alone: must group alone +;; z196_end: ends a group +;; z196_cracked: instruction is cracked or expanded +(define_attr "z196prop" "none, + z196_alone, z196_ends, + z196_cracked" + (const_string "none")) ;; Length in bytes. @@ -258,10 +272,10 @@ ;; distinguish between g5 and g6, but there are differences between the two ;; CPUs could in theory be modeled. -(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" +(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10,z196" (const (symbol_ref "s390_tune_attr"))) -(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" +(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196" (const_string "standard")) (define_attr "enabled" "" @@ -290,6 +304,10 @@ (and (eq_attr "cpu_facility" "z10") (ne (symbol_ref "TARGET_Z10") (const_int 0))) + (const_int 1) + + (and (eq_attr "cpu_facility" "z196") + (ne (symbol_ref "TARGET_Z196") (const_int 0))) (const_int 1)] (const_int 0))) @@ -303,6 +321,9 @@ ;; Pipeline description for z10 (include "2097.md") +;; Pipeline description for z196 +(include "2817.md") + ;; Predicates (include "predicates.md") @@ -361,8 +382,10 @@ ;; This iterator and attribute allow to combine most atomic operations. (define_code_iterator ATOMIC [and ior xor plus minus mult]) +(define_code_iterator ATOMIC_Z196 [and ior xor plus]) (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") (plus "add") (minus "sub") (mult "nand")]) +(define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. @@ -464,6 +487,11 @@ ;; and "cfdbr" in SImode. (define_mode_attr gf [(DI "g") (SI "f")]) +;; In GPR templates, a string like sll<gk> will expand to sllg for DI +;; and sllk for SI. This way it is possible to merge the new z196 SI +;; 3 operands shift instructions into the existing patterns. +(define_mode_attr gk [(DI "g") (SI "k")]) + ;; ICM mask required to load MODE value into the lowest subreg ;; of a SImode register. (define_mode_attr icm_lo [(HI "3") (QI "1")]) @@ -775,7 +803,8 @@ chrl\t%0,%1" [(set_attr "op_type" "RX,RXY,RIL") (set_attr "cpu_facility" "*,*,z10") - (set_attr "type" "*,*,larl")]) + (set_attr "type" "*,*,larl") + (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) (define_insn "*cmphi_ccs_z10" [(set (reg CC_REGNUM) @@ -783,7 +812,8 @@ (match_operand:HI 1 "immediate_operand" "K")))] "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" "chhsi\t%0,%1" - [(set_attr "op_type" "SIL")]) + [(set_attr "op_type" "SIL") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*cmpdi_ccs_signhi_rl" [(set (reg CC_REGNUM) @@ -1002,7 +1032,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10" + "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" { if (get_attr_length (insn) == 6) return which_alternative ? @@ -1030,7 +1060,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10" + "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" { if (get_attr_length (insn) == 6) return which_alternative ? @@ -1060,7 +1090,7 @@ (pc) (label_ref (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10" + "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" { if (get_attr_length (insn) == 6) return which_alternative ? @@ -1088,7 +1118,7 @@ (pc) (label_ref (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10" + "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" { if (get_attr_length (insn) == 6) return which_alternative ? @@ -1928,10 +1958,11 @@ "") (define_insn "*mov<mode>_64" - [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o") - (match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))] + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") + (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] "TARGET_ZARCH" "@ + lzxr\t%0 lxr\t%0,%1 # # @@ -1939,19 +1970,22 @@ stmg\t%1,%N1,%S0 # #" - [(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*") - (set_attr "type" "fsimptf,*,*,lm,stm,*,*")]) + [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") + (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") + (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) (define_insn "*mov<mode>_31" - [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o") - (match_operand:TD_TF 1 "general_operand" " f,o,f"))] + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") + (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] "!TARGET_ZARCH" "@ + lzxr\t%0 lxr\t%0,%1 # #" - [(set_attr "op_type" "RRE,*,*") - (set_attr "type" "fsimptf,*,*")]) + [(set_attr "op_type" "RRE,RRE,*,*") + (set_attr "type" "fsimptf,fsimptf,*,*") + (set_attr "cpu_facility" "z196,*,*,*")]) ; TFmode in GPRs splitters @@ -2042,11 +2076,12 @@ (define_insn "*mov<mode>_64dfp" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,d,f,f,R,T,d,d, d,RT") + "=f,f,f,d,f,f,R,T,d,d, d,RT") (match_operand:DD_DF 1 "general_operand" - " f,d,f,R,T,f,f,G,d,RT, d"))] + " G,f,d,f,R,T,f,f,G,d,RT, d"))] "TARGET_DFP" "@ + lzdr\t%0 ldr\t%0,%1 ldgr\t%0,%1 lgdr\t%0,%1 @@ -2058,17 +2093,18 @@ lgr\t%0,%1 lg\t%0,%1 stg\t%1,%0" - [(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") - (set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf, + [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") + (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, fstoredf,fstoredf,*,lr,load,store") - (set_attr "z10prop" "*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") -]) + (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") + (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) (define_insn "*mov<mode>_64" - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d, d,RT") - (match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,G,d,RT, d"))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") + (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] "TARGET_ZARCH" "@ + lzdr\t%0 ldr\t%0,%1 ld\t%0,%1 ldy\t%0,%1 @@ -2078,18 +2114,20 @@ lgr\t%0,%1 lg\t%0,%1 stg\t%1,%0" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") - (set_attr "type" "fload<mode>,fload<mode>,fload<mode>, - fstore<mode>,fstore<mode>,*,lr,load,store") - (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")]) + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") + (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,*,lr,load,store") + (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") + (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) (define_insn "*mov<mode>_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,R,T,d,d,Q,S, d,o") + "=f,f,f,f,R,T,d,d,Q,S, d,o") (match_operand:DD_DF 1 "general_operand" - " f,R,T,f,f,Q,S,d,d,dPRT,d"))] + " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] "!TARGET_ZARCH" "@ + lzdr\t%0 ldr\t%0,%1 ld\t%0,%1 ldy\t%0,%1 @@ -2101,9 +2139,10 @@ stmy\t%1,%N1,%S0 # #" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") - (set_attr "type" "fload<mode>,fload<mode>,fload<mode>, - fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") + (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") + (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") @@ -2152,11 +2191,12 @@ (define_insn "mov<mode>" [(set (match_operand:SD_SF 0 "nonimmediate_operand" - "=f,f,f,R,T,d,d,d,d,R,T") + "=f,f,f,f,R,T,d,d,d,d,R,T") (match_operand:SD_SF 1 "general_operand" - " f,R,T,f,f,G,d,R,T,d,d"))] + " G,f,R,T,f,f,G,d,R,T,d,d"))] "" "@ + lzer\t%0 ler\t%0,%1 le\t%0,%1 ley\t%0,%1 @@ -2168,10 +2208,11 @@ ly\t%0,%1 st\t%1,%0 sty\t%1,%0" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") - (set_attr "type" "fload<mode>,fload<mode>,fload<mode>, - fstore<mode>,fstore<mode>,*,lr,load,load,store,store") - (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")]) + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") + (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,*,lr,load,load,store,store") + (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") + (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) ; ; movcc instruction pattern @@ -2191,7 +2232,8 @@ ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") (set_attr "type" "lr,*,*,store,store,load,load") - (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) + (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3") + (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) ; ; Block move (MVC) patterns. @@ -3846,100 +3888,141 @@ [(parallel [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) - (clobber (match_scratch:TD 2 "=f"))])] + (unspec:DI [(const_int 5)] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_DFP" { - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (TDmode); - REAL_VALUE_TYPE cmp, sub; - - decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ - decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ - - /* 2^63 can't be represented as 64bit DFP number with full precision. The - solution is doing the check and the subtraction in TD mode and using a - TD -> DI convert afterwards. */ - emit_insn (gen_extendddtd2 (temp, operands[1])); - temp = force_reg (TDmode, temp); - emit_cmp_and_jump_insns (temp, - CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), - LT, NULL_RTX, VOIDmode, 0, label1); - emit_insn (gen_subtd3 (temp, temp, - CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); - emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); - emit_label (label2); - DONE; + if (!TARGET_Z196) + { + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx temp = gen_reg_rtx (TDmode); + REAL_VALUE_TYPE cmp, sub; + + decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ + decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ + + /* 2^63 can't be represented as 64bit DFP number with full precision. The + solution is doing the check and the subtraction in TD mode and using a + TD -> DI convert afterwards. */ + emit_insn (gen_extendddtd2 (temp, operands[1])); + temp = force_reg (TDmode, temp); + emit_cmp_and_jump_insns (temp, + CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), + LT, NULL_RTX, VOIDmode, 0, label1); + emit_insn (gen_subtd3 (temp, temp, + CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); + emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); + emit_jump (label2); + + emit_label (label1); + emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); + emit_label (label2); + DONE; + } }) (define_expand "fixuns_trunctddi2" - [(set (match_operand:DI 0 "register_operand" "") - (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) + (unspec:DI [(const_int 5)] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_HARD_DFP" { - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (TDmode); - REAL_VALUE_TYPE cmp, sub; - - operands[1] = force_reg (TDmode, operands[1]); - decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ - decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ - - emit_cmp_and_jump_insns (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), - LT, NULL_RTX, VOIDmode, 0, label1); - emit_insn (gen_subtd3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); - emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); - emit_label (label2); - DONE; + if (!TARGET_Z196) + { + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx temp = gen_reg_rtx (TDmode); + REAL_VALUE_TYPE cmp, sub; + + operands[1] = force_reg (TDmode, operands[1]); + decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ + decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ + + emit_cmp_and_jump_insns (operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), + LT, NULL_RTX, VOIDmode, 0, label1); + emit_insn (gen_subtd3 (temp, operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); + emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); + emit_jump (label2); + + emit_label (label1); + emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); + emit_label (label2); + DONE; + } }) ; -; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 +; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 ; instruction pattern(s). ; (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "register_operand" "") - (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))] + [(parallel + [(set (match_operand:GPR 0 "register_operand" "") + (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) + (unspec:GPR [(const_int 5)] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" { - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (<BFP:MODE>mode); - REAL_VALUE_TYPE cmp, sub; - - operands[1] = force_reg (<BFP:MODE>mode, operands[1]); - real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); - real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); - - emit_cmp_and_jump_insns (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), - LT, NULL_RTX, VOIDmode, 0, label1); - emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); - emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, - GEN_INT (7))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], - operands[1], GEN_INT (5))); - emit_label (label2); - DONE; + if (!TARGET_Z196) + { + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx temp = gen_reg_rtx (<BFP:MODE>mode); + REAL_VALUE_TYPE cmp, sub; + + operands[1] = force_reg (<BFP:MODE>mode, operands[1]); + real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); + real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); + + emit_cmp_and_jump_insns (operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), + LT, NULL_RTX, VOIDmode, 0, label1); + emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); + emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, + GEN_INT (7))); + emit_jump (label2); + + emit_label (label1); + emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], + operands[1], GEN_INT (5))); + emit_label (label2); + DONE; + } }) +; fixuns_trunc(td|dd)si2 expander +(define_expand "fixuns_trunc<mode>si2" + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) + (unspec:SI [(const_int 5)] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_Z196 && TARGET_HARD_FLOAT" + "") + +; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. + +; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr +; clfdtr, clfxtr, clgdtr, clgxtr +(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) + (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z196" + "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" + [(set_attr "op_type" "RRF") + (set_attr "type" "ftoi")]) + (define_expand "fix_trunc<DSF:mode><GPR:mode>2" [(set (match_operand:GPR 0 "register_operand" "") (fix:GPR (match_operand:DSF 1 "register_operand" "")))] @@ -4024,6 +4107,28 @@ [(set_attr "op_type" "RRE") (set_attr "type" "itof<mode>" )]) +; cxftr, cdftr +(define_insn "floatsi<mode>2" + [(set (match_operand:DFP 0 "register_operand" "=f") + (float:DFP (match_operand:SI 1 "register_operand" "d")))] + "TARGET_Z196 && TARGET_HARD_FLOAT" + "c<xde>ftr\t%0,0,%1,0" + [(set_attr "op_type" "RRE") + (set_attr "type" "itof<mode>" )]) + +; +; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). +; + +; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr +; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr +(define_insn "floatuns<GPR:mode><FP:mode>2" + [(set (match_operand:FP 0 "register_operand" "=f") + (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] + "TARGET_Z196 && TARGET_HARD_FLOAT" + "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" + [(set_attr "op_type" "RRE") + (set_attr "type" "itof<FP:mode>" )]) ; ; truncdfsf2 instruction pattern(s). @@ -4294,7 +4399,8 @@ "@ agfr\t%0,%2 agf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z196prop" "z196_cracked,z196_cracked")]) (define_insn "*adddi3_zero_cc" [(set (reg CC_REGNUM) @@ -4414,178 +4520,178 @@ "@ ah\t%0,%2 ahy\t%0,%2" - [(set_attr "op_type" "RX,RXY")]) + [(set_attr "op_type" "RX,RXY") + (set_attr "z196prop" "z196_cracked,z196_cracked")]) ; ; add(di|si)3 instruction pattern(s). ; -; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi +; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") - (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") + (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") + (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ a<g>r\t%0,%2 + a<g>rk\t%0,%1,%2 a<g>hi\t%0,%h2 + a<g>hik\t%0,%1,%h2 al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 a<g>\t%0,%2 a<y>\t%0,%2 a<g>si\t%0,%c2" - [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") - (set_attr "z10prop" "z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, + z10_super_E1,z10_super_E1,z10_super_E1")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi +; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik (define_insn "*add<mode>3_carry1_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) (match_dup 1))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 + al<g>hsik\t%0,%1,%h2 al<g>\t%0,%2 al<y>\t%0,%2 al<g>si\t%0,%c2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") - (set_attr "z10prop" "z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1,z10_super_E1")]) -; alr, al, aly, algr, alg +; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_carry1_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi +; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add<mode>3_carry2_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") + (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) (match_dup 2))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 + al<g>hsik\t%0,%1,%h2 al<g>\t%0,%2 al<y>\t%0,%2 al<g>si\t%0,%c2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") - (set_attr "z10prop" "z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1,z10_super_E1")]) -; alr, al, aly, algr, alg +; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_carry2_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (match_dup 2))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) -; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi +; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add<mode>3_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") + (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>fi\t%0,%2 sl<g>fi\t%0,%n2 + al<g>hsik\t%0,%1,%h2 al<g>\t%0,%2 al<y>\t%0,%2 al<g>si\t%0,%c2" - [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") - (set_attr "z10prop" "z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1, - z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, + *,z10_super_E1,z10_super_E1,z10_super_E1")]) -; alr, al, aly, algr, alg +; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCLmode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) -; alr, al, aly, algr, alg +; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_cconly2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") - (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") + (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode(insn, CCLmode)" "@ al<g>r\t%0,%2 + al<g>rk\t%0,%1,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") - (match_operand:GPR 2 "const_int_operand" "K,Os,C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") + (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") @@ -4594,11 +4700,12 @@ && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" "@ a<g>hi\t%0,%h2 + a<g>hik\t%0,%1,%h2 a<g>fi\t%0,%2 a<g>si\t%0,%c2" - [(set_attr "op_type" "RI,RIL,SIY") - (set_attr "cpu_facility" "*,extimm,z10") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RI,RIE,RIL,SIY") + (set_attr "cpu_facility" "*,z196,extimm,z10") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). @@ -4702,7 +4809,8 @@ sgfr\t%0,%2 sgf\t%0,%2" [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_c,*")]) + (set_attr "z10prop" "z10_c,*") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) @@ -4821,117 +4929,132 @@ "@ sh\t%0,%2 shy\t%0,%2" - [(set_attr "op_type" "RX,RXY")]) + [(set_attr "op_type" "RX,RXY") + (set_attr "z196prop" "z196_cracked,z196_cracked")]) ; ; sub(di|si)3 instruction pattern(s). ; -; sr, s, sy, sgr, sg +; sr, s, sy, sgr, sg, srk, sgrk (define_insn "*sub<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d") - (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T") ) ) + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") + (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ s<g>r\t%0,%2 + s<g>rk\t%0,%1,%2 s<g>\t%0,%2 s<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_borrow_cc" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d") + (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") (minus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL2mode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_borrow_cconly" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL2mode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cc" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d") + (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") (minus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cc2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T"))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d") + (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T"))) + (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") (minus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL3mode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cconly" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T")) + (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCLmode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) -; slr, sl, sly, slgr, slg +; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cconly2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "register_operand" "0,0,0") - (match_operand:GPR 2 "general_operand" "d,R,T"))) - (clobber (match_scratch:GPR 0 "=d,d,d"))] + (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") + (match_operand:GPR 2 "general_operand" "d,d,R,T"))) + (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL3mode)" "@ sl<g>r\t%0,%2 + sl<g>rk\t%0,%1,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY") - (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") + (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; @@ -5008,7 +5131,8 @@ "@ alc<g>r\t%0,%2 alc<g>\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z196prop" "z196_alone,z196_alone")]) ; alcr, alc, alcgr, alcg (define_insn "*add<mode>3_alc_carry1_cconly" @@ -5023,7 +5147,8 @@ "@ alc<g>r\t%0,%2 alc<g>\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z196prop" "z196_alone,z196_alone")]) ; op1 + op2 + c < op2 @@ -5201,6 +5326,52 @@ ;; +;; - Conditional move instructions (introduced with z196) +;; + +(define_expand "mov<mode>cc" + [(set (match_operand:GPR 0 "nonimmediate_operand" "") + (if_then_else:GPR (match_operand 1 "comparison_operator" "") + (match_operand:GPR 2 "nonimmediate_operand" "") + (match_operand:GPR 3 "nonimmediate_operand" "")))] + "TARGET_Z196" + "operands[1] = s390_emit_compare (GET_CODE (operands[1]), + XEXP (operands[1], 0), XEXP (operands[1], 1));") + +; locr, loc, stoc, locgr, lgoc, stgoc +(define_insn_and_split "*mov<mode>cc" + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") + (if_then_else:GPR + (match_operator 1 "s390_comparison" + [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") + (const_int 0)]) + (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") + (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] + "TARGET_Z196" + "@ + loc<g>r%C1\t%0,%3 + loc<g>r%D1\t%0,%4 + l<g>oc%C1\t%0,%3 + l<g>oc%D1\t%0,%4 + st<g>oc%C1\t%3,%0 + st<g>oc%D1\t%4,%0 + #" + "&& reload_completed + && MEM_P (operands[3]) && MEM_P (operands[4])" + [(set (match_dup 0) + (if_then_else:GPR + (match_op_dup 1 [(match_dup 2) (const_int 0)]) + (match_dup 3) + (match_dup 0))) + (set (match_dup 0) + (if_then_else:GPR + (match_op_dup 1 [(match_dup 2) (const_int 0)]) + (match_dup 0) + (match_dup 4)))] + "" + [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) + +;; ;;- Multiply instructions. ;; @@ -5327,7 +5498,7 @@ ma<xde>br\t%0,%1,%2 ma<xde>b\t%0,%1,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmul<mode>")]) + (set_attr "type" "fmadd<mode>")]) ; msxbr, msdbr, msebr, msxb, msdb, mseb (define_insn "*fmsub<mode>" @@ -5340,7 +5511,7 @@ ms<xde>br\t%0,%1,%2 ms<xde>b\t%0,%1,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmul<mode>")]) + (set_attr "type" "fmadd<mode>")]) ;; ;;- Divide and modulo instructions. @@ -5795,39 +5966,44 @@ (define_insn "*anddi3_cc" [(set (reg CC_REGNUM) - (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d") + (set (match_operand:DI 0 "register_operand" "=d,d, d") (and:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ngr\t%0,%2 + ngrk\t%0,%1,%2 ng\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "cpu_facility" "*,z196,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) - (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d,d"))] + (clobber (match_scratch:DI 0 "=d,d, d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH /* Do not steal TM patterns. */ && s390_single_part (operands[2], DImode, HImode, 0) < 0" "@ ngr\t%0,%2 + ngrk\t%0,%1,%2 ng\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "cpu_facility" "*,z196,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*anddi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") + [(set (match_operand:DI 0 "nonimmediate_operand" + "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q") (and:DI (match_operand:DI 1 "nonimmediate_operand" - "%d,o,0,0,0,0,0,0,0,0,0,0") + "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0") (match_operand:DI 2 "general_operand" - "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) + "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -5840,11 +6016,12 @@ nihf\t%0,%m2 nilf\t%0,%m2 ngr\t%0,%2 + ngrk\t%0,%1,%2 ng\t%0,%2 # #" - [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") + [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") + (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*") (set_attr "z10prop" "*, *, z10_super_E1, @@ -5854,6 +6031,7 @@ z10_super_E1, z10_super_E1, z10_super_E1, + *, z10_super_E1, *, *")]) @@ -5875,43 +6053,49 @@ (define_insn "*andsi3_cc" [(set (reg CC_REGNUM) - (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") (and:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ nilf\t%0,%o2 nr\t%0,%2 + nrk\t%0,%1,%2 n\t%0,%2 ny\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_cconly" [(set (reg CC_REGNUM) - (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (clobber (match_scratch:SI 0 "=d,d,d,d"))] + (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] "s390_match_ccmode(insn, CCTmode) /* Do not steal TM patterns. */ && s390_single_part (operands[2], SImode, HImode, 0) < 0" "@ nilf\t%0,%o2 nr\t%0,%2 + nrk\t%0,%1,%2 n\t%0,%2 ny\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_zarch" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") + [(set (match_operand:SI 0 "nonimmediate_operand" + "=d,d, d, d, d,d,d,d,d, AQ,Q") (and:SI (match_operand:SI 1 "nonimmediate_operand" - "%d,o,0,0,0,0,0,0,0,0") + "%d,o, 0, 0, 0,0,d,0,0, 0,0") (match_operand:SI 2 "general_operand" - "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) + " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -5921,26 +6105,29 @@ nill\t%0,%j2 nilf\t%0,%o2 nr\t%0,%2 + nrk\t%0,%1,%2 n\t%0,%2 ny\t%0,%2 # #" - [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") + [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") + (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*") (set_attr "z10prop" "*, *, z10_super_E1, z10_super_E1, z10_super_E1, z10_super_E1, + *, z10_super_E1, z10_super_E1, *, *")]) (define_insn "*andsi3_esa" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") + (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -5967,18 +6154,20 @@ ; (define_insn "*andhi3_zarch" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") + (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") + (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 + nrk\t%0,%1,%2 nill\t%0,%x2 # #" - [(set_attr "op_type" "RR,RI,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") + [(set_attr "op_type" "RR,RRF,RI,SI,SS") + (set_attr "cpu_facility" "*,z196,*,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") ]) (define_insn "*andhi3_esa" @@ -6010,19 +6199,21 @@ ; (define_insn "*andqi3_zarch" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") - (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") + (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") + (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 + nrk\t%0,%1,%2 nill\t%0,%b2 ni\t%S0,%b2 niy\t%S0,%b2 #" - [(set_attr "op_type" "RR,RI,SI,SIY,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) + [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") + (set_attr "cpu_facility" "*,z196,*,*,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*andqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") @@ -6049,7 +6240,8 @@ (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "nc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS")]) + [(set_attr "op_type" "SS") + (set_attr "z196prop" "z196_cracked")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -6114,36 +6306,42 @@ (define_insn "*iordi3_cc" [(set (reg CC_REGNUM) - (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d") + (set (match_operand:DI 0 "register_operand" "=d,d, d") (ior:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ogr\t%0,%2 + ogrk\t%0,%1,%2 og\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "cpu_facility" "*,z196,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) - (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d,d"))] + (clobber (match_scratch:DI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ ogr\t%0,%2 + ogrk\t%0,%1,%2 og\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "cpu_facility" "*,z196,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*iordi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") - (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") + [(set (match_operand:DI 0 "nonimmediate_operand" + "=d, d, d, d, d, d,d,d, d, AQ,Q") + (ior:DI (match_operand:DI 1 "nonimmediate_operand" + " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") (match_operand:DI 2 "general_operand" - "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) + "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -6154,11 +6352,12 @@ oihf\t%0,%k2 oilf\t%0,%k2 ogr\t%0,%2 + ogrk\t%0,%1,%2 og\t%0,%2 # #" - [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") + [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") + (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") (set_attr "z10prop" "z10_super_E1, z10_super_E1, z10_super_E1, @@ -6166,6 +6365,7 @@ z10_super_E1, z10_super_E1, z10_super_E1, + *, z10_super_E1, *, *")]) @@ -6186,39 +6386,43 @@ (define_insn "*iorsi3_cc" [(set (reg CC_REGNUM) - (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") (ior:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ oilf\t%0,%o2 or\t%0,%2 + ork\t%0,%1,%2 o\t%0,%2 oy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_cconly" [(set (reg CC_REGNUM) - (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (clobber (match_scratch:SI 0 "=d,d,d,d"))] + (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] "s390_match_ccmode(insn, CCTmode)" "@ oilf\t%0,%o2 or\t%0,%2 + ork\t%0,%1,%2 o\t%0,%2 oy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_zarch" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") - (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") - (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) + [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") + (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") + (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -6226,15 +6430,18 @@ oill\t%0,%i2 oilf\t%0,%o2 or\t%0,%2 + ork\t%0,%1,%2 o\t%0,%2 oy\t%0,%2 # #" - [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") + [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") + (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") (set_attr "z10prop" "z10_super_E1, z10_super_E1, z10_super_E1, z10_super_E1, + *, z10_super_E1, z10_super_E1, *, @@ -6269,18 +6476,20 @@ ; (define_insn "*iorhi3_zarch" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") - (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") + (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") + (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 + ork\t%0,%1,%2 oill\t%0,%x2 # #" - [(set_attr "op_type" "RR,RI,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) + [(set_attr "op_type" "RR,RRF,RI,SI,SS") + (set_attr "cpu_facility" "*,z196,*,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) (define_insn "*iorhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") @@ -6310,19 +6519,22 @@ ; (define_insn "*iorqi3_zarch" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") - (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") + (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") + (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 + ork\t%0,%1,%2 oill\t%0,%b2 oi\t%S0,%b2 oiy\t%S0,%b2 #" - [(set_attr "op_type" "RR,RI,SI,SIY,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) + [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") + (set_attr "cpu_facility" "*,z196,*,*,*,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, + z10_super,z10_super,*")]) (define_insn "*iorqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") @@ -6349,7 +6561,8 @@ (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "oc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS")]) + [(set_attr "op_type" "SS") + (set_attr "z196prop" "z196_cracked")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -6414,47 +6627,52 @@ (define_insn "*xordi3_cc" [(set (reg CC_REGNUM) - (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d") + (set (match_operand:DI 0 "register_operand" "=d,d, d") (xor:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ xgr\t%0,%2 + xgrk\t%0,%1,%2 xg\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) - (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,RT")) + (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") + (match_operand:DI 2 "general_operand" " d,d,RT")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d,d"))] + (clobber (match_scratch:DI 0 "=d,d, d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ xgr\t%0,%2 + xgrk\t%0,%1,%2 xg\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RRE,RRF,RXY") + (set_attr "cpu_facility" "*,z196,*") + (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*xordi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") - (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) + [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") + (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") + (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ xihf\t%0,%k2 xilf\t%0,%k2 xgr\t%0,%2 + xgrk\t%0,%1,%2 xg\t%0,%2 # #" - [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) + [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") + (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, + *,z10_super_E1,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") @@ -6472,50 +6690,59 @@ (define_insn "*xorsi3_cc" [(set (reg CC_REGNUM) - (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") (xor:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ xilf\t%0,%o2 xr\t%0,%2 + xrk\t%0,%1,%2 x\t%0,%2 xy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3_cconly" [(set (reg CC_REGNUM) - (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T")) + (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) (const_int 0))) - (clobber (match_scratch:SI 0 "=d,d,d,d"))] + (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] "s390_match_ccmode(insn, CCTmode)" "@ xilf\t%0,%o2 xr\t%0,%2 + xrk\t%0,%1,%2 x\t%0,%2 xy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") - (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") + (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") + (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xilf\t%0,%o2 xr\t%0,%2 + xrk\t%0,%1,%2 x\t%0,%2 xy\t%0,%2 # #" - [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) + [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") + (set_attr "cpu_facility" "*,*,z196,*,*,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, + z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:SI 0 "s_operand" "") @@ -6532,18 +6759,20 @@ ; (define_insn "*xorhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") - (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") + (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") + (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xilf\t%0,%x2 xr\t%0,%2 + xrk\t%0,%1,%2 # #" - [(set_attr "op_type" "RIL,RR,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) + [(set_attr "op_type" "RIL,RR,RRF,SI,SS") + (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) (define_split [(set (match_operand:HI 0 "s_operand" "") @@ -6560,19 +6789,21 @@ ; (define_insn "*xorqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") - (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") + (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") + (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xilf\t%0,%b2 xr\t%0,%2 + xrk\t%0,%1,%2 xi\t%S0,%b2 xiy\t%S0,%b2 #" - [(set_attr "op_type" "RIL,RR,SI,SIY,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) + [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") + (set_attr "cpu_facility" "*,*,z196,*,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) ; @@ -6644,7 +6875,8 @@ (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" "xc\t%O0(%1,%R0),%S0" - [(set_attr "op_type" "SS")]) + [(set_attr "op_type" "SS") + (set_attr "z196prop" "z196_cracked")]) (define_peephole2 [(parallel @@ -7167,7 +7399,7 @@ ; ; (ashl|lshr)(di|si)3 instruction pattern(s). -; +; Left shifts and logical right shifts (define_expand "<shift><mode>3" [(set (match_operand:DSI 0 "register_operand" "") @@ -7184,18 +7416,22 @@ "!TARGET_ZARCH" "s<lr>dl\t%0,%Y2" [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z196prop" "z196_cracked")]) -; sll, srl, sllg, srlg +; sll, srl, sllg, srlg, sllk, srlk (define_insn "*<shift><mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] "" - "s<lr>l<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + s<lr>l<g>\t%0,<1>%Y2 + s<lr>l<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) ; sldl, srdl (define_insn "*<shift>di3_31_and" @@ -7208,21 +7444,24 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -; sll, srl, sllg, srlg +; sll, srl, sllg, srlg, sllk, srlk (define_insn "*<shift><mode>3_and" - [(set (match_operand:GPR 0 "register_operand" "=d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") + (match_operand:SI 3 "const_int_operand" "n,n"))))] "(INTVAL (operands[3]) & 63) == 63" - "s<lr>l<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + s<lr>l<g>\t%0,<1>%Y2 + s<lr>l<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) ; ; ashr(di|si)3 instruction pattern(s). -; +; Arithmetic right shifts (define_expand "ashr<mode>3" [(parallel @@ -7266,44 +7505,53 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -; sra, srag +; sra, srag, srak (define_insn "*ashr<mode>3_cc" [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") + (set (match_operand:GPR 0 "register_operand" "=d,d") (ashiftrt:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCSmode)" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) -; sra, srag +; sra, srag, srak (define_insn "*ashr<mode>3_cconly" [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode(insn, CCSmode)" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) ; sra, srag (define_insn "*ashr<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) (clobber (reg:CC CC_REGNUM))] "" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) ; shift pattern with implicit ANDs @@ -7346,47 +7594,55 @@ [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -; sra, srag +; sra, srag, srak (define_insn "*ashr<mode>3_cc_and" [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") + (match_operand:SI 3 "const_int_operand" "n,n"))) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") + (set (match_operand:GPR 0 "register_operand" "=d,d") (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) -; sra, srag +; sra, srag, srak (define_insn "*ashr<mode>3_cconly_and" [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) + (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") + (match_operand:SI 3 "const_int_operand" "n,n"))) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "cpu_facility" "*,z196") + (set_attr "z10prop" "z10_super_E1,*")]) -; sra, srag +; sra, srag, srak (define_insn "*ashr<mode>3_and" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n")))) + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") + (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") + (match_operand:SI 3 "const_int_operand" "n,n")))) (clobber (reg:CC CC_REGNUM))] "(INTVAL (operands[3]) & 63) == 63" - "sra<g>\t%0,<1>%Y2" - [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "@ + sra<g>\t%0,<1>%Y2 + sra<gk>\t%0,%1,%Y2" + [(set_attr "op_type" "RS<E>,RSY") + (set_attr "atype" "reg,reg") + (set_attr "z10prop" "z10_super_E1,*")]) ;; @@ -7941,7 +8197,8 @@ (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") (set_attr "atype" "agen") - (set_attr "z10prop" "z10_c")]) + (set_attr "z10prop" "z10_c") + (set_attr "z196prop" "z196_cracked")]) (define_insn_and_split "doloop_di" [(set (pc) @@ -8261,7 +8518,8 @@ && GET_MODE (operands[2]) == Pmode" "bras\t%2,%0" [(set_attr "op_type" "RI") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*brasl" [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) @@ -8272,7 +8530,8 @@ && GET_MODE (operands[2]) == Pmode" "brasl\t%2,%0" [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*basr" [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) @@ -8289,7 +8548,8 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "jsr") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z196prop" "z196_cracked")]) ; ; call_value instruction pattern(s). @@ -8317,7 +8577,8 @@ && GET_MODE (operands[3]) == Pmode" "bras\t%3,%1" [(set_attr "op_type" "RI") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*brasl_r" [(set (match_operand 0 "" "") @@ -8329,7 +8590,8 @@ && GET_MODE (operands[3]) == Pmode" "brasl\t%3,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*basr_r" [(set (match_operand 0 "" "") @@ -8347,7 +8609,8 @@ (if_then_else (match_operand 1 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "jsr") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z196prop" "z196_cracked")]) ;; ;;- Thread-local storage support. @@ -8416,7 +8679,8 @@ && GET_MODE (operands[3]) == Pmode" "bras\t%3,%1%J4" [(set_attr "op_type" "RI") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*brasl_tls" [(set (match_operand 0 "" "") @@ -8429,7 +8693,8 @@ && GET_MODE (operands[3]) == Pmode" "brasl\t%3,%1%J4" [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "z196prop" "z196_cracked")]) (define_insn "*basr_tls" [(set (match_operand 0 "" "") @@ -8448,7 +8713,8 @@ (if_then_else (match_operand 1 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "jsr") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z196prop" "z196_cracked")]) ;; ;;- Atomic operations @@ -8557,6 +8823,36 @@ "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], false); DONE;") +; z196 load and add, xor, or and and instructions + +; lan, lang, lao, laog, lax, laxg, laa, laag +(define_insn "sync_<atomic><mode>" + [(parallel + [(set (match_operand:GPR 0 "memory_operand" "+QS") + (unspec_volatile:GPR + [(ATOMIC_Z196:GPR (match_dup 0) + (match_operand:GPR 1 "general_operand" "d"))] + UNSPECV_ATOMIC_OP)) + (clobber (match_scratch:GPR 2 "=d")) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_Z196" + "la<noxa><g>\t%2,%1,%0") + +; lan, lang, lao, laog, lax, laxg, laa, laag +(define_insn "sync_old_<atomic><mode>" + [(parallel + [(set (match_operand:GPR 0 "register_operand" "=d") + (match_operand:GPR 1 "memory_operand" "+QS")) + (set (match_dup 1) + (unspec_volatile + [(ATOMIC_Z196:GPR (match_dup 1) + (match_operand:GPR 2 "general_operand" "d"))] + UNSPECV_ATOMIC_OP)) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_Z196" + "la<noxa><g>\t%0,%2,%1") + + (define_expand "sync_<atomic><mode>" [(set (match_operand:HQI 0 "memory_operand") (ATOMIC:HQI (match_dup 0) @@ -8775,7 +9071,8 @@ "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "basr\t%0,0" [(set_attr "op_type" "RR") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z196prop" "z196_cracked")]) (define_insn "main_base_31_large" [(set (match_operand 0 "register_operand" "=a") @@ -8783,7 +9080,8 @@ (set (pc) (label_ref (match_operand 2 "" "")))] "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "bras\t%0,%2" - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z196prop" "z196_cracked")]) (define_insn "main_base_64" [(set (match_operand 0 "register_operand" "=a") @@ -8811,7 +9109,8 @@ "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "basr\t%0,0\;la\t%0,%1-.(%0)" [(set_attr "length" "6") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z196prop" "z196_cracked")]) (define_insn "reload_base_64" [(set (match_operand 0 "register_operand" "=a") @@ -8984,7 +9283,8 @@ } [(set_attr "type" "load,larl") (set_attr "op_type" "RXY,RIL") - (set_attr "z10prop" "z10_super")]) + (set_attr "z10prop" "z10_super") + (set_attr "z196prop" "z196_alone")]) ; @@ -9001,3 +9301,107 @@ [(set_attr "type" "*,load") (set_attr "op_type" "RRE,RXY") (set_attr "z10prop" "z10_super")]) + + +; +; Population count instruction +; + +; The S/390 popcount instruction counts the bits of op1 in 8 byte +; portions and stores the result in the corresponding bytes in op0. +(define_insn "*popcount<mode>" + [(set (match_operand:INT 0 "register_operand" "=d") + (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z196" + "popcnt\t%0,%1" + [(set_attr "op_type" "RRE")]) + +(define_expand "popcountdi2" + [; popcnt op0, op1 + (parallel [(set (match_operand:DI 0 "register_operand" "") + (unspec:DI [(match_operand:DI 1 "register_operand")] + UNSPEC_POPCNT)) + (clobber (reg:CC CC_REGNUM))]) + ; sllg op2, op0, 32 + (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) + ; agr op0, op2 + (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; sllg op2, op0, 16 + (set (match_operand:DI 2 "register_operand" "") + (ashift:DI (match_dup 0) (const_int 16))) + ; agr op0, op2 + (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; sllg op2, op0, 8 + (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) + ; agr op0, op2 + (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; srlg op0, op0, 56 + (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] + "TARGET_Z196 && TARGET_64BIT" + "operands[2] = gen_reg_rtx (DImode);") + +(define_expand "popcountsi2" + [; popcnt op0, op1 + (parallel [(set (match_operand:SI 0 "register_operand" "") + (unspec:SI [(match_operand:SI 1 "register_operand")] + UNSPEC_POPCNT)) + (clobber (reg:CC CC_REGNUM))]) + ; sllk op2, op0, 16 + (set (match_operand:SI 2 "register_operand" "") + (ashift:SI (match_dup 0) (const_int 16))) + ; ar op0, op2 + (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; sllk op2, op0, 8 + (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) + ; ar op0, op2 + (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; srl op0, op0, 24 + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] + "TARGET_Z196" + "operands[2] = gen_reg_rtx (SImode);") + +(define_expand "popcounthi2" + [; popcnt op0, op1 + (parallel [(set (match_operand:HI 0 "register_operand" "") + (unspec:HI [(match_operand:HI 1 "register_operand")] + UNSPEC_POPCNT)) + (clobber (reg:CC CC_REGNUM))]) + ; sllk op2, op0, 8 + (set (match_operand:SI 2 "register_operand" "") + (ashift:SI (match_dup 0) (const_int 8))) + ; ar op0, op2 + (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))]) + ; srl op0, op0, 8 + (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] + "TARGET_Z196" + "operands[2] = gen_reg_rtx (SImode);") + +(define_expand "popcountqi2" + [; popcnt op0, op1 + (parallel [(set (match_operand:QI 0 "register_operand" "") + (unspec:QI [(match_operand:QI 1 "register_operand")] + UNSPEC_POPCNT)) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_Z196" + "") + +;; +;;- Copy sign instructions +;; + +(define_insn "copysign<mode>3" + [(set (match_operand:FP 0 "register_operand" "=f") + (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") + (match_operand:FP 2 "register_operand" "f")] + UNSPEC_COPYSIGN))] + "TARGET_Z196" + "cpsdr\t%0,%2,%1" + [(set_attr "op_type" "RRF") + (set_attr "type" "fsimp<mode>")]) diff --git a/gcc/config/s390/t-linux64 b/gcc/config/s390/t-linux64 index 36aced09c2c..ede76a2cbf3 100644 --- a/gcc/config/s390/t-linux64 +++ b/gcc/config/s390/t-linux64 @@ -1,3 +1,10 @@ +# On Debian, Ubuntu and other derivative distributions, the 32bit libraries +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to +# /lib and /usr/lib, while other distributions install libraries into /lib64 +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, +# it doesn't tell anything about the 32bit libraries on those systems. Set +# MULTILIB_OSDIRNAMES according to what is found on the target. + MULTILIB_OPTIONS = m64/m31 MULTILIB_DIRNAMES = 64 32 -MULTILIB_OSDIRNAMES = ../lib64 ../lib +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) diff --git a/gcc/config/score/score-conv.h b/gcc/config/score/score-conv.h index e042dc1b7d3..3a40090dbc9 100644 --- a/gcc/config/score/score-conv.h +++ b/gcc/config/score/score-conv.h @@ -1,5 +1,5 @@ /* score-conv.h for Sunplus S+CORE processor - Copyright (C) 2005, 2007 Free Software Foundation, Inc. + Copyright (C) 2005, 2007, 2009, 2010 Free Software Foundation, Inc. This file is part of GCC. @@ -20,8 +20,6 @@ #ifndef GCC_SCORE_CONV_H #define GCC_SCORE_CONV_H -extern int target_flags; - #define GP_REG_FIRST 0U #define GP_REG_LAST 31U #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1U) diff --git a/gcc/config/score/score.c b/gcc/config/score/score.c index f2b2215f617..764293a9d65 100644 --- a/gcc/config/score/score.c +++ b/gcc/config/score/score.c @@ -295,11 +295,6 @@ score_handle_option (size_t code, const char *arg, int value) { switch (code) { - case OPT_G: - g_switch_value = value; - g_switch_set = true; - return true; - case OPT_mscore7d: target_flags &= ~(MASK_ALL_CPU_BITS); target_flags |= MASK_SCORE7 | MASK_SCORE7D; diff --git a/gcc/config/score/score3.c b/gcc/config/score/score3.c index d4b171e05d2..fd2e7844abd 100644 --- a/gcc/config/score/score3.c +++ b/gcc/config/score/score3.c @@ -641,11 +641,13 @@ score3_option_override (void) { flag_pic = false; if (!flag_pic) - score3_sdata_max = g_switch_set ? g_switch_value : SCORE3_DEFAULT_SDATA_MAX; + score3_sdata_max = (global_options_set.x_g_switch_value + ? g_switch_value + : SCORE3_DEFAULT_SDATA_MAX); else { score3_sdata_max = 0; - if (g_switch_set && (g_switch_value != 0)) + if (global_options_set.x_g_switch_value && (g_switch_value != 0)) warning (0, "-fPIC and -G are incompatible"); } diff --git a/gcc/config/score/score7.c b/gcc/config/score/score7.c index f1c86230d54..85ae0171790 100644 --- a/gcc/config/score/score7.c +++ b/gcc/config/score/score7.c @@ -640,11 +640,13 @@ score7_option_override (void) { flag_pic = false; if (!flag_pic) - score7_sdata_max = g_switch_set ? g_switch_value : SCORE7_DEFAULT_SDATA_MAX; + score7_sdata_max = (global_options_set.x_g_switch_value + ? g_switch_value + : SCORE7_DEFAULT_SDATA_MAX); else { score7_sdata_max = 0; - if (g_switch_set && (g_switch_value != 0)) + if (global_options_set.x_g_switch_value && (g_switch_value != 0)) warning (0, "-fPIC and -G are incompatible"); } diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 1e8b141813a..1c201bbe6a3 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -6860,6 +6860,7 @@ sh_expand_prologue (void) int d_rounding = 0; int save_flags = target_flags; int pretend_args; + int stack_usage; tree sp_switch_attr = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)); @@ -6876,6 +6877,7 @@ sh_expand_prologue (void) output_stack_adjust (-pretend_args - crtl->args.info.stack_regs * 8, stack_pointer_rtx, 0, NULL, false); + stack_usage = pretend_args + crtl->args.info.stack_regs * 8; if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie) /* We're going to use the PIC register to load the address of the @@ -6934,6 +6936,7 @@ sh_expand_prologue (void) )) break; push (rn); + stack_usage += GET_MODE_SIZE (SImode); } } } @@ -7006,6 +7009,7 @@ sh_expand_prologue (void) output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx, 0, NULL, true); + stack_usage += save_size + d_rounding; sh5_schedule_saves (&live_regs_mask, &schedule, offset_base); tmp_pnt = schedule.temps; @@ -7157,7 +7161,10 @@ sh_expand_prologue (void) gcc_assert (entry->offset == d_rounding); } else - push_regs (&live_regs_mask, current_function_interrupt); + { + push_regs (&live_regs_mask, current_function_interrupt); + stack_usage += d; + } if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) emit_insn (gen_GOTaddr2picreg ()); @@ -7181,6 +7188,7 @@ sh_expand_prologue (void) output_stack_adjust (-rounded_frame_size (d) + d_rounding, stack_pointer_rtx, 0, NULL, true); + stack_usage += rounded_frame_size (d) - d_rounding; if (frame_pointer_needed) frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx)); @@ -7194,6 +7202,9 @@ sh_expand_prologue (void) "__GCC_shcompact_incoming_args", SFUNC_GOT); emit_insn (gen_shcompact_incoming_args ()); } + + if (flag_stack_usage) + current_function_static_stack_size = stack_usage; } void diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 2e9ee76d3ef..01236c18ab4 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -503,8 +503,6 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 -extern const char *sh_fixed_range_str; - /* Target machine storage layout. */ @@ -2546,8 +2544,6 @@ enum processor_type { #define sh_cpu_attr ((enum attr_cpu)sh_cpu) extern enum processor_type sh_cpu; -extern int optimize; /* needed for gen_casesi. */ - enum mdep_reorg_phase_e { SH_BEFORE_MDEP_REORG, diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 95e2ca439d5..f10408fb02b 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -1,6 +1,7 @@ ; Options for the SH port of the compiler. -; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. +; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 +; Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -106,11 +107,11 @@ Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Generate SH4-200 FPU-less code m4-300-nofpu -Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists +Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) Generate SH4-300 FPU-less code m4-340 -Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists +Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) Generate code for SH4 340 series (MMU/FPU-less) ;; passes -isa=sh4-nommu-nofpu to the assembler. @@ -137,7 +138,7 @@ Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Generate default single-precision SH4-200 code m4-300-single -Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists +Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) Generate default single-precision SH4-300 code m4-single-only @@ -153,7 +154,7 @@ Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Generate only single-precision SH4-200 code m4-300-single-only -Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists +Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) Generate only single-precision SH4-300 code m4a diff --git a/gcc/config/sol2.opt b/gcc/config/sol2.opt new file mode 100644 index 00000000000..2da2ab5774c --- /dev/null +++ b/gcc/config/sol2.opt @@ -0,0 +1,23 @@ +; Options for the Solaris 2 port of the compiler +; +; Copyright (C) 2010 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT +; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +; License for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. + +mimpure-text +Target Report +Pass -z text to linker diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 35a280ffc10..17de80da06f 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -34,10 +34,6 @@ munaligned-doubles Target Report Mask(UNALIGNED_DOUBLES) Assume possible double misalignment -mimpure-text -Target Report -Pass -assert pure-text to linker - mapp-regs Target Report Mask(APP_REGS) Use ABI reserved registers diff --git a/gcc/config/sparc/t-linux64 b/gcc/config/sparc/t-linux64 index 67acb7e1ea6..97c28ba2233 100644 --- a/gcc/config/sparc/t-linux64 +++ b/gcc/config/sparc/t-linux64 @@ -17,9 +17,16 @@ # along with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. +# On Debian, Ubuntu and other derivative distributions, the 32bit libraries +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to +# /lib and /usr/lib, while other distributions install libraries into /lib64 +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, +# it doesn't tell anything about the 32bit libraries on those systems. Set +# MULTILIB_OSDIRNAMES according to what is found on the target. + MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 -MULTILIB_OSDIRNAMES = ../lib64 ../lib +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/spu/spu-c.c b/gcc/config/spu/spu-c.c index 1f22cd6fb7c..b8ac433ccbd 100644 --- a/gcc/config/spu/spu-c.c +++ b/gcc/config/spu/spu-c.c @@ -95,7 +95,7 @@ spu_resolve_overloaded_builtin (location_t loc, tree fndecl, void *passed_args) || POINTER_TYPE_P (t)) VEC(tree,gc) *fnargs = (VEC(tree,gc) *) passed_args; unsigned int nargs = VEC_length (tree, fnargs); - int new_fcode, fcode = DECL_FUNCTION_CODE (fndecl) - END_BUILTINS; + int new_fcode, fcode = DECL_FUNCTION_CODE (fndecl); struct spu_builtin_description *desc; tree match = NULL_TREE; diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 8b462ecf5e3..d2f10ac18e2 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -472,6 +472,9 @@ static const struct attribute_spec spu_attribute_table[] = #undef TARGET_OPTION_OPTIMIZATION #define TARGET_OPTION_OPTIMIZATION spu_option_optimization +#undef TARGET_EXCEPT_UNWIND_INFO +#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info + struct gcc_target targetm = TARGET_INITIALIZER; static void @@ -5713,8 +5716,7 @@ spu_init_builtins (void) sprintf (name, "__builtin_%s", d->name); spu_builtin_decls[i] = - add_builtin_function (name, p, END_BUILTINS + i, BUILT_IN_MD, - NULL, NULL_TREE); + add_builtin_function (name, p, i, BUILT_IN_MD, NULL, NULL_TREE); if (d->fcode == SPU_MASK_FOR_LOAD) TREE_READONLY (spu_builtin_decls[i]) = 1; @@ -6642,7 +6644,7 @@ spu_expand_builtin (tree exp, int ignore ATTRIBUTE_UNUSED) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl) - END_BUILTINS; + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); struct spu_builtin_description *d; if (fcode < NUM_SPU_BUILTINS) diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h index 878cb6383e5..9f72cb228f5 100644 --- a/gcc/config/spu/spu.h +++ b/gcc/config/spu/spu.h @@ -24,9 +24,6 @@ #define INIT_EXPANDERS spu_init_expanders() -extern int target_flags; -extern const char *spu_fixed_range_string; - /* Which processor to generate code or schedule for. */ enum processor_type { diff --git a/gcc/config/spu/spu.opt b/gcc/config/spu/spu.opt index 4ad7128de51..75cf8c3fd39 100644 --- a/gcc/config/spu/spu.opt +++ b/gcc/config/spu/spu.opt @@ -1,5 +1,5 @@ ; Options for the SPU port of the compiler -; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc. +; Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ; This file is free software; you can redistribute it and/or modify it under ; the terms of the GNU General Public License as published by the Free @@ -88,7 +88,7 @@ Target Report RejectNegative Var(spu_ea_model,32) Init(32) Access variables in 32-bit PPU objects (default) mea64 -Target Report RejectNegative Var(spu_ea_model,64) VarExists +Target Report RejectNegative Var(spu_ea_model,64) Access variables in 64-bit PPU objects maddress-space-conversion diff --git a/gcc/config/vxworksae.h b/gcc/config/vxworksae.h index a093eda1d9f..d29b465eda0 100644 --- a/gcc/config/vxworksae.h +++ b/gcc/config/vxworksae.h @@ -55,3 +55,13 @@ along with GCC; see the file COPYING3. If not see #define VXWORKS_STARTFILE_SPEC "" #define VXWORKS_KIND VXWORKS_KIND_AE + +/* A VxWorks 653 implementation of TARGET_OS_CPP_BUILTINS. */ +#define VXWORKS_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__vxworks"); \ + builtin_define ("__VXWORKS__"); \ + } \ + while (0) + diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 1bc2fdef074..7dc22a2a466 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -22,9 +22,6 @@ along with GCC; see the file COPYING3. If not see /* Get Xtensa configuration settings */ #include "xtensa-config.h" -/* Standard GCC variables that we reference. */ -extern int optimize; - /* External variables defined in xtensa.c. */ extern unsigned xtensa_current_frame_size; |