2009-12-07 Basile Starynkevitch <basile@starynkevitch.net>

        MELT branch merged with trunk rev 155029



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@155032 138bc75d-0d04-0410-961f-82ee72b054a4

11 files changed, 435 insertions, 674 deletions

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 82f75f9b733..cd317f1eae9 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1310,7 +1310,7 @@
          (mult:SI (match_operand:SI 1 "register_operand" "%0")
 	          (match_operand:SI 2 "register_operand" "l"))
          (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r"))]
+   (clobber (match_scratch:SI 0 "=l"))]
   "TARGET_THUMB2 && optimize_size"
   "muls\\t%0, %2, %0"
   [(set_attr "length" "2")
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ade3a7d6d32..6cd9d7dc740 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -30307,7 +30307,8 @@ ix86_enum_va_list (int idx, const char **pname, tree *ptree)
 #define TARGET_DEFAULT_TARGET_FLAGS	\
   (TARGET_DEFAULT			\
    | TARGET_SUBTARGET_DEFAULT		\
-   | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
+   | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
+   | MASK_FUSED_MADD)
 
 #undef TARGET_HANDLE_OPTION
 #define TARGET_HANDLE_OPTION ix86_handle_option
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index eb1c86fa2a8..860d234efbd 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -546,8 +546,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
 %{msse5:-mavx \
 %n'-msse5' was removed.\n} \
-%{mfused-madd:-mavx \
-%n'-mfused-madd' was removed.\n} \
 %{mno-intel-syntax:-masm=att \
 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 1ef3025ef56..9fd9f9aaf5d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -788,7 +788,7 @@
 (define_mode_attr i [(QI "n") (HI "n") (SI "i") (DI "e")])
 
 ;; General operand constraint for word modes.
-(define_mode_attr g [(SI "g") (DI "rme")])
+(define_mode_attr g [(QI "qmn") (HI "rmn") (SI "g") (DI "rme")])
 
 ;; Immediate operand constraint for double integer modes.
 (define_mode_attr di [(SI "iF") (DI "e")])
@@ -801,6 +801,13 @@
 	 (DI "x86_64_general_operand")
 	 (TI "x86_64_general_operand")])
 
+;; General sign/zero extend operand predicate for integer modes.
+(define_mode_attr general_szext_operand
+	[(QI "general_operand")
+	 (HI "general_operand")
+	 (SI "general_operand")
+	 (DI "x86_64_szext_general_operand")])
+
 ;; SSE and x87 SFmode and DFmode floating point modes
 (define_mode_iterator MODEF [SF DF])
 
@@ -8110,39 +8117,6 @@
 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
 ;; Note that this excludes ah.
 
-(define_insn "*testdi_1_rex64"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
-		  (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
-	  (const_int 0)))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "@
-   test{l}\t{%k1, %k0|%k0, %k1}
-   test{l}\t{%k1, %k0|%k0, %k1}
-   test{q}\t{%1, %0|%0, %1}
-   test{q}\t{%1, %0|%0, %1}
-   test{q}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "test")
-   (set_attr "modrm" "0,1,0,1,1")
-   (set_attr "mode" "SI,SI,DI,DI,DI")
-   (set_attr "pent_pair" "uv,np,uv,np,uv")])
-
-(define_insn "testsi_1"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
-		  (match_operand:SI 1 "general_operand" "i,i,ri"))
-	  (const_int 0)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "test{l}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "test")
-   (set_attr "modrm" "0,1,1")
-   (set_attr "mode" "SI")
-   (set_attr "pent_pair" "uv,np,uv")])
-
 (define_expand "testsi_ccno_1"
   [(set (reg:CCNO FLAGS_REG)
 	(compare:CCNO
@@ -8152,19 +8126,6 @@
   ""
   "")
 
-(define_insn "*testhi_1"
-  [(set (reg FLAGS_REG)
-        (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
-			 (match_operand:HI 1 "general_operand" "n,n,rn"))
-		 (const_int 0)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "test{w}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "test")
-   (set_attr "modrm" "0,1,1")
-   (set_attr "mode" "HI")
-   (set_attr "pent_pair" "uv,np,uv")])
-
 (define_expand "testqi_ccz_1"
   [(set (reg:CCZ FLAGS_REG)
         (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
@@ -8173,6 +8134,25 @@
   ""
   "")
 
+(define_insn "*testdi_1"
+  [(set (reg FLAGS_REG)
+	(compare
+	 (and:DI
+	  (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
+	  (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
+	 (const_int 0)))]
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+   test{l}\t{%k1, %k0|%k0, %k1}
+   test{l}\t{%k1, %k0|%k0, %k1}
+   test{q}\t{%1, %0|%0, %1}
+   test{q}\t{%1, %0|%0, %1}
+   test{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,0,1,1")
+   (set_attr "mode" "SI,SI,DI,DI,DI")])
+
 (define_insn "*testqi_1_maybe_si"
   [(set (reg FLAGS_REG)
         (compare
@@ -8198,19 +8178,19 @@
    (set_attr "mode" "QI,QI,QI,SI")
    (set_attr "pent_pair" "uv,np,uv,np")])
 
-(define_insn "*testqi_1"
+(define_insn "*test<mode>_1"
   [(set (reg FLAGS_REG)
-        (compare
-	  (and:QI
-	    (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
-	    (match_operand:QI 1 "general_operand" "n,n,qn"))
-	  (const_int 0)))]
-  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
-   && ix86_match_ccmode (insn, CCNOmode)"
-  "test{b}\t{%1, %0|%0, %1}"
+	(compare
+	 (and:SWI124
+	  (match_operand:SWI124 0 "nonimmediate_operand" "%!*a,<r>,<r>m")
+	  (match_operand:SWI124 1 "general_operand" "<i>,<i>,<r><i>"))
+	 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "test{<imodesuffix>}\t{%1, %0|%0, %1}"
   [(set_attr "type" "test")
    (set_attr "modrm" "0,1,1")
-   (set_attr "mode" "QI")
+   (set_attr "mode" "<MODE>")
    (set_attr "pent_pair" "uv,np,uv")])
 
 (define_expand "testqi_ext_ccno_0"
@@ -8244,7 +8224,7 @@
    (set_attr "modrm" "1")
    (set_attr "pent_pair" "np")])
 
-(define_insn "*testqi_ext_1"
+(define_insn "*testqi_ext_1_rex64"
   [(set (reg FLAGS_REG)
 	(compare
 	  (and:SI
@@ -8253,15 +8233,14 @@
 	      (const_int 8)
 	      (const_int 8))
 	    (zero_extend:SI
-	      (match_operand:QI 1 "general_operand" "Qm")))
+	      (match_operand:QI 1 "register_operand" "Q")))
 	  (const_int 0)))]
-  "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "type" "test")
    (set_attr "mode" "QI")])
 
-(define_insn "*testqi_ext_1_rex64"
+(define_insn "*testqi_ext_1"
   [(set (reg FLAGS_REG)
 	(compare
 	  (and:SI
@@ -8270,9 +8249,9 @@
 	      (const_int 8)
 	      (const_int 8))
 	    (zero_extend:SI
-	      (match_operand:QI 1 "register_operand" "Q")))
+	      (match_operand:QI 1 "general_operand" "Qm")))
 	  (const_int 0)))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
+  "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "type" "test")
    (set_attr "mode" "QI")])
@@ -8295,24 +8274,6 @@
   [(set_attr "type" "test")
    (set_attr "mode" "QI")])
 
-;; Combine likes to form bit extractions for some tests.  Humor it.
-(define_insn "*testqi_ext_3"
-  [(set (reg FLAGS_REG)
-        (compare (zero_extract:SI
-		   (match_operand 0 "nonimmediate_operand" "rm")
-		   (match_operand:SI 1 "const_int_operand" "")
-		   (match_operand:SI 2 "const_int_operand" ""))
-		 (const_int 0)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && INTVAL (operands[1]) > 0
-   && INTVAL (operands[2]) >= 0
-   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
-   && (GET_MODE (operands[0]) == SImode
-       || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
-       || GET_MODE (operands[0]) == HImode
-       || GET_MODE (operands[0]) == QImode)"
-  "#")
-
 (define_insn "*testqi_ext_3_rex64"
   [(set (reg FLAGS_REG)
         (compare (zero_extract:DI
@@ -8334,6 +8295,24 @@
        || GET_MODE (operands[0]) == QImode)"
   "#")
 
+;; Combine likes to form bit extractions for some tests.  Humor it.
+(define_insn "*testqi_ext_3"
+  [(set (reg FLAGS_REG)
+        (compare (zero_extract:SI
+		   (match_operand 0 "nonimmediate_operand" "rm")
+		   (match_operand:SI 1 "const_int_operand" "")
+		   (match_operand:SI 2 "const_int_operand" ""))
+		 (const_int 0)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && INTVAL (operands[1]) > 0
+   && INTVAL (operands[2]) >= 0
+   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
+   && (GET_MODE (operands[0]) == SImode
+       || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
+       || GET_MODE (operands[0]) == HImode
+       || GET_MODE (operands[0]) == QImode)"
+  "#")
+
 (define_split
   [(set (match_operand 0 "flags_reg_operand" "")
         (match_operator 1 "compare_operator"
@@ -8433,22 +8412,22 @@
   "operands[2] = gen_lowpart (QImode, operands[2]);
    operands[3] = gen_lowpart (QImode, operands[3]);")
 
-
 ;; %%% This used to optimize known byte-wide and operations to memory,
 ;; and sometimes to QImode registers.  If this is considered useful,
 ;; it should be done with splitters.
 
-(define_expand "anddi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(and:DI (match_operand:DI 1 "nonimmediate_operand" "")
-		(match_operand:DI 2 "x86_64_szext_general_operand" "")))]
-  "TARGET_64BIT"
-  "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
+(define_expand "and<mode>3"
+  [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
+	(and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
+		  (match_operand:SWIM 2 "<general_szext_operand>" "")))]
+  ""
+  "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
 
-(define_insn "*anddi_1_rex64"
+(define_insn "*anddi_1"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
-	(and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
-		(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
+	(and:DI
+	 (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
+	 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
 {
@@ -8493,29 +8472,6 @@
        (const_string "*")))
    (set_attr "mode" "SI,DI,DI,SI")])
 
-(define_insn "*anddi_2"
-  [(set (reg FLAGS_REG)
-	(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
-			 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
-		 (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
-	(and:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, DImode, operands)"
-  "@
-   and{l}\t{%k2, %k0|%k0, %k2}
-   and{q}\t{%2, %0|%0, %2}
-   and{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI,DI,DI")])
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(and:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
-
 (define_insn "*andsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
 	(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
@@ -8561,43 +8517,6 @@
    (set_attr "length_immediate" "*,*,0")
    (set_attr "mode" "SI")])
 
-(define_split
-  [(set (match_operand 0 "register_operand" "")
-	(and (match_dup 0)
-	     (const_int -65536)))
-   (clobber (reg:CC FLAGS_REG))]
-  "optimize_function_for_size_p (cfun) || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
-  [(set (strict_low_part (match_dup 1)) (const_int 0))]
-  "operands[1] = gen_lowpart (HImode, operands[0]);")
-
-(define_split
-  [(set (match_operand 0 "ext_register_operand" "")
-	(and (match_dup 0)
-	     (const_int -256)))
-   (clobber (reg:CC FLAGS_REG))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
-  [(set (strict_low_part (match_dup 1)) (const_int 0))]
-  "operands[1] = gen_lowpart (QImode, operands[0]);")
-
-(define_split
-  [(set (match_operand 0 "ext_register_operand" "")
-	(and (match_dup 0)
-	     (const_int -65281)))
-   (clobber (reg:CC FLAGS_REG))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
-  [(parallel [(set (zero_extract:SI (match_dup 0)
-				    (const_int 8)
-				    (const_int 8))
-		   (xor:SI
-		     (zero_extract:SI (match_dup 0)
-				      (const_int 8)
-				      (const_int 8))
-		     (zero_extract:SI (match_dup 0)
-				      (const_int 8)
-				      (const_int 8))))
-	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);")
-
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 (define_insn "*andsi_1_zext"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8610,40 +8529,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
-(define_insn "*andsi_2"
-  [(set (reg FLAGS_REG)
-	(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:SI 2 "general_operand" "g,ri"))
-		 (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
-	(and:SI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, SImode, operands)"
-  "and{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*andsi_2_zext"
-  [(set (reg FLAGS_REG)
-	(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-			 (match_operand:SI 2 "general_operand" "g"))
-		 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, SImode, operands)"
-  "and{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-(define_expand "andhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-	(and:HI (match_operand:HI 1 "nonimmediate_operand" "")
-		(match_operand:HI 2 "general_operand" "")))]
-  "TARGET_HIMODE_MATH"
-  "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
-
 (define_insn "*andhi_1"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
 	(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
@@ -8674,26 +8559,6 @@
        (const_string "*")))
    (set_attr "mode" "HI,HI,SI")])
 
-(define_insn "*andhi_2"
-  [(set (reg FLAGS_REG)
-	(compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:HI 2 "general_operand" "rmn,rn"))
-		 (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
-	(and:HI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, HImode, operands)"
-  "and{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_expand "andqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-	(and:QI (match_operand:QI 1 "nonimmediate_operand" "")
-		(match_operand:QI 2 "general_operand" "")))]
-  "TARGET_QIMODE_MATH"
-  "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
-
 ;; %%% Potential partial reg stall on alternative 2.  What to do?
 (define_insn "*andqi_1"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
@@ -8713,17 +8578,75 @@
 	(and:QI (match_dup 0)
 		(match_operand:QI 1 "general_operand" "qn,qmn")))
    (clobber (reg:CC FLAGS_REG))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "and{b}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
    (set_attr "mode" "QI")])
 
+(define_split
+  [(set (match_operand 0 "register_operand" "")
+	(and (match_dup 0)
+	     (const_int -65536)))
+   (clobber (reg:CC FLAGS_REG))]
+  "(TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)
+    || optimize_function_for_size_p (cfun)"
+  [(set (strict_low_part (match_dup 1)) (const_int 0))]
+  "operands[1] = gen_lowpart (HImode, operands[0]);")
+
+(define_split
+  [(set (match_operand 0 "ext_register_operand" "")
+	(and (match_dup 0)
+	     (const_int -256)))
+   (clobber (reg:CC FLAGS_REG))]
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+   && reload_completed"
+  [(set (strict_low_part (match_dup 1)) (const_int 0))]
+  "operands[1] = gen_lowpart (QImode, operands[0]);")
+
+(define_split
+  [(set (match_operand 0 "ext_register_operand" "")
+	(and (match_dup 0)
+	     (const_int -65281)))
+   (clobber (reg:CC FLAGS_REG))]
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+   && reload_completed"
+  [(parallel [(set (zero_extract:SI (match_dup 0)
+				    (const_int 8)
+				    (const_int 8))
+		   (xor:SI
+		     (zero_extract:SI (match_dup 0)
+				      (const_int 8)
+				      (const_int 8))
+		     (zero_extract:SI (match_dup 0)
+				      (const_int 8)
+				      (const_int 8))))
+	      (clobber (reg:CC FLAGS_REG))])]
+  "operands[0] = gen_lowpart (SImode, operands[0]);")
+
+(define_insn "*anddi_2"
+  [(set (reg FLAGS_REG)
+	(compare
+	 (and:DI
+	  (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
+	  (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
+	(and:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, DImode, operands)"
+  "@
+   and{l}\t{%k2, %k0|%k0, %k2}
+   and{q}\t{%2, %0|%0, %2}
+   and{q}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI,DI,DI")])
+
 (define_insn "*andqi_2_maybe_si"
   [(set (reg FLAGS_REG)
 	(compare (and:QI
-		      (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
-		      (match_operand:QI 2 "general_operand" "qmn,qn,n"))
+		  (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+		  (match_operand:QI 2 "general_operand" "qmn,qn,n"))
 		 (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
 	(and:QI (match_dup 1) (match_dup 2)))]
@@ -8743,19 +8666,34 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI,QI,SI")])
 
-(define_insn "*andqi_2"
+(define_insn "*and<mode>_2"
   [(set (reg FLAGS_REG)
-	(compare (and:QI
-		   (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		   (match_operand:QI 2 "general_operand" "qmn,qn"))
+	(compare (and:SWI124
+		  (match_operand:SWI124 1 "nonimmediate_operand" "%0,0")
+		  (match_operand:SWI124 2 "general_operand" "<g>,<r><i>"))
 		 (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
-	(and:QI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:SWI124 0 "nonimmediate_operand" "=<r>,<r>m")
+	(and:SWI124 (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, QImode, operands)"
-  "and{b}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
+  "and{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
+   (set_attr "mode" "<MODE>")])
+
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*andsi_2_zext"
+  [(set (reg FLAGS_REG)
+	(compare (and:SI
+		  (match_operand:SI 1 "nonimmediate_operand" "%0")
+		  (match_operand:SI 2 "general_operand" "g"))
+		 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, SImode, operands)"
+  "and{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "*andqi_2_slp"
   [(set (reg FLAGS_REG)
@@ -8765,7 +8703,7 @@
 		 (const_int 0)))
    (set (strict_low_part (match_dup 0))
 	(and:QI (match_dup 0) (match_dup 1)))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && ix86_match_ccmode (insn, CCNOmode)
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "and{b}\t{%1, %0|%0, %1}"
@@ -8775,7 +8713,6 @@
 ;; ??? A bug in recog prevents it from recognizing a const_int as an
 ;; operand to zero_extend in andqi_ext_1.  It was checking explicitly
 ;; for a QImode operand, which of course failed.
-
 (define_insn "andqi_ext_0"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
@@ -8796,7 +8733,6 @@
 
 ;; Generated by peephole translating test to and.  This shows up
 ;; often in fp comparisons.
-
 (define_insn "*andqi_ext_0_cc"
   [(set (reg FLAGS_REG)
 	(compare
@@ -8823,7 +8759,7 @@
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
-(define_insn "*andqi_ext_1"
+(define_insn "*andqi_ext_1_rex64"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -8833,15 +8769,15 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand:QI 2 "general_operand" "Qm"))))
+	    (match_operand 2 "ext_register_operand" "Q"))))
    (clobber (reg:CC FLAGS_REG))]
-  "!TARGET_64BIT"
+  "TARGET_64BIT"
   "and{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
    (set_attr "mode" "QI")])
 
-(define_insn "*andqi_ext_1_rex64"
+(define_insn "*andqi_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -8851,9 +8787,9 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand 2 "ext_register_operand" "Q"))))
+	    (match_operand:QI 2 "general_operand" "Qm"))))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT"
+  "!TARGET_64BIT"
   "and{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
@@ -8929,68 +8865,36 @@
 ;; %%% This used to optimize known byte-wide and operations to memory.
 ;; If this is considered useful, it should be done with splitters.
 
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
-		(match_operand:DI 2 "x86_64_general_operand" "")))]
-  "TARGET_64BIT"
-  "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
+(define_expand "ior<mode>3"
+  [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
+	(ior:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
+		  (match_operand:SWIM 2 "<general_operand>" "")))]
+  ""
+  "ix86_expand_binary_operator (IOR, <MODE>mode, operands); DONE;")
 
-(define_insn "*iordi_1_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
-	(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:DI 2 "x86_64_general_operand" "re,rme")))
+(define_insn "*ior<mode>_1"
+  [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
+	(ior:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
+		    (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && ix86_binary_operator_ok (IOR, DImode, operands)"
-  "or{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-(define_insn "*iordi_2_rex64"
-  [(set (reg FLAGS_REG)
-	(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
-		 (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
-	(ior:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT
-   && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (IOR, DImode, operands)"
-  "or{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-(define_insn "*iordi_3_rex64"
-  [(set (reg FLAGS_REG)
-	(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
-			 (match_operand:DI 2 "x86_64_general_operand" "rem"))
-		 (const_int 0)))
-   (clobber (match_scratch:DI 0 "=r"))]
-  "TARGET_64BIT
-   && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (IOR, DImode, operands)"
-  "or{q}\t{%2, %0|%0, %2}"
+  "ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
+  "or{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*iorsi_1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,g")))
+;; %%% Potential partial reg stall on alternative 2.  What to do?
+(define_insn "*iorqi_1"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
+	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+		(match_operand:QI 2 "general_operand" "qmn,qn,rn")))
    (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (IOR, SImode, operands)"
-  "or{l}\t{%2, %0|%0, %2}"
+  "ix86_binary_operator_ok (IOR, QImode, operands)"
+  "@
+   or{b}\t{%2, %0|%0, %2}
+   or{b}\t{%2, %0|%0, %2}
+   or{l}\t{%k2, %k0|%k0, %k2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "QI,QI,SI")])
 
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 (define_insn "*iorsi_1_zext"
@@ -9009,23 +8913,35 @@
 	(ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
 		(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
   "or{l}\t{%2, %k0|%k0, %2}"
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
-(define_insn "*iorsi_2"
+(define_insn "*iorqi_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
+	(ior:QI (match_dup 0)
+		(match_operand:QI 1 "general_operand" "qmn,qn")))
+   (clobber (reg:CC FLAGS_REG))]
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "or{b}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "QI")])
+
+(define_insn "*ior<mode>_2"
   [(set (reg FLAGS_REG)
-	(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:SI 2 "general_operand" "g,ri"))
+	(compare (ior:SWI
+		  (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
+		  (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
 		 (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
-	(ior:SI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+	(ior:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (IOR, SImode, operands)"
-  "or{l}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
+  "or{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "<MODE>")])
 
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 ;; ??? Special case for immediate operand is missing - it is tricky.
@@ -9044,8 +8960,9 @@
 
 (define_insn "*iorsi_2_zext_imm"
   [(set (reg FLAGS_REG)
-	(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-			 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
+	(compare (ior:SI
+		  (match_operand:SI 1 "nonimmediate_operand" "%0")
+		  (match_operand:SI 2 "x86_64_zext_immediate_operand" "Z"))
 		 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
@@ -9055,105 +8972,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
-(define_insn "*iorsi_3"
-  [(set (reg FLAGS_REG)
-	(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-			 (match_operand:SI 2 "general_operand" "g"))
-		 (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r"))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "or{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-(define_expand "iorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-	(ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
-		(match_operand:HI 2 "general_operand" "")))]
-  "TARGET_HIMODE_MATH"
-  "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
-
-(define_insn "*iorhi_1"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
-	(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "rmn,rn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (IOR, HImode, operands)"
-  "or{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_insn "*iorhi_2"
-  [(set (reg FLAGS_REG)
-	(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:HI 2 "general_operand" "rmn,rn"))
-		 (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
-	(ior:HI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (IOR, HImode, operands)"
-  "or{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_insn "*iorhi_3"
-  [(set (reg FLAGS_REG)
-	(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
-			 (match_operand:HI 2 "general_operand" "rmn"))
-		 (const_int 0)))
-   (clobber (match_scratch:HI 0 "=r"))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "or{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_expand "iorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
-		(match_operand:QI 2 "general_operand" "")))]
-  "TARGET_QIMODE_MATH"
-  "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
-
-;; %%% Potential partial reg stall on alternative 2.  What to do?
-(define_insn "*iorqi_1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
-	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
-		(match_operand:QI 2 "general_operand" "qmn,qn,rn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (IOR, QImode, operands)"
-  "@
-   or{b}\t{%2, %0|%0, %2}
-   or{b}\t{%2, %0|%0, %2}
-   or{l}\t{%k2, %k0|%k0, %k2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "QI,QI,SI")])
-
-(define_insn "*iorqi_1_slp"
-  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
-	(ior:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "qmn,qn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "or{b}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "mode" "QI")])
-
-(define_insn "*iorqi_2"
-  [(set (reg FLAGS_REG)
-	(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:QI 2 "general_operand" "qmn,qn"))
-		 (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
-	(ior:QI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (IOR, QImode, operands)"
-  "or{b}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
-
 (define_insn "*iorqi_2_slp"
   [(set (reg FLAGS_REG)
 	(compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
@@ -9161,24 +8979,25 @@
 		 (const_int 0)))
    (set (strict_low_part (match_dup 0))
 	(ior:QI (match_dup 0) (match_dup 1)))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && ix86_match_ccmode (insn, CCNOmode)
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "or{b}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
    (set_attr "mode" "QI")])
 
-(define_insn "*iorqi_3"
+(define_insn "*ior<mode>_3"
   [(set (reg FLAGS_REG)
-	(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
-			 (match_operand:QI 2 "general_operand" "qmn"))
+	(compare (ior:SWI
+		  (match_operand:SWI 1 "nonimmediate_operand" "%0")
+		  (match_operand:SWI 2 "<general_operand>" "<g>"))
 		 (const_int 0)))
-   (clobber (match_scratch:QI 0 "=q"))]
+   (clobber (match_scratch:SWI 0 "=<r>"))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "or{b}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
+  "or{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*iorqi_ext_0"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
@@ -9191,14 +9010,14 @@
 	    (const_int 8))
 	  (match_operand 2 "const_int_operand" "n")))
    (clobber (reg:CC FLAGS_REG))]
-  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
+  "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "or{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
-(define_insn "*iorqi_ext_1"
+(define_insn "*iorqi_ext_1_rex64"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -9208,16 +9027,16 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand:QI 2 "general_operand" "Qm"))))
+	    (match_operand 2 "ext_register_operand" "Q"))))
    (clobber (reg:CC FLAGS_REG))]
-  "!TARGET_64BIT
+  "TARGET_64BIT
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
   "or{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
    (set_attr "mode" "QI")])
 
-(define_insn "*iorqi_ext_1_rex64"
+(define_insn "*iorqi_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -9227,9 +9046,9 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand 2 "ext_register_operand" "Q"))))
+	    (match_operand:QI 2 "general_operand" "Qm"))))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
+  "!TARGET_64BIT
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
   "or{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
@@ -9248,7 +9067,7 @@
 	  		   (const_int 8)
 			   (const_int 8))))
    (clobber (reg:CC FLAGS_REG))]
-  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
+  "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "ior{b}\t{%h2, %h0|%h0, %h2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
@@ -9299,67 +9118,36 @@
 ;; %%% This used to optimize known byte-wide and operations to memory.
 ;; If this is considered useful, it should be done with splitters.
 
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
-		(match_operand:DI 2 "x86_64_general_operand" "")))]
-  "TARGET_64BIT"
-  "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
+(define_expand "xor<mode>3"
+  [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
+	(xor:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
+		  (match_operand:SWIM 2 "<general_operand>" "")))]
+  ""
+  "ix86_expand_binary_operator (XOR, <MODE>mode, operands); DONE;")
 
-(define_insn "*xordi_1_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
-	(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
+(define_insn "*xor<mode>_1"
+  [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
+	(xor:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
+		    (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && ix86_binary_operator_ok (XOR, DImode, operands)"
-  "xor{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-(define_insn "*xordi_2_rex64"
-  [(set (reg FLAGS_REG)
-	(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
-		 (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
-	(xor:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT
-   && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (XOR, DImode, operands)"
-  "xor{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-(define_insn "*xordi_3_rex64"
-  [(set (reg FLAGS_REG)
-	(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
-			 (match_operand:DI 2 "x86_64_general_operand" "rem"))
-		 (const_int 0)))
-   (clobber (match_scratch:DI 0 "=r"))]
-  "TARGET_64BIT
-   && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (XOR, DImode, operands)"
-  "xor{q}\t{%2, %0|%0, %2}"
+  "ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
+  "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "DI")])
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*xorsi_1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,rm")))
+;; %%% Potential partial reg stall on alternative 2.  What to do?
+(define_insn "*xorqi_1"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
+	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+		(match_operand:QI 2 "general_operand" "qmn,qn,rn")))
    (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (XOR, SImode, operands)"
-  "xor{l}\t{%2, %0|%0, %2}"
+  "ix86_binary_operator_ok (XOR, QImode, operands)"
+  "@
+   xor{b}\t{%2, %0|%0, %2}
+   xor{b}\t{%2, %0|%0, %2}
+   xor{l}\t{%k2, %k0|%k0, %k2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "QI,QI,SI")])
 
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 ;; Add speccase for immediates
@@ -9384,18 +9172,30 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
-(define_insn "*xorsi_2"
+(define_insn "*xorqi_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
+	(xor:QI (match_dup 0)
+		(match_operand:QI 1 "general_operand" "qn,qmn")))
+   (clobber (reg:CC FLAGS_REG))]
+  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "xor{b}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "QI")])
+
+(define_insn "*xor<mode>_2"
   [(set (reg FLAGS_REG)
-	(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:SI 2 "general_operand" "g,ri"))
+	(compare (xor:SWI
+		  (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
+		  (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
 		 (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
-	(xor:SI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+	(xor:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (XOR, SImode, operands)"
-  "xor{l}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
+  "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "<MODE>")])
 
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 ;; ??? Special case for immediate operand is missing - it is tricky.
@@ -9425,91 +9225,32 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
-(define_insn "*xorsi_3"
-  [(set (reg FLAGS_REG)
-	(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-			 (match_operand:SI 2 "general_operand" "g"))
-		 (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r"))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "xor{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-(define_expand "xorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-	(xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
-		(match_operand:HI 2 "general_operand" "")))]
-  "TARGET_HIMODE_MATH"
-  "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
-
-(define_insn "*xorhi_1"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
-	(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "rmn,rn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (XOR, HImode, operands)"
-  "xor{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_insn "*xorhi_2"
+(define_insn "*xorqi_2_slp"
   [(set (reg FLAGS_REG)
-	(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			 (match_operand:HI 2 "general_operand" "rmn,rn"))
+	(compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
+			 (match_operand:QI 1 "general_operand" "qmn,qn"))
 		 (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
-	(xor:HI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (XOR, HImode, operands)"
-  "xor{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
+   (set (strict_low_part (match_dup 0))
+	(xor:QI (match_dup 0) (match_dup 1)))]
+  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+   && ix86_match_ccmode (insn, CCNOmode)
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "xor{b}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "QI")])
 
-(define_insn "*xorhi_3"
+(define_insn "*xor<mode>_3"
   [(set (reg FLAGS_REG)
-	(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
-			 (match_operand:HI 2 "general_operand" "rmn"))
+	(compare (xor:SWI
+		  (match_operand:SWI 1 "nonimmediate_operand" "%0")
+		  (match_operand:SWI 2 "<general_operand>" "<g>"))
 		 (const_int 0)))
-   (clobber (match_scratch:HI 0 "=r"))]
+   (clobber (match_scratch:SWI 0 "=<r>"))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "xor{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "HI")])
-
-(define_expand "xorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
-		(match_operand:QI 2 "general_operand" "")))]
-  "TARGET_QIMODE_MATH"
-  "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
-
-;; %%% Potential partial reg stall on alternative 2.  What to do?
-(define_insn "*xorqi_1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
-	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
-		(match_operand:QI 2 "general_operand" "qmn,qn,rn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (XOR, QImode, operands)"
-  "@
-   xor{b}\t{%2, %0|%0, %2}
-   xor{b}\t{%2, %0|%0, %2}
-   xor{l}\t{%k2, %k0|%k0, %k2}"
+   && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
+  "xor{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
-   (set_attr "mode" "QI,QI,SI")])
-
-(define_insn "*xorqi_1_slp"
-  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
-	(xor:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "qn,qmn")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "xor{b}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "mode" "QI")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*xorqi_ext_0"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
@@ -9522,14 +9263,14 @@
 	    (const_int 8))
 	  (match_operand 2 "const_int_operand" "n")))
    (clobber (reg:CC FLAGS_REG))]
-  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
+  "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
-(define_insn "*xorqi_ext_1"
+(define_insn "*xorqi_ext_1_rex64"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -9539,16 +9280,16 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand:QI 2 "general_operand" "Qm"))))
+	    (match_operand 2 "ext_register_operand" "Q"))))
    (clobber (reg:CC FLAGS_REG))]
-  "!TARGET_64BIT
+  "TARGET_64BIT
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
    (set_attr "mode" "QI")])
 
-(define_insn "*xorqi_ext_1_rex64"
+(define_insn "*xorqi_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
@@ -9558,9 +9299,9 @@
 	    (const_int 8)
 	    (const_int 8))
 	  (zero_extend:SI
-	    (match_operand 2 "ext_register_operand" "Q"))))
+	    (match_operand:QI 2 "general_operand" "Qm"))))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
+  "!TARGET_64BIT
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
@@ -9579,54 +9320,36 @@
 	  		   (const_int 8)
 			   (const_int 8))))
    (clobber (reg:CC FLAGS_REG))]
-  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
+  "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "xor{b}\t{%h2, %h0|%h0, %h2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "0")
    (set_attr "mode" "QI")])
 
-(define_insn "*xorqi_cc_1"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		  (match_operand:QI 2 "general_operand" "qmn,qn"))
-	  (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
-	(xor:QI (match_dup 1) (match_dup 2)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (XOR, QImode, operands)"
-  "xor{b}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
-
-(define_insn "*xorqi_2_slp"
-  [(set (reg FLAGS_REG)
-	(compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
-			 (match_operand:QI 1 "general_operand" "qmn,qn"))
-		 (const_int 0)))
-   (set (strict_low_part (match_dup 0))
-	(xor:QI (match_dup 0) (match_dup 1)))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "xor{b}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "mode" "QI")])
-
-(define_insn "*xorqi_cc_2"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
-		  (match_operand:QI 2 "general_operand" "qmn"))
-	  (const_int 0)))
-   (clobber (match_scratch:QI 0 "=q"))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "xor{b}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
+(define_expand "xorqi_cc_ext_1"
+  [(parallel [
+     (set (reg:CCNO FLAGS_REG)
+	  (compare:CCNO
+	    (xor:SI
+	      (zero_extract:SI
+		(match_operand 1 "ext_register_operand" "")
+		(const_int 8)
+		(const_int 8))
+	      (match_operand:QI 2 "general_operand" ""))
+	    (const_int 0)))
+     (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
+			   (const_int 8)
+			   (const_int 8))
+	  (xor:SI
+	    (zero_extract:SI
+	     (match_dup 1)
+	     (const_int 8)
+	     (const_int 8))
+	    (match_dup 2)))])]
+  ""
+  "")
 
-(define_insn "*xorqi_cc_ext_1"
+(define_insn "*xorqi_cc_ext_1_rex64"
   [(set (reg FLAGS_REG)
 	(compare
 	  (xor:SI
@@ -9634,21 +9357,24 @@
 	      (match_operand 1 "ext_register_operand" "0")
 	      (const_int 8)
 	      (const_int 8))
-	    (match_operand:QI 2 "general_operand" "qmn"))
+	    (match_operand:QI 2 "nonmemory_operand" "Qn"))
 	  (const_int 0)))
-   (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
+   (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
 	(xor:SI
-	  (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
+	  (zero_extract:SI
+	   (match_dup 1)
+	   (const_int 8)
+	   (const_int 8))
 	  (match_dup 2)))]
-  "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
-(define_insn "*xorqi_cc_ext_1_rex64"
+(define_insn "*xorqi_cc_ext_1"
   [(set (reg FLAGS_REG)
 	(compare
 	  (xor:SI
@@ -9656,40 +9382,23 @@
 	      (match_operand 1 "ext_register_operand" "0")
 	      (const_int 8)
 	      (const_int 8))
-	    (match_operand:QI 2 "nonmemory_operand" "Qn"))
+	    (match_operand:QI 2 "general_operand" "qmn"))
 	  (const_int 0)))
-   (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
+   (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
 			 (const_int 8)
 			 (const_int 8))
 	(xor:SI
-	  (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
+	  (zero_extract:SI
+	   (match_dup 1)
+	   (const_int 8)
+	   (const_int 8))
 	  (match_dup 2)))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
+  "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
-(define_expand "xorqi_cc_ext_1"
-  [(parallel [
-     (set (reg:CCNO FLAGS_REG)
-	  (compare:CCNO
-	    (xor:SI
-	      (zero_extract:SI
-		(match_operand 1 "ext_register_operand" "")
-		(const_int 8)
-		(const_int 8))
-	      (match_operand:QI 2 "general_operand" ""))
-	    (const_int 0)))
-     (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
-			   (const_int 8)
-			   (const_int 8))
-	  (xor:SI
-	    (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
-	    (match_dup 2)))])]
-  ""
-  "")
-
 (define_split
   [(set (match_operand 0 "register_operand" "")
 	(xor (match_operand 1 "register_operand" "")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index dd47b7d1dc5..0afdd1197f6 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -244,6 +244,12 @@ mcld
 Target Report Mask(CLD) Save
 Generate cld instruction in the function prologue.
 
+mfused-madd
+Target Report Mask(FUSED_MADD) Save
+Enable automatic generation of fused floating point multiply-add instructions
+if the ISA supports such instructions.  The -mfused-madd option is on by
+default.
+
 ;; ISA support
 
 m32
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 78e4b6af1d8..9524d4f7957 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1709,7 +1709,8 @@
 	  (match_operand:FMA4MODEF4 1 "register_operand" "%x,x")
 	  (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1741,7 +1742,8 @@
 	  (match_operand:FMA4MODEF4 1 "register_operand" "%x,x")
 	  (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1775,7 +1777,8 @@
 	 (mult:FMA4MODEF4
 	  (match_operand:FMA4MODEF4 1 "register_operand" "%x,x")
 	  (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1809,7 +1812,8 @@
 	   (match_operand:FMA4MODEF4 1 "register_operand" "%x,x"))
 	  (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1843,7 +1847,8 @@
 	  (match_operand:SSEMODEF4 1 "register_operand" "%x,x")
 	  (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1879,7 +1884,8 @@
 	  (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
 	 (match_dup 0)
 	 (const_int 1)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1893,7 +1899,8 @@
 	  (match_operand:SSEMODEF4 1 "register_operand" "%x,x")
 	  (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1929,7 +1936,8 @@
 	  (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
 	 (match_dup 0)
 	 (const_int 1)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1945,7 +1953,8 @@
 	 (mult:SSEMODEF4
 	  (match_operand:SSEMODEF4 1 "register_operand" "%x,x")
 	  (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,m"))))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1981,7 +1990,8 @@
 	   (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,m")))
 	 (match_dup 0)
 	 (const_int 1)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -1997,7 +2007,8 @@
 	   (match_operand:SSEMODEF4 1 "register_operand" "%x,x"))
 	  (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,m"))
 	 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x")))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2037,7 +2048,8 @@
 	  (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
 	 (match_dup 0)
 	 (const_int 1)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2053,7 +2065,8 @@
 	    (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2067,7 +2080,8 @@
 	    (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2081,7 +2095,8 @@
 	    (match_operand:FMA4MODEF4 1 "register_operand" "%x,x")
 	    (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m")))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2096,7 +2111,8 @@
 	    (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2111,7 +2127,8 @@
 	    (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2125,7 +2142,8 @@
 	    (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2139,7 +2157,8 @@
 	    (match_operand:SSEMODEF2P 1 "register_operand" "%x,x")
 	    (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,m")))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2154,7 +2173,8 @@
 	    (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,m"))
 	   (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<MODE>")])
@@ -2173,7 +2193,8 @@
 	   (match_dup 0)
 	   (const_int 1))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<ssescalarmode>")])
@@ -2190,7 +2211,8 @@
 	   (match_dup 0)
 	   (const_int 1))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<ssescalarmode>")])
@@ -2207,7 +2229,8 @@
 	   (match_dup 0)
 	   (const_int 1))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<ssescalarmode>")])
@@ -2225,7 +2248,8 @@
 	   (match_dup 0)
 	   (const_int 1))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "<ssescalarmode>")])
@@ -2250,7 +2274,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 170)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V8SF")])
@@ -2269,7 +2294,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 10)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4DF")])
@@ -2288,7 +2314,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 10)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
@@ -2307,7 +2334,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 2)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V2DF")])
@@ -2326,7 +2354,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 85)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V8SF")])
@@ -2345,7 +2374,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 5)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4DF")])
@@ -2364,7 +2394,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 5)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
@@ -2383,7 +2414,8 @@
 	      (match_dup 2))
 	    (match_dup 3))
 	  (const_int 1)))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V2DF")])
@@ -2406,7 +2438,8 @@
 	     (match_dup 3))
 	   (const_int 170))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V8SF")])
@@ -2427,7 +2460,8 @@
 	     (match_dup 3))
 	   (const_int 10))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4DF")])
@@ -2448,7 +2482,8 @@
 	     (match_dup 3))
 	   (const_int 10))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
@@ -2469,7 +2504,8 @@
 	     (match_dup 3))
 	   (const_int 2))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V2DF")])
@@ -2490,7 +2526,8 @@
 	     (match_dup 3))
 	   (const_int 85))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V8SF")])
@@ -2511,7 +2548,8 @@
 	     (match_dup 3))
 	   (const_int 5))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4DF")])
@@ -2532,7 +2570,8 @@
 	     (match_dup 3))
 	   (const_int 5))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
@@ -2553,7 +2592,8 @@
 	     (match_dup 3))
 	   (const_int 1))]
 	 UNSPEC_FMA4_INTRINSIC))]
-  "TARGET_FMA4 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+  "TARGET_FMA4 && TARGET_FUSED_MADD
+   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V2DF")])
diff --git a/gcc/config/pa/hpux-unwind.h b/gcc/config/pa/hpux-unwind.h
index cfce90be6ba..92061ec3677 100644
--- a/gcc/config/pa/hpux-unwind.h
+++ b/gcc/config/pa/hpux-unwind.h
@@ -351,6 +351,7 @@ pa_fallback_frame_state (struct _Unwind_Context *context,
 
       fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
       UPDATE_FS_FOR_PC (fs, DWARF_ALT_FRAME_RETURN_COLUMN);
+      fs->signal_frame = 1;
 
       return _URC_NO_REASON;
     }
diff --git a/gcc/config/pa/linux-unwind.h b/gcc/config/pa/linux-unwind.h
index 733f772c1c7..a0560e97445 100644
--- a/gcc/config/pa/linux-unwind.h
+++ b/gcc/config/pa/linux-unwind.h
@@ -135,6 +135,7 @@ pa32_fallback_frame_state (struct _Unwind_Context *context,
   fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset
     = (long) &sc->sc_iaoq[0] - new_cfa;
   fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
+  fs->signal_frame = 1;
   return _URC_NO_REASON;
 }
 #endif /* inhibit_libc */
diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h
index df36ea2e8a9..4fe03f6dd8d 100644
--- a/gcc/config/pa/pa-hpux10.h
+++ b/gcc/config/pa/pa-hpux10.h
@@ -89,6 +89,7 @@ along with GCC; see the file COPYING3.  If not see
    %{!shared:%{pg:-L/lib/libp %{!static:\
      %nWarning: consider linking with `-static' as system libraries with\n\
      %n  profiling support are only provided in archive format}}}\
+   %{!shared:%{!static:%{rdynamic:-E}}}\
    -z %{mlinker-opt:-O} %{!shared:-u main}\
    %{static:-a archive} %{shared:-b}"
 #else
@@ -99,6 +100,7 @@ along with GCC; see the file COPYING3.  If not see
    %{!shared:%{pg:-L/lib/libp %{!static:\
      %nWarning: consider linking with `-static' as system libraries with\n\
      %n  profiling support are only provided in archive format}}}\
+   %{!shared:%{!static:%{rdynamic:-E}}}\
    -z %{mlinker-opt:-O} %{!shared:-u main}\
    %{static:-a archive} %{shared:-b}"
 #endif
diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h
index 09b414cb00a..540a93da524 100644
--- a/gcc/config/pa/pa-hpux11.h
+++ b/gcc/config/pa/pa-hpux11.h
@@ -110,6 +110,7 @@ along with GCC; see the file COPYING3.  If not see
    %{!shared:%{pg:-L/lib/libp -L/usr/lib/libp %{!static:\
      %nWarning: consider linking with `-static' as system libraries with\n\
      %n  profiling support are only provided in archive format}}}\
+   %{!shared:%{!static:%{rdynamic:-E}}}\
    -z %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\
    %{static:-a archive} %{shared:-b}"
 
diff --git a/gcc/config/pa/pa64-hpux.h b/gcc/config/pa/pa64-hpux.h
index 16f5a3e4b09..35ea51ce5f4 100644
--- a/gcc/config/pa/pa64-hpux.h
+++ b/gcc/config/pa/pa64-hpux.h
@@ -32,7 +32,8 @@ along with GCC; see the file COPYING3.  If not see
    %{!shared:%{pg:-L/lib/pa20_64/libp -L/usr/lib/pa20_64/libp %{!static:\
      %nWarning: consider linking with `-static' as system libraries with\n\
      %n  profiling support are only provided in archive format}}}\
-   %{mhp-ld:+Accept TypeMismatch -z} -E %{mlinker-opt:-O}\
+   %{!shared:%{!static:%{rdynamic:-E}}}\
+   %{mhp-ld:+Accept TypeMismatch -z} %{mlinker-opt:-O}\
    %{!shared:-u main %{!nostdlib:%{!nodefaultlibs:-u __cxa_finalize}}}\
    %{static:-a archive} %{shared:%{mhp-ld:-b}%{!mhp-ld:-shared}}"
 #else
@@ -43,7 +44,8 @@ along with GCC; see the file COPYING3.  If not see
    %{!shared:%{pg:-L/lib/pa20_64/libp -L/usr/lib/pa20_64/libp %{!static:\
      %nWarning: consider linking with `-static' as system libraries with\n\
      %n  profiling support are only provided in archive format}}}\
-   %{!mgnu-ld:+Accept TypeMismatch -z} -E %{mlinker-opt:-O}\
+   %{!shared:%{!static:%{rdynamic:-E}}}\
+   %{!mgnu-ld:+Accept TypeMismatch -z} %{mlinker-opt:-O}\
    %{!shared:-u main %{!nostdlib:%{!nodefaultlibs:-u __cxa_finalize}}}\
    %{static:-a archive} %{shared:%{mgnu-ld:-shared}%{!mgnu-ld:-b}}"
 #endif