Merge in gcc2-ss-010999

From-SVN: r29150

3 files changed, 36 insertions, 36 deletions

diff --git a/gcc/config/we32k/we32k.c b/gcc/config/we32k/we32k.c
index e1b58f9f477..ef03232cb5d 100644
--- a/gcc/config/we32k/we32k.c
+++ b/gcc/config/we32k/we32k.c
@@ -1,6 +1,6 @@
 /* Subroutines for insn-output.c for AT&T we32000 Family.
+   Copyright (C) 1991, 1992, 1997, 1998, 1999 Free Software Foundation, Inc.
    Contributed by John Wehle (john@feith1.uucp)
-   Copyright (C) 1991, 1992, 1997 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -21,12 +21,11 @@ Boston, MA 02111-1307, USA.  */
 
 
 #include "config.h"
-#include <stdio.h>
+#include "system.h"
 #include "rtl.h"
 #include "function.h"
 #include "real.h"
 
-
 void
 output_move_double (operands)
      rtx *operands;
@@ -37,7 +36,7 @@ output_move_double (operands)
 
   if (GET_CODE (operands[0]) == REG) 
     {
-      lsw_operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
       msw_dreg = operands[0];
     }
   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
@@ -47,7 +46,7 @@ output_move_double (operands)
 
   if (GET_CODE (operands[1]) == REG) 
     {
-      lsw_operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+      lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
       lsw_sreg = lsw_operands[1];
     }
   else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) 
@@ -116,12 +115,12 @@ output_push_double (operands)
   rtx lsw_operands[1];
 
   if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+    lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
     lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
   else if (GET_CODE (operands[0]) == CONST_DOUBLE)
     {
-      lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
+      lsw_operands[0] = GEN_INT CONST_DOUBLE_HIGH (operands[0]));
       operands[0] = GEN_INT (CONST_DOUBLE_LOW (operands[0]));
     }
   else if (GET_CODE (operands[0]) == CONST_INT)
diff --git a/gcc/config/we32k/we32k.h b/gcc/config/we32k/we32k.h
index af7c7ff774d..7a66c734083 100644
--- a/gcc/config/we32k/we32k.h
+++ b/gcc/config/we32k/we32k.h
@@ -1,5 +1,6 @@
 /* Definitions of target machine for GNU compiler.  AT&T we32000 version.
-   Copyright (C) 1991, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
+   Copyright (C) 1991, 92, 93, 94, 95, 96, 98, 1999
+   Free Software Foundation, Inc.
    Contributed by John Wehle (john@feith1.uucp)
 
 This file is part of GNU CC.
@@ -319,14 +320,14 @@ enum reg_class { NO_REGS, GENERAL_REGS,
 /* On the we32000 the return value is in r0 regardless.  */
 
 #define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
+  gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
 
 /* Define how to find the value returned by a library function
    assuming the value has mode MODE.  */
 
 /* On the we32000 the return value is in r0 regardless.  */
 
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
+#define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, 0)
 
 /* 1 if N is a possible register number for a function value.
    On the we32000, r0 is the only register thus used.  */
@@ -478,15 +479,15 @@ enum reg_class { NO_REGS, GENERAL_REGS,
      mov #STATIC,%r8
      jmp #FUNCTION */
 
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x844f));				\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_CHAR (FILE, GEN_INT (0x48));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x247f));				\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
+#define TRAMPOLINE_TEMPLATE(FILE)		\
+{						\
+  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x844f));	\
+  ASM_OUTPUT_SHORT (FILE, const0_rtx);		\
+  ASM_OUTPUT_SHORT (FILE, const0_rtx);		\
+  ASM_OUTPUT_CHAR  (FILE, GEN_INT (0x48));	\
+  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x247f));	\
+  ASM_OUTPUT_SHORT (FILE, const0_rtx);		\
+  ASM_OUTPUT_SHORT (FILE, const0_rtx);		\
 }
 
 /* Length in units of the trampoline for entering a nested function.  */
@@ -499,8 +500,8 @@ enum reg_class { NO_REGS, GENERAL_REGS,
 
 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
 {									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 9)), FNADDR); \
+  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
+  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 9)), FNADDR); \
 }
 
 /* Generate calls to memcpy() and memset() rather
diff --git a/gcc/config/we32k/we32k.md b/gcc/config/we32k/we32k.md
index 9d85a1026db..afabb9200cd 100644
--- a/gcc/config/we32k/we32k.md
+++ b/gcc/config/we32k/we32k.md
@@ -1,5 +1,5 @@
 ;; Machine description for GNU compiler, AT&T we32000 Version
-;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1991, 1992, 1994, 1998, 1999 Free Software Foundation, Inc.
 ;; Contributed by John Wehle (john@feith1.uucp)
 
 ;; This file is part of GNU CC.
@@ -125,7 +125,7 @@
   rtx lsw_operands[3];
 
   if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+    lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
@@ -133,7 +133,7 @@
       abort();
 
   if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+    lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
   else
     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
@@ -175,7 +175,7 @@
   rtx lsw_operands[3];
 
   if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+    lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
@@ -183,7 +183,7 @@
       abort();
 
   if (GET_CODE (operands[1]) == REG)
-    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
+    lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
   else
     if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
       lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
@@ -203,7 +203,7 @@
           abort();
 
   if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+    lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
   else
     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
@@ -289,7 +289,7 @@
   rtx lsw_operands[3];
 
   if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+    lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
@@ -297,7 +297,7 @@
       abort();
 
   if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+    lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
   else
     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
@@ -339,7 +339,7 @@
   rtx lsw_operands[3];
 
   if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+    lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
@@ -347,7 +347,7 @@
       abort();
 
   if (GET_CODE (operands[1]) == REG)
-    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
+    lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
   else
     if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
       lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
@@ -367,7 +367,7 @@
           abort();
 
   if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+    lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
   else
     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
@@ -758,7 +758,7 @@
 
   if (GET_CODE (operands[1]) == CONST_INT &&
     ((unsigned long)INTVAL (operands[1]) & 0x8000L))
-    operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffff0000L);
+    operands[1] = GEN_INT (INTVAL (operands[1]) | 0xffff0000L);
 
   output_asm_insn(\"CMPH %1, %0\",operands);
 
@@ -913,7 +913,7 @@
   "*
   {
 
-  operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
   output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
 
   return \"\";
@@ -928,7 +928,7 @@
   "*
   {
 
-  operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
   output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
 
   return \"\";
@@ -943,7 +943,7 @@
   "*
   {
 
-  operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
+  operands[1] = GEN_INT (INTVAL (operands[1]) - 1);
   output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
 
   return \"\";