PR target/59316

	* config/sparc/sparc.h (SPARC_LOW_FE_EXCEPT_VALUES): Define.
	* config/sparc/sol2.h (SPARC_LOW_FE_EXCEPT_VALUES): Redefine.
	* config/sparc/sparc.c (TARGET_INIT_BUILTINS): Move around.
	(TARGET_BUILTIN_DECL): Define.
	(TARGET_ATOMIC_ASSIGN_EXPAND_FENV): Likewise.
	(sparc32_initialize_trampoline): Adjust call to gen_flush.
	(enum sparc_builtins): New enumeral type.
	(sparc_builtins): New static array.
	(sparc_builtins_icode): Likewise.
	(def_builtin): Accept a separate icode and save the result.
	(def_builtin_const): Likewise.
	(sparc_fpu_init_builtins): New function.
	(sparc_vis_init_builtins): Pass the builtin code.
	(sparc_init_builtins): Call it if TARGET_FPU.
	(sparc_builtin_decl): New function.
	(sparc_expand_builtin): Deal with SPARC_BUILTIN_{LD,ST}FSR.
	(sparc_handle_vis_mul8x16): Use the builtin code.
	(sparc_fold_builtin): Likewise.  Deal with SPARC_BUILTIN_{LD,ST}FSR
	and SPARC_BUILTIN_PDISTN.
	(compound_expr): New helper function.
	(sparc_atomic_assign_expand_fenv): New function.
	* config/sparc/sparc.md (unspecv): Reorder values, add UNSPECV_LDFSR
	and UNSPECV_STFSR.
	(flush, flushdi): Merge into single pattern.
	(ldfsr): New instruction.
	(stfsr): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205735 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 26 insertions, 16 deletions

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index be7bbe977a2..b3fb2eb18fb 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -96,13 +96,19 @@
 
 (define_c_enum "unspecv" [
   UNSPECV_BLOCKAGE
+  UNSPECV_PROBE_STACK_RANGE
+
   UNSPECV_FLUSHW
-  UNSPECV_FLUSH
   UNSPECV_SAVEW
-  UNSPECV_CAS
-  UNSPECV_SWAP
+
+  UNSPECV_FLUSH
+
   UNSPECV_LDSTUB
-  UNSPECV_PROBE_STACK_RANGE
+  UNSPECV_SWAP
+  UNSPECV_CAS
+
+  UNSPECV_LDFSR
+  UNSPECV_STFSR
 ])
 
 (define_constants
@@ -6783,22 +6789,26 @@
 
 ;; Special pattern for the FLUSH instruction.
 
-; We do SImode and DImode versions of this to quiet down genrecog's complaints
-; of the define_insn otherwise missing a mode.  We make "flush", aka
-; gen_flush, the default one since sparc_initialize_trampoline uses
-; it on SImode mem values.
-
-(define_insn "flush"
-  [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
+(define_insn "flush<P:mode>"
+  [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
   ""
   { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
   [(set_attr "type" "iflush")])
 
-(define_insn "flushdi"
-  [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
-  ""
-  { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
-  [(set_attr "type" "iflush")])
+;; Special insns to load and store the 32-bit FP Status Register.
+
+(define_insn "ldfsr"
+  [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_LDFSR)]
+  "TARGET_FPU"
+  "ld\t%0, %%fsr"
+  [(set_attr "type" "load")])
+
+(define_insn "stfsr"
+  [(set (match_operand:SI 0 "memory_operand" "=m")
+        (unspec_volatile:SI [(const_int 0)] UNSPECV_STFSR))]
+  "TARGET_FPU"
+  "st\t%%fsr, %0"
+  [(set_attr "type" "store")])
 
 
 ;; Find first set instructions.