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author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-07-01 22:22:57 +0000 |
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committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-07-01 22:22:57 +0000 |
commit | 9e169c4bf36a38689550c059570c57efbf00a6fb (patch) | |
tree | 95e6800f7ac2a49ff7f799d96f04172320e70ac0 /gcc/config/rs6000/vsx.md | |
parent | 6170dfb6edfb7b19f8ae5209b8f948fe0076a4ad (diff) | |
download | gcc-vect256.tar.gz |
Merged trunk at revision 161680 into branch.vect256
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/vect256@161681 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/vsx.md')
-rw-r--r-- | gcc/config/rs6000/vsx.md | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7d572a48412..213d53ae5d1 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -195,7 +195,7 @@ (UNSPEC_VSX_MSUB 511) (UNSPEC_VSX_NMADD 512) (UNSPEC_VSX_NMSUB 513) - (UNSPEC_VSX_RSQRTE 514) + ;; 514 deleted (UNSPEC_VSX_TDIV 515) (UNSPEC_VSX_TSQRT 516) (UNSPEC_VSX_XXPERMDI 517) @@ -446,10 +446,10 @@ [(set_attr "type" "<VStype_sqrt>") (set_attr "fp_type" "<VSfptype_sqrt>")]) -(define_insn "vsx_rsqrte<mode>2" +(define_insn "*vsx_rsqrte<mode>2" [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] - UNSPEC_VSX_RSQRTE))] + UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>rsqrte<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") @@ -862,6 +862,20 @@ [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) +;; Special version of copysign for single precision that knows internally +;; scalar single values are kept as double +(define_insn "vsx_copysignsf3" + [(set (match_operand:SF 0 "vsx_register_operand" "=f") + (if_then_else:SF + (ge:SF (match_operand:SF 2 "vsx_register_operand" "f") + (match_operand:SF 3 "zero_constant" "j")) + (abs:SF (match_operand:SF 1 "vsx_register_operand" "f")) + (neg:SF (abs:SF (match_dup 1)))))] + "VECTOR_UNIT_VSX_P (DFmode)" + "xscpsgndp %x0,%x2,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_d")]) + ;; For the conversions, limit the register class for the integer value to be ;; the fprs because we don't want to add the altivec registers to movdi/movsi. ;; For the unsigned tests, there isn't a generic double -> unsigned conversion |