diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-05-17 05:56:15 +0000 |
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| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-05-17 05:56:15 +0000 |
| commit | f259ef2dde37cdc1994ab89de4202de11db1758d (patch) | |
| tree | fa16d409fa166f36caaced4b9b18b5c11655a10f /gcc/config/rs6000/altivec.md | |
| parent | f901aa342fec3c1daf7be7c1f6258571542389b1 (diff) | |
| download | gcc-f259ef2dde37cdc1994ab89de4202de11db1758d.tar.gz | |
2008-05-17 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk r135459
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@135460 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 95c588ca070..f8ed145350e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -575,7 +575,7 @@ /* Generate [-0.0, -0.0, -0.0, -0.0]. */ neg0 = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx)); - emit_insn (gen_ashlv4si3 (neg0, neg0, neg0)); + emit_insn (gen_vashlv4si3 (neg0, neg0, neg0)); /* Use the multiply-add. */ emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2], @@ -634,7 +634,7 @@ high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); - emit_insn (gen_ashlv4si3 (high_product, high_product, sixteen)); + emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen)); emit_insn (gen_addv4si3 (operands[0], high_product, low_product)); @@ -1238,7 +1238,7 @@ "vslo %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "ashl<mode>3" +(define_insn "vashl<mode>3" [(set (match_operand:VI 0 "register_operand" "=v") (ashift:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v") ))] @@ -1246,7 +1246,7 @@ "vsl<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "lshr<mode>3" +(define_insn "vlshr<mode>3" [(set (match_operand:VI 0 "register_operand" "=v") (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v") ))] @@ -1254,7 +1254,7 @@ "vsr<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "ashr<mode>3" +(define_insn "vashr<mode>3" [(set (match_operand:VI 0 "register_operand" "=v") (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v") ))] @@ -2640,7 +2640,7 @@ /* Generate [-0.0, -0.0, -0.0, -0.0]. */ neg0 = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx)); - emit_insn (gen_ashlv4si3 (neg0, neg0, neg0)); + emit_insn (gen_vashlv4si3 (neg0, neg0, neg0)); /* XOR */ emit_insn (gen_xorv4sf3 (operands[0], |