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| author | mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-01-19 16:05:59 +0000 |
|---|---|---|
| committer | mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-01-19 16:05:59 +0000 |
| commit | fccc4b5408942b92bc00bc053f4da9af2109557c (patch) | |
| tree | ae0716bdf6bac1b9b8b9cef9772bca16a85af21c /gcc/config/mips | |
| parent | 6d0c5d85097829ed871a2cfb0a5ee004b9cc13a6 (diff) | |
| download | gcc-fccc4b5408942b92bc00bc053f4da9af2109557c.tar.gz | |
MIPS: PR target/78176 add -mlxc1-sxc1.
gcc/
PR target/78176
* config.gcc (supported_defaults): Add lxc1-sxc1.
(with_lxc1_sxc1): Add validation.
(all_defaults): Add lxc1-sxc1.
* config/mips/mips.opt (mlxc1-sxc1): New option.
* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
mlxc1-sxc1.
(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
__mips_no_lxc1_sxc1.
(ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1.
* gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option.
* doc/install.texi (--with-lxc1-sxc1): Document the new option.
gcc/testsuite/
* gcc.target/mips/lxc1-sxc1-1.c: New file.
* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
HAS_LXC1.
(mips_option_groups): Add -m[no-]lxc1-sxc1.
(mips-dg-init): Detect default -mno-lxc1-sxc1.
(mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244640 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips')
| -rw-r--r-- | gcc/config/mips/mips.h | 8 | ||||
| -rw-r--r-- | gcc/config/mips/mips.opt | 4 |
2 files changed, 10 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index fbd7011512e..4205589af45 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -637,6 +637,8 @@ struct mips_cpu_info { \ if (TARGET_CACHE_BUILTIN) \ builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ + if (!ISA_HAS_LXC1_SXC1) \ + builtin_define ("__mips_no_lxc1_sxc1"); \ } \ while (0) @@ -866,7 +868,8 @@ struct mips_cpu_info { {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ - {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } + {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ + {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \ /* A spec that infers the: -mnan=2008 setting from a -mips argument, @@ -1036,7 +1039,8 @@ struct mips_cpu_info { /* ISA has floating-point indexed load and store instructions (LWXC1, LDXC1, SWXC1 and SDXC1). */ -#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 +#define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ + && mips_lxc1_sxc1) /* ISA has paired-single instructions. */ #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 2559649ffc5..75ebafdba26 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -388,6 +388,10 @@ mlra Target Report Var(mips_lra_flag) Init(1) Save Use LRA instead of reload. +mlxc1-sxc1 +Target Report Var(mips_lxc1_sxc1) Init(1) +Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable. + mtune= Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value) -mtune=PROCESSOR Optimize the output for PROCESSOR. |