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| author | nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-07-03 16:56:20 +0000 |
|---|---|---|
| committer | nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-07-03 16:56:20 +0000 |
| commit | bd9c476483e53c73baa1bbdedbf4a5c07c9b37f4 (patch) | |
| tree | 9e67e8dd0a06a422c7fc60ee07ff0ba61eeffe22 /gcc/config/m32r/m32r.c | |
| parent | f66be06b01f231e3309cb6a7fb3b88bd3a6aad00 (diff) | |
| download | gcc-bd9c476483e53c73baa1bbdedbf4a5c07c9b37f4.tar.gz | |
* config/m32r/constraints.md: New file.
* config/m32r/m32r.c: Include tm-constrs.h.
(small_data_operand): Use satisfies_constraint_* instead of macro.
(addr24_operand, gen_compare): Likewise.
* config/m32r/m32r.h (REG_CLASS_FROM_LETTER): Remove.
(INT8_P, UPPER16_P, UINT32_P, UINT5_P, INVERTED_SIGNED_8BIT,
CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Likewise.
* config/m32r/m32r.md: Include constraints.md.
(movsi_insn): Use satisfies_constraint_* instead of macro.
(andsi3, iorsi3, xorsi3, seq_insn+1, sne): Likewise.
* config/m32r/predicates.md (conditional_move_operand): Likewise.
(two_insn_const_operand, int8_operand, uint16_operand,
reg_or_int16_operand, reg_or_uint16_operand,
reg_or_cmp_int16_operand, cmp_int16_operand,
seth_add3_operand): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@126265 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/m32r/m32r.c')
| -rw-r--r-- | gcc/config/m32r/m32r.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index fa0a6ad9eb0..6758d1a579d 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -42,6 +42,7 @@ #include "tm_p.h" #include "target.h" #include "target-def.h" +#include "tm-constrs.h" /* Save the operands last given to a compare for use when we generate a scc or bcc insn. */ @@ -508,8 +509,7 @@ small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1)))) + && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0)); return 0; @@ -533,8 +533,7 @@ addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) else if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1)))) + && satisfies_constraint_M (XEXP (XEXP (op, 0), 1))) sym = XEXP (XEXP (op, 0), 0); else return 0; @@ -691,8 +690,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) switch (compare_code) { case EQ: - if (GET_CODE (y) == CONST_INT - && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */ + if (satisfies_constraint_P (y) /* Reg equal to small const. */ && y != const0_rtx) { rtx tmp = gen_reg_rtx (SImode); @@ -718,7 +716,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) case LT: if (register_operand (y, SImode) - || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y)))) + || satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */ @@ -758,7 +756,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) case LTU: if (register_operand (y, SImode) - || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y)))) + || satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */ @@ -814,8 +812,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) /* Reg/smallconst equal comparison. */ if (compare_code == EQ - && GET_CODE (y) == CONST_INT - && CMP_INT16_P (INTVAL (y))) + && satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); |