PR target/35714

	* config/i386/mmx.md (mmx_subv2sf3): New expander.
	(*mmx_subv2sf3): Rename from mmx_subv2sf3 insn pattern.
	(*mmx_eqv2sf3): Rename from mmx_eqv2sf3 insn pattern.
	(mmx_eqv2sf3): New expander.  Use ix86_fixup_binary_operands_no_copy
	to handle nonimmediate operands.
	(*mmx_paddwd): Rename from mmx_paddwd insn pattern.
	(mmx_paddwd): New expander.  Use ix86_fixup_binary_operands_no_copy
	to handle nonimmediate operands.
	(*mmx_pmulhrwv4hi3): Rename from mmx_pmulhrwv4hi3 insn pattern.
	(mmx_pmulhrwv4hi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_umulv1siv1di3): Rename from sse2_umulv1siv1di3 insn pattern.
	(sse2_umulv1siv1di3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*mmx_eq<mode>3): Rename from mmx_eq<mode>3 insn pattern.
	(mmx_eq<mode>3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*mmx_uavgv8qi3): Rename from mmx_uavgv8qi3 insn pattern.
	(mmx_uavgv8qi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*mmx_uavgv4hi3): Rename from mmx_uavgv4hi3 insn pattern.
	(mmx_uavgv4hi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.

	* config/i386/sse.md
	(*sse_movhlps): Rename from sse_movhlps insn pattern.
	(sse_movhlps): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse_movlhps): Rename from sse_movlhps insn pattern.
	(sse_movlhps): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse_loadhps): Rename from sse_loadhps insn pattern.
	(sse_loadhps): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse_loadlps): Rename from sse_loadlps insn pattern.
	(sse_loadlps): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse2_unpckhpd): Rename from sse2_unpckhpd insn pattern.
	(sse2_unpckhpd): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_unpcklpd): Rename from sse2_unpcklpd insn pattern.
	(sse2_unpcklpd): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse_loadhpd): Rename from sse_loadhpd insn pattern.
	(sse_loadhpd): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse_loadlpd): Rename from sse_loadlpd insn pattern.
	(sse_loadlpd): New expander.  Use ix86_fixup_binary_operands
	to handle nonimmediate operands.
	(*sse2_<plusminus_insn><mode>3): Rename from
	sse2_<plusminus_insn><mode>3 insn pattern.
	(sse2_<plusminus_insn><mode>3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_umulv2siv2di3): Rename from sse2_umulv2siv2di3 insn pattern.
	(sse2_umulv2siv2di3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse4_1_mulv2siv2di3): Rename from sse4_1_mulv2siv2di3 insn pattern.
	(sse4_1_mulv2siv2di3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_pmaddwd): Rename from sse2_pmaddwd insn pattern.
	(sse2_pmaddwd): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_eq<mode>3): Rename from sse2_eq<mode>3 insn pattern.
	(sse2_eq<mode>3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse4_1_eqv2di3): Rename from sse4_1_eqv2di3 insn pattern.
	(sse4_1_eqv2di3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_uavgv16qi3): Rename from sse2_uavgv16qi3 insn pattern.
	(sse2_uavgv16qi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_uavgv16qi3): Rename from sse2_uavgv16qi3 insn pattern.
	(sse2_uavgv16qi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*sse2_uavgv8hi3): Rename from sse2_uavgv8hi3 insn pattern.
	(sse2_uavgv8hi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*ssse3_pmulhrswv8hi3): Rename from ssse3_pmulhrswv8hi3 insn pattern.
	(ssse3_pmulhrswv8hi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
	(*ssse3_pmulhrswv4hi3): Rename from ssse3_pmulhrswv4hi3 insn pattern.
	(ssse3_pmulhrswv4hi3): New expander.  Use
	ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.

	(<sse>_vm<plusminus_insn><mode>3): Do not use ix86_binary_operator_ok.
	(<sse>_vmmul<mode>3): Ditto.
	(divv4sf3): Do not use ix86_fixup_binary_operands_no_copy.
	(divv2df3): Ditto.
	(ssse3_pmaddubsw128): Use register_operand for operand 1.
	(ssse3_pmaddubsw): Ditto.

	* config/i386/sse.md (ix86_fixup_binary_operands): Assert that src1
	and src2 must have the same mode when swapped.
	(ix86_expand_binop_builtin): Do not use ix86_fixup_binary_operands
	and ix86_binary_operator_ok.  Do not force operands in registers
	when optimizing.

testsuite/ChangeLog:

	PR target/35714
	* gcc.target/i386/pr35714.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@135041 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 131 insertions, 23 deletions

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 2f2c02f75a6..0a507e07a2f 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -229,7 +229,21 @@
   [(set_attr "type" "mmxadd")
    (set_attr "mode" "V2SF")])
 
-(define_insn "mmx_subv2sf3"
+(define_expand "mmx_subv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "")
+        (minus:V2SF (match_operand:V2SF 1 "register_operand" "")
+		    (match_operand:V2SF 2 "nonimmediate_operand" "")))]
+  "TARGET_3DNOW"
+  "")
+
+(define_expand "mmx_subrv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "")
+        (minus:V2SF (match_operand:V2SF 2 "register_operand" "")
+		    (match_operand:V2SF 1 "nonimmediate_operand" "")))]
+  "TARGET_3DNOW"
+  "")
+
+(define_insn "*mmx_subv2sf3"
   [(set (match_operand:V2SF 0 "register_operand" "=y,y")
         (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
 		    (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
@@ -240,13 +254,6 @@
   [(set_attr "type" "mmxadd")
    (set_attr "mode" "V2SF")])
 
-(define_expand "mmx_subrv2sf3"
-  [(set (match_operand:V2SF 0 "register_operand" "")
-        (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "")
-		    (match_operand:V2SF 1 "nonimmediate_operand" "")))]
-  "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "")
-
 (define_expand "mmx_mulv2sf3"
   [(set (match_operand:V2SF 0 "register_operand" "")
 	(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
@@ -403,6 +410,22 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+(define_expand "mmx_eqv2sf3"
+  [(set (match_operand:V2SI 0 "register_operand" "")
+	(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "")
+		 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
+  "TARGET_3DNOW"
+  "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
+
+(define_insn "*mmx_eqv2sf3"
+  [(set (match_operand:V2SI 0 "register_operand" "=y")
+	(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
+		 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
+  "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
+  "pfcmpeq\t{%2, %0|%0, %2}"
+  [(set_attr "type" "mmxcmp")
+   (set_attr "mode" "V2SF")])
+
 (define_insn "mmx_gtv2sf3"
   [(set (match_operand:V2SI 0 "register_operand" "=y")
 	(gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
@@ -421,15 +444,6 @@
   [(set_attr "type" "mmxcmp")
    (set_attr "mode" "V2SF")])
 
-(define_insn "mmx_eqv2sf3"
-  [(set (match_operand:V2SI 0 "register_operand" "=y")
-	(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
-		 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
-  "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
-  "pfcmpeq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxcmp")
-   (set_attr "mode" "V2SF")])
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel single-precision floating point conversion operations
@@ -702,7 +716,29 @@
   [(set_attr "type" "mmxmul")
    (set_attr "mode" "DI")])
 
-(define_insn "mmx_pmaddwd"
+(define_expand "mmx_pmaddwd"
+  [(set (match_operand:V2SI 0 "register_operand" "")
+        (plus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI
+	      (vec_select:V2HI
+		(match_operand:V4HI 1 "nonimmediate_operand" "")
+		(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI
+	      (vec_select:V2HI
+		(match_operand:V4HI 2 "nonimmediate_operand" "")
+		(parallel [(const_int 0) (const_int 2)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI
+	      (vec_select:V2HI (match_dup 1)
+		(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI
+	      (vec_select:V2HI (match_dup 2)
+		(parallel [(const_int 1) (const_int 3)]))))))]
+  "TARGET_MMX"
+  "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
+
+(define_insn "*mmx_pmaddwd"
   [(set (match_operand:V2SI 0 "register_operand" "=y")
         (plus:V2SI
 	  (mult:V2SI
@@ -726,7 +762,23 @@
   [(set_attr "type" "mmxmul")
    (set_attr "mode" "DI")])
 
-(define_insn "mmx_pmulhrwv4hi3"
+(define_expand "mmx_pmulhrwv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "")
+	(truncate:V4HI
+	  (lshiftrt:V4SI
+	    (plus:V4SI
+	      (mult:V4SI
+	        (sign_extend:V4SI
+		  (match_operand:V4HI 1 "nonimmediate_operand" ""))
+	        (sign_extend:V4SI
+		  (match_operand:V4HI 2 "nonimmediate_operand" "")))
+	      (const_vector:V4SI [(const_int 32768) (const_int 32768)
+				  (const_int 32768) (const_int 32768)]))
+	    (const_int 16))))]
+  "TARGET_3DNOW"
+  "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
+
+(define_insn "*mmx_pmulhrwv4hi3"
   [(set (match_operand:V4HI 0 "register_operand" "=y")
 	(truncate:V4HI
 	  (lshiftrt:V4SI
@@ -744,7 +796,21 @@
   [(set_attr "type" "mmxmul")
    (set_attr "mode" "DI")])
 
-(define_insn "sse2_umulv1siv1di3"
+(define_expand "sse2_umulv1siv1di3"
+  [(set (match_operand:V1DI 0 "register_operand" "")
+        (mult:V1DI
+	  (zero_extend:V1DI
+	    (vec_select:V1SI
+	      (match_operand:V2SI 1 "nonimmediate_operand" "")
+	      (parallel [(const_int 0)])))
+	  (zero_extend:V1DI
+	    (vec_select:V1SI
+	      (match_operand:V2SI 2 "nonimmediate_operand" "")
+	      (parallel [(const_int 0)])))))]
+  "TARGET_SSE2"
+  "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
+
+(define_insn "*sse2_umulv1siv1di3"
   [(set (match_operand:V1DI 0 "register_operand" "=y")
         (mult:V1DI
 	  (zero_extend:V1DI
@@ -834,7 +900,15 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "mmx_eq<mode>3"
+(define_expand "mmx_eq<mode>3"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "")
+        (eq:MMXMODEI
+	  (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
+	  (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
+  "TARGET_MMX"
+  "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
+
+(define_insn "*mmx_eq<mode>3"
   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
         (eq:MMXMODEI
 	  (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
@@ -1275,7 +1349,25 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "mmx_uavgv8qi3"
+(define_expand "mmx_uavgv8qi3"
+  [(set (match_operand:V8QI 0 "register_operand" "")
+	(truncate:V8QI
+	  (lshiftrt:V8HI
+	    (plus:V8HI
+	      (plus:V8HI
+		(zero_extend:V8HI
+		  (match_operand:V8QI 1 "nonimmediate_operand" ""))
+		(zero_extend:V8HI
+		  (match_operand:V8QI 2 "nonimmediate_operand" "")))
+	      (const_vector:V8HI [(const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)]))
+	    (const_int 1))))]
+  "TARGET_SSE || TARGET_3DNOW"
+  "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
+
+(define_insn "*mmx_uavgv8qi3"
   [(set (match_operand:V8QI 0 "register_operand" "=y")
 	(truncate:V8QI
 	  (lshiftrt:V8HI
@@ -1303,7 +1395,23 @@
   [(set_attr "type" "mmxshft")
    (set_attr "mode" "DI")])
 
-(define_insn "mmx_uavgv4hi3"
+(define_expand "mmx_uavgv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "")
+	(truncate:V4HI
+	  (lshiftrt:V4SI
+	    (plus:V4SI
+	      (plus:V4SI
+		(zero_extend:V4SI
+		  (match_operand:V4HI 1 "nonimmediate_operand" ""))
+		(zero_extend:V4SI
+		  (match_operand:V4HI 2 "nonimmediate_operand" "")))
+	      (const_vector:V4SI [(const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)]))
+	    (const_int 1))))]
+  "TARGET_SSE || TARGET_3DNOW_A"
+  "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
+
+(define_insn "*mmx_uavgv4hi3"
   [(set (match_operand:V4HI 0 "register_operand" "=y")
 	(truncate:V4HI
 	  (lshiftrt:V4SI