diff options
author | collison <collison@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-04-15 06:13:53 +0000 |
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committer | collison <collison@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-04-15 06:13:53 +0000 |
commit | ffc50d7d8fc6e7abb2f25283784a1eef00e74ff8 (patch) | |
tree | 98e4cb67122b11409710b6871960df793f187fab | |
parent | cbe2ea7cf2ca550ca5c38bc370de54be1fcde76b (diff) | |
download | gcc-ffc50d7d8fc6e7abb2f25283784a1eef00e74ff8.tar.gz |
2015-04-14 Michael Collison <michael.collison@linaro.org>
Backport from trunk r220399, r220413.
2015-02-04 Matthew Wahab <matthew.wahab@arm.com>
* config/aarch64/aarch64-cores.def: Add cortex-a72 and
cortex-a72.cortex-a53.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AArch64 Options/-mtune): Add "cortex-a72".
2015-02-04 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm-cores.def: Add cortex-a72 and
cortex-a72.cortex-a53.
* config/arm/bpabi.h (BE8_LINK_SPEC): Likewise.
* config/arm/t-aprofile (MULTILIB_MATCHES): Likewise.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Add entries for "cortex-a72" and
"cortex-a72.cortex-a53".
* doc/invoke.texi (ARM Options/-mtune): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@222113 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog.linaro | 22 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-cores.def | 2 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-tune.md | 2 | ||||
-rw-r--r-- | gcc/config/arm/arm-cores.def | 2 | ||||
-rw-r--r-- | gcc/config/arm/arm-tables.opt | 6 | ||||
-rw-r--r-- | gcc/config/arm/arm-tune.md | 4 | ||||
-rw-r--r-- | gcc/config/arm/bpabi.h | 4 | ||||
-rw-r--r-- | gcc/config/arm/t-aprofile | 2 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 14 |
9 files changed, 49 insertions, 9 deletions
diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro index 2cc80092c59..3ac887e0ece 100644 --- a/gcc/ChangeLog.linaro +++ b/gcc/ChangeLog.linaro @@ -1,3 +1,25 @@ +2015-04-14 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r220399, r220413. + + 2015-02-04 Matthew Wahab <matthew.wahab@arm.com> + + * config/aarch64/aarch64-cores.def: Add cortex-a72 and + cortex-a72.cortex-a53. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi (AArch64 Options/-mtune): Add "cortex-a72". + + 2015-02-04 Matthew Wahab <matthew.wahab@arm.com> + + * config/arm/arm-cores.def: Add cortex-a72 and + cortex-a72.cortex-a53. + * config/arm/bpabi.h (BE8_LINK_SPEC): Likewise. + * config/arm/t-aprofile (MULTILIB_MATCHES): Likewise. + * config/arm/arm-tune.md: Regenerate. + * config/arm/arm-tables.opt: Add entries for "cortex-a72" and + "cortex-a72.cortex-a53". + * doc/invoke.texi (ARM Options/-mtune): Likewise. + 2015-04-13 Michael Collison <michael.collison@linaro.org> Backport from trunk r219724, 219746, r220103. diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index cfc8f6c5eac..45a30356769 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -36,9 +36,11 @@ AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53) AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57) +AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57) AARCH64_CORE("thunderx", thunderx, thunderx, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx) AARCH64_CORE("xgene1", xgene1, xgene1, 8, AARCH64_FL_FOR_ARCH8, xgene1) /* V8 big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57) +AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 80f59c84ef9..c3305f9935c 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa53,cortexa57,thunderx,xgene1,cortexa57cortexa53" + "cortexa53,cortexa57,cortexa72,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index e4cf943231c..07ce3bee4f0 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -167,7 +167,9 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED | /* V8 Architecture Processors */ ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57) +ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57) ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1) /* V8 big.LITTLE implementations */ ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a57) +ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a57) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 92d9d275910..6aa092f9edd 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -310,11 +310,17 @@ EnumValue Enum(processor_type) String(cortex-a57) Value(cortexa57) EnumValue +Enum(processor_type) String(cortex-a72) Value(cortexa72) + +EnumValue Enum(processor_type) String(xgene1) Value(xgene1) EnumValue Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53) +EnumValue +Enum(processor_type) String(cortex-a72.cortex-a53) Value(cortexa72cortexa53) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index dcd505423f6..d459f27c98c 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -32,6 +32,6 @@ cortexr4f,cortexr5,cortexr7, cortexm7,cortexm4,cortexm3, marvell_pj4,cortexa15cortexa7,cortexa17cortexa7, - cortexa53,cortexa57,xgene1, - cortexa57cortexa53" + cortexa53,cortexa57,cortexa72, + xgene1,cortexa57cortexa53,cortexa72cortexa53" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index b8b31675225..49b7557558f 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -71,6 +71,8 @@ |mcpu=cortex-a53 \ |mcpu=cortex-a57 \ |mcpu=cortex-a57.cortex-a53 \ + |mcpu=cortex-a72 \ + |mcpu=cortex-a72.cortex-a53 \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m0.small-multiply \ @@ -93,6 +95,8 @@ |mcpu=cortex-a53 \ |mcpu=cortex-a57 \ |mcpu=cortex-a57.cortex-a53 \ + |mcpu=cortex-a72 \ + |mcpu=cortex-a72.cortex-a53 \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m0.small-multiply \ diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 60ac1b6dd79..40ad79d1255 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -89,6 +89,8 @@ MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a17.cortex-a7 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53 +MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72 +MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72.cortex-a53 # Arch Matches MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d70fdade2ed..7d5d54462af 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11472,12 +11472,12 @@ architecture. @opindex mtune Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: -@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{thunderx}, -@samp{xgene1}. +@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, +@samp{cortex-a72}, @samp{thunderx}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance -of the code for a big.LITTLE system. The only permissible value is -@samp{cortex-a57.cortex-a53}. +of the code for a big.LITTLE system. Permissible values for this +option are: @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}. Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=} are specified, the code will be tuned to perform well across a range @@ -12344,7 +12344,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, -@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57}, +@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, +@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7}, @samp{cortex-m4}, @@ -12363,7 +12364,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: -@samp{cortex-a15.cortex-a7}, @samp{cortex-a57.cortex-a53}. +@samp{cortex-a15.cortex-a7}, @samp{cortex-a57.cortex-a53}, +@samp{cortex-a72.cortex-a53}. @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}. |