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authorBen Elliston <bje@au.ibm.com>2008-10-14 05:15:35 +0000
committerBen Elliston <bje@gcc.gnu.org>2008-10-14 16:15:35 +1100
commitf8f49aeaade57ba895b8ae8c56c69b5d4eca7cfa (patch)
tree8512c770c3d1fbdb6de56bfd15be3a0d76115e92
parent88de9dd0236282cc67952ace2233f2a2be054c90 (diff)
downloadgcc-f8f49aeaade57ba895b8ae8c56c69b5d4eca7cfa.tar.gz
* config/rs6000/rs6000.md (cell_micro): Fix formatting.
From-SVN: r141103
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/rs6000/rs6000.md7
2 files changed, 7 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7cdbe4489b8..93fc32b2ec1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2008-10-14 Ben Elliston <bje@au.ibm.com>
+
+ * config/rs6000/rs6000.md (cell_micro): Fix formatting.
+
2008-10-13 Joseph Myers <joseph@codesourcery.com>
* combine.c (simplify_set): Avoid calling LOAD_EXTEND_OP on
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4a49a5b505d..4fa690d8097 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -145,10 +145,9 @@
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
- (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
- (const_string "always")
- (const_string "not")))
-
+ (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
+ (const_string "always")
+ (const_string "not")))
(automata_option "ndfa")