PR target/78904

	* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use
	nonimmediate_operand instead of nonimmediate_x64nomem_operand.
	(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
	(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand
	instead of general_x64nomem_operand.
	* config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove.
	(general_x64nomem_operand): Ditto.

testsuite/ChangeLog:

	PR target/78904
	* gcc.target/i386/pr78904-2.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243933 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 75 insertions, 23 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e7865bdf7b5..3b0e8161ae1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use
+	nonimmediate_operand instead of nonimmediate_x64nomem_operand.
+	(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
+	(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand
+	instead of general_x64nomem_operand.
+	* config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove.
+	(general_x64nomem_operand): Ditto.
+
 2016-12-26  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR target/78904
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f3f358326ac..3fd85974bb5 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1295,7 +1295,7 @@
 (define_insn "*cmpqi_ext_1"
   [(set (reg FLAGS_REG)
 	(compare
-	  (match_operand:QI 0 "nonimmediate_x64nomem_operand" "Q,m")
+	  (match_operand:QI 0 "nonimmediate_operand" "Q,m")
 	  (subreg:QI
 	    (zero_extract:SI
 	      (match_operand 1 "ext_register_operand" "Q,Q")
@@ -1340,7 +1340,7 @@
 	      (match_operand 0 "ext_register_operand" "Q,Q")
 	      (const_int 8)
 	      (const_int 8)) 0)
-	  (match_operand:QI 1 "general_x64nomem_operand" "Qn,m")))]
+	  (match_operand:QI 1 "general_operand" "Qn,m")))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "isa" "*,nox64")
@@ -2781,7 +2781,7 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*extvqi"
-  [(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
         (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q")
                          (const_int 8)
                          (const_int 8)))]
@@ -2836,7 +2836,7 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*extzvqi"
-  [(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
         (subreg:QI
 	  (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
 			   (const_int 8)
@@ -2897,7 +2897,7 @@
   [(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q")
 			     (const_int 8)
 			     (const_int 8))
-	(match_operand:SWI248 1 "general_x64nomem_operand" "Qn,m"))]
+	(match_operand:SWI248 1 "general_operand" "Qn,m"))]
   ""
 {
   if (CONST_INT_P (operands[1]))
@@ -6087,7 +6087,7 @@
 	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
-	    (match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
+	    (match_operand:QI 2 "general_operand" "Qn,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   ""
 {
@@ -7889,7 +7889,7 @@
 	      (zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q")
 			       (const_int 8)
 			       (const_int 8)) 0)
-	    (match_operand:QI 1 "general_x64nomem_operand" "Qn,m"))
+	    (match_operand:QI 1 "general_operand" "Qn,m"))
 	  (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
@@ -8417,7 +8417,7 @@
 	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
-	    (match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
+	    (match_operand:QI 2 "general_operand" "Qn,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "and{b}\t{%2, %h0|%h0, %2}"
@@ -8803,7 +8803,7 @@
 	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
-	    (match_operand:QI 2 "general_x64nomem_operand" "Qn,m")) 0))
+	    (match_operand:QI 2 "general_operand" "Qn,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "<logic>{b}\t{%2, %h0|%h0, %2}"
@@ -8913,7 +8913,7 @@
 	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
-	    (match_operand:QI 2 "general_x64nomem_operand" "Qn,m"))
+	    (match_operand:QI 2 "general_operand" "Qn,m"))
 	  (const_int 0)))
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
 			 (const_int 8)
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index eb985983ff6..b2d847e991f 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -100,18 +100,6 @@
 	  && (REGNO (op) > LAST_VIRTUAL_REGISTER || QI_REGNO_P (REGNO (op))));
 })
 
-;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
-(define_predicate "nonimmediate_x64nomem_operand"
-  (if_then_else (match_test "TARGET_64BIT")
-    (match_operand 0 "register_operand")
-    (match_operand 0 "nonimmediate_operand")))
-
-;; Match general operands, but exclude memory operands on 64bit targets.
-(define_predicate "general_x64nomem_operand"
-  (if_then_else (match_test "TARGET_64BIT")
-    (match_operand 0 "nonmemory_operand")
-    (match_operand 0 "general_operand")))
-
 ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
 (define_predicate "register_ssemem_operand"
   (if_then_else
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 31f0e434583..fc9233a21bb 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,7 +1,12 @@
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* gcc.target/i386/pr78904-2.c: New test.
+
 2016-12-26  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR target/78904
-	* gcc.target/i386/pr78904.c: New test.
+	* gcc.target/i386/pr78904-1.c: New test.
 
 2016-12-23  Andre Vehreschild  <vehre@gcc.gnu.org>
 
diff --git a/gcc/testsuite/gcc.target/i386/pr78904.c b/gcc/testsuite/gcc.target/i386/pr78904-1.c
index d27d7fd651d..d27d7fd651d 100644
--- a/gcc/testsuite/gcc.target/i386/pr78904.c
+++ b/gcc/testsuite/gcc.target/i386/pr78904-1.c
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-2.c b/gcc/testsuite/gcc.target/i386/pr78904-2.c
new file mode 100644
index 00000000000..03792b0242f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-2.c
@@ -0,0 +1,48 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+
+struct S1
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+};
+
+extern struct S1 t;
+
+struct S1 test_and (struct S1 a, struct S1 b)
+{
+  a.val &= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb\[^\n\r]*, %.h" } } */
+
+struct S1 test_or (struct S1 a, struct S1 b)
+{
+  a.val |= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb\[^\n\r]*, %.h" } } */
+
+struct S1 test_xor (struct S1 a, struct S1 b)
+{
+  a.val ^= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb\[^\n\r]*, %.h" } } */
+
+struct S1 test_add (struct S1 a, struct S1 b)
+{
+  a.val += t.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb\[^\n\r]*, %.h" } } */