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| author | olegendo <olegendo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-03 11:50:38 +0000 |
|---|---|---|
| committer | olegendo <olegendo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-03 11:50:38 +0000 |
| commit | 5e8551bdc9dc48630fde2980335287df017e814b (patch) | |
| tree | db13079bd93dd5aa02a6ec135f11e904f84055b5 | |
| parent | f0a8ace174bbef647b2c53ecade3b8a9495ee166 (diff) | |
| download | gcc-5e8551bdc9dc48630fde2980335287df017e814b.tar.gz | |
* config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210033 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/sh/sh.h | 16 |
2 files changed, 20 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6464565bca2..e6b50130b0f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2014-05-03 Oleg Endo <olegendo@gcc.gnu.org> + * config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases. + +2014-05-03 Oleg Endo <olegendo@gcc.gnu.org> + * config/sh/sh.h (ROUND_ADVANCE): Delete macro. (ROUND_REG, PASS_IN_REG_P): Move and rename macros to ... * config/sh/sh.c (sh_round_reg, sh_pass_in_reg_p): ... these new diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 0b6bd1bc94a..00ee0edffda 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -267,9 +267,25 @@ extern int code_for_indirect_jump_scratch; #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" #endif +/* Define which ISA type to pass to the assembler. + For SH4 we pass SH4A to allow using some instructions that are available + on some SH4 variants, but officially are part of the SH4A ISA. */ #define SH_ASM_SPEC \ "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ +%{m1:--isa=sh} \ +%{m2:--isa=sh2} \ +%{m2e:--isa=sh2e} \ +%{m3:--isa=sh3} \ +%{m3e:--isa=sh3e} \ +%{m4:--isa=sh4a} \ +%{m4-single:--isa=sh4a} \ +%{m4-single-only:--isa=sh4a} \ +%{m4-nofpu:--isa=sh4a-nofpu} \ +%{m4a:--isa=sh4a} \ +%{m4a-single:--isa=sh4a} \ +%{m4a-single-only:--isa=sh4a} \ +%{m4a-nofpu:--isa=sh4a-nofpu} \ %{m2a:--isa=sh2a} \ %{m2a-single:--isa=sh2a} \ %{m2a-single-only:--isa=sh2a} \ |