* config/alpha/alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.

	* config/alpha/alpha.c (alpha_rtx_costs): Handle CONST_WIDE_INT.
	(alpha_extract_integer): Ditto.
	(alpha_legitimate_constant_p): Ditto.
	(alpha_split_tmode_pair): Ditto.
	(alpha_preferred_reload_class): Add CONST_WIDE_INT.
	(alpha_expand_mov): Ditto.
	(print_operand): Remove handling of 'H' modifier.
	<case 'm'>: Remove CONST_DOUBLE handling.
	(summarize_insn): Handle CONST_WIDE_INT.
	* config/alpha/alpha.md (*andsi_internal): Remove H constraint.
	(anddi3): Ditto.
	(movti): Handle CONST_WIDE_INT.
	* config/alpha/constraints.md ('H'): Remove constraint definition.
	('G'): Do not match MODE_FLOAT class.
	* config/alpha/predicates.md (const0_operand): Also match
	const_wide_int.
	(non_add_const_operand): Ditto.
	(non_zero_const_operand): Ditto.
	(some_operand): Ditto.
	(input_operand): Ditto.  Handle CONST_WIDE_INT.
	(and_operand): Do not match const_double.
	* config/alpha/sync.md (fetchop_constr): Remove H constraint.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223097 138bc75d-0d04-0410-961f-82ee72b054a4

7 files changed, 62 insertions, 65 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4f55ef01935..4d67a4d9153 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+2015-05-12  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/alpha/alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.
+	* config/alpha/alpha.c (alpha_rtx_costs): Handle CONST_WIDE_INT.
+	(alpha_extract_integer): Ditto.
+	(alpha_legitimate_constant_p): Ditto.
+	(alpha_split_tmode_pair): Ditto.
+	(alpha_preferred_reload_class): Add CONST_WIDE_INT.
+	(alpha_expand_mov): Ditto.
+	(print_operand): Remove handling of 'H' modifier.
+	<case 'm'>: Remove CONST_DOUBLE handling.
+	(summarize_insn): Handle CONST_WIDE_INT.
+	* config/alpha/alpha.md (*andsi_internal): Remove H constraint.
+	(anddi3): Ditto.
+	(movti): Handle CONST_WIDE_INT.
+	* config/alpha/constraints.md ('H'): Remove constraint definition.
+	('G'): Do not match MODE_FLOAT class.
+	* config/alpha/predicates.md (const0_operand): Also match
+	const_wide_int.
+	(non_add_const_operand): Ditto.
+	(non_zero_const_operand): Ditto.
+	(some_operand): Ditto.
+	(input_operand): Ditto.  Handle CONST_WIDE_INT.
+	(and_operand): Do not match const_double.
+	* config/alpha/sync.md (fetchop_constr): Remove H constraint.
+
 2015-05-12  Andrew MacLeod  <amacleod@redhat.com>
 
 	PR target/65697
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 4af0dbec7a0..5f5edebc55a 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1412,6 +1412,7 @@ alpha_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
       /* FALLTHRU */
 
     case CONST_DOUBLE:
+    case CONST_WIDE_INT:
       if (x == CONST0_RTX (mode))
 	*total = 0;
       else if ((outer_code == PLUS && add_operand (x, VOIDmode))
@@ -1647,6 +1648,7 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
 
   /* These sorts of constants we can easily drop to memory.  */
   if (CONST_INT_P (x)
+      || GET_CODE (x) == CONST_WIDE_INT
       || GET_CODE (x) == CONST_DOUBLE
       || GET_CODE (x) == CONST_VECTOR)
     {
@@ -2104,8 +2106,8 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
   return target;
 }
 
-/* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return 
-   the low 64 bits.  */
+/* Given an integral CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
+   or CONST_VECTOR, return the low 64 bits.  */
 
 static void
 alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
@@ -2115,18 +2117,15 @@ alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
   if (GET_CODE (x) == CONST_VECTOR)
     x = simplify_subreg (DImode, x, GET_MODE (x), 0);
 
-
   if (CONST_INT_P (x))
-    {
-      i0 = INTVAL (x);
-      i1 = -(i0 < 0);
-    }
+    i0 = INTVAL (x);
+  else if (CONST_WIDE_INT_P (x))
+    i0 = CONST_WIDE_INT_ELT (x, 0);
   else
-    {
-      i0 = CONST_DOUBLE_LOW (x);
-      i1 = -(i0 < 0);
-    }
+    i0 = CONST_DOUBLE_LOW (x);
 
+  i1 = -(i0 < 0);
+      
   *p0 = i0;
   *p1 = i1;
 }
@@ -2163,13 +2162,16 @@ alpha_legitimate_constant_p (machine_mode mode, rtx x)
       /* TLS symbols are never valid.  */
       return SYMBOL_REF_TLS_MODEL (x) == 0;
 
-    case CONST_DOUBLE:
+    case CONST_WIDE_INT:
       if (x == CONST0_RTX (mode))
 	return true;
-      if (FLOAT_MODE_P (mode))
-	return false;
       goto do_integer;
 
+    case CONST_DOUBLE:
+      if (x == CONST0_RTX (mode))
+	return true;
+      return false;
+
     case CONST_VECTOR:
       if (x == CONST0_RTX (mode))
 	return true;
@@ -2249,6 +2251,7 @@ alpha_expand_mov (machine_mode mode, rtx *operands)
 
   /* Split large integers.  */
   if (CONST_INT_P (operands[1])
+      || GET_CODE (operands[1]) == CONST_WIDE_INT
       || GET_CODE (operands[1]) == CONST_DOUBLE
       || GET_CODE (operands[1]) == CONST_VECTOR)
     {
@@ -3291,6 +3294,7 @@ alpha_split_tmode_pair (rtx operands[4], machine_mode mode,
       break;
 
     case CONST_INT:
+    case CONST_WIDE_INT:
     case CONST_DOUBLE:
       gcc_assert (operands[1] == CONST0_RTX (mode));
       operands[2] = operands[3] = const0_rtx;
@@ -5151,13 +5155,6 @@ print_operand (FILE *file, rtx x, int code)
       fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
       break;
 
-    case 'H':
-      if (GET_CODE (x) == HIGH)
-	output_addr_const (file, XEXP (x, 0));
-      else
-	output_operand_lossage ("invalid %%H value");
-      break;
-
     case 'J':
       {
 	const char *lituse;
@@ -5254,27 +5251,7 @@ print_operand (FILE *file, rtx x, int code)
 
     case 'm':
       /* Write mask for ZAP insn.  */
-      if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  HOST_WIDE_INT mask = 0;
-	  HOST_WIDE_INT value;
-
-	  value = CONST_DOUBLE_LOW (x);
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
-	       i++, value >>= 8)
-	    if (value & 0xff)
-	      mask |= (1 << i);
-
-	  value = CONST_DOUBLE_HIGH (x);
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
-	       i++, value >>= 8)
-	    if (value & 0xff)
-	      mask |= (1 << (i + sizeof (int)));
-
-	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
-	}
-
-      else if (CONST_INT_P (x))
+      if (CONST_INT_P (x))
 	{
 	  HOST_WIDE_INT mask = 0, value = INTVAL (x);
 
@@ -8602,8 +8579,8 @@ summarize_insn (rtx x, struct shadow_summary *sum, int set)
       summarize_insn (XEXP (x, 0), sum, 0);
       break;
 
-    case CONST_INT:   case CONST_DOUBLE:
-    case SYMBOL_REF:  case LABEL_REF:     case CONST:
+    case CONST_INT:   case CONST_WIDE_INT:  case CONST_DOUBLE:
+    case SYMBOL_REF:  case LABEL_REF:       case CONST:
     case SCRATCH:     case ASM_INPUT:
       break;
 
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index fb3849a6b80..196349df911 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -1066,3 +1066,5 @@ extern long alpha_auto_offset;
 
 /* The system headers under Alpha systems are generally C++-aware.  */
 #define NO_IMPLICIT_EXTERN_C
+
+#define TARGET_SUPPORTS_WIDE_INT 1
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index eb59f6ca427..2323de9462f 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -922,7 +922,7 @@
 (define_insn "*andsi_internal"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 	(and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
-		(match_operand:SI 2 "and_operand" "rI,N,MH")))]
+		(match_operand:SI 2 "and_operand" "rI,N,M")))]
   ""
   "@
    and %r1,%2,%0
@@ -933,7 +933,7 @@
 (define_insn "anddi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
-		(match_operand:DI 2 "and_operand" "rI,N,MH")))]
+		(match_operand:DI 2 "and_operand" "rI,N,M")))]
   ""
   "@
    and %r1,%2,%0
@@ -4154,6 +4154,7 @@
      32-bit constants in TImode and rely on the splitter, but
      this doesn't seem to be worth the pain.  */
   else if (CONST_INT_P (operands[1])
+	   || GET_CODE (operands[1]) == CONST_WIDE_INT
 	   || GET_CODE (operands[1]) == CONST_DOUBLE)
     {
       rtx in[2], out[2], target;
diff --git a/gcc/config/alpha/constraints.md b/gcc/config/alpha/constraints.md
index 58cddd8e19b..ef7068248b0 100644
--- a/gcc/config/alpha/constraints.md
+++ b/gcc/config/alpha/constraints.md
@@ -18,7 +18,7 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;;; Unused letters:
-;;;    ABCDEF               V  YZ
+;;;    ABCDEF H             V  YZ
 ;;;       de ghijkl   pq  tu wxyz
 
 ;; Integer register constraints.
@@ -84,17 +84,11 @@
   (and (match_code "const_int")
        (match_test "ival == 1 || ival == 2 || ival == 3")))
 
-(define_constraint "H"
-  "A valid operand of a ZAP insn, when building with 32-bit HOST_WIDE_INT"
-  (and (match_code "const_double")
-       (match_test "mode == VOIDmode && zap_mask (hval) && zap_mask (lval)")))
-
 ;; Floating-point constant constraints.
 (define_constraint "G"
   "The floating point zero constant"
   (and (match_code "const_double")
-       (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
-		    && op == CONST0_RTX (mode)")))
+       (match_test "op == CONST0_RTX (mode)")))
 
 ;; "Extra" constraints.
 (define_constraint "Q"
diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md
index 241a4ceec69..b33044d43a9 100644
--- a/gcc/config/alpha/predicates.md
+++ b/gcc/config/alpha/predicates.md
@@ -19,7 +19,7 @@
 
 ;; Return 1 if OP is the zero constant for MODE.
 (define_predicate "const0_operand"
-  (and (match_code "const_int,const_double,const_vector")
+  (and (match_code "const_int,const_wide_int,const_double,const_vector")
        (match_test "op == CONST0_RTX (mode)")))
 
 ;; Returns true if OP is either the constant zero or a register.
@@ -66,12 +66,12 @@
 ;; Return 1 if the operand is a non-symbolic constant operand that
 ;; does not satisfy add_operand.
 (define_predicate "non_add_const_operand"
-  (and (match_code "const_int,const_double,const_vector")
+  (and (match_code "const_int,const_wide_int,const_double,const_vector")
        (not (match_operand 0 "add_operand"))))
 
 ;; Return 1 if the operand is a non-symbolic, nonzero constant operand.
 (define_predicate "non_zero_const_operand"
-  (and (match_code "const_int,const_double,const_vector")
+  (and (match_code "const_int,const_wide_int,const_double,const_vector")
        (match_test "op != CONST0_RTX (mode)")))
 
 ;; Return 1 if OP is the constant 4 or 8.
@@ -85,11 +85,7 @@
     (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
 		 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
 		 || zap_mask (INTVAL (op))")
-    (if_then_else (match_code "const_double")
-      (match_test "GET_MODE (op) == VOIDmode
-		   && zap_mask (CONST_DOUBLE_LOW (op))
-		   && zap_mask (CONST_DOUBLE_HIGH (op))")
-      (match_operand 0 "register_operand"))))
+    (match_operand 0 "register_operand")))
 
 ;; Return 1 if OP is a valid first operand to an IOR or XOR insn.
 (define_predicate "or_operand"
@@ -155,7 +151,7 @@
 ;; Return 1 if OP is something that can be reloaded into a register;
 ;; if it is a MEM, it need not be valid.
 (define_predicate "some_operand"
-  (ior (match_code "reg,mem,const_int,const_double,const_vector,
+  (ior (match_code "reg,mem,const_int,const_wide_int,const_double,const_vector,
 		    label_ref,symbol_ref,const,high")
        (and (match_code "subreg")
 	    (match_test "some_operand (SUBREG_REG (op), VOIDmode)"))))
@@ -169,7 +165,7 @@
 ;; Return 1 if OP is a valid operand for the source of a move insn.
 (define_predicate "input_operand"
   (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
-	       const_double,const_vector,const_int")
+	       const_double,const_vector,const_int,const_wide_int")
 {
   switch (GET_CODE (op))
     {
@@ -205,6 +201,7 @@
       return ((TARGET_BWX || (mode != HImode && mode != QImode))
 	      && general_operand (op, mode));
 
+    case CONST_WIDE_INT:
     case CONST_DOUBLE:
       return op == CONST0_RTX (mode);
 
diff --git a/gcc/config/alpha/sync.md b/gcc/config/alpha/sync.md
index ecb1c6d1669..d5f33eb2c51 100644
--- a/gcc/config/alpha/sync.md
+++ b/gcc/config/alpha/sync.md
@@ -24,7 +24,7 @@
   [(plus "add_operand") (minus "reg_or_8bit_operand")
    (ior "or_operand") (xor "or_operand") (and "and_operand")])
 (define_code_attr fetchop_constr
-  [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
+  [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNM")])
 
 
 (define_expand "memory_barrier"