PR target/78904

	* config/i386/constraints.md (Bn): New special memory constraint.
	* config/i386/predicates.md (norex_memory_operand): New predicate.
	* config/i386/i386.md (*extzvqi_mem_rex64): New insn pattern and
	corresponding peephole2 pattern.

testsuite/ChangeLog:

	PR target/78904
	* gcc.target/i386/pr78904-4.c: New test.
	* gcc.target/i386/pr78904-5.c: Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243955 138bc75d-0d04-0410-961f-82ee72b054a4

7 files changed, 99 insertions, 2 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c8e2c420936..580d91877ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-12-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/constraints.md (Bn): New special memory constraint.
+	* config/i386/predicates.md (norex_memory_operand): New predicate.
+	* config/i386/i386.md (*extzvqi_mem_rex64): New insn pattern and
+	corresponding peephole2 pattern.
+
 2016-12-27  Sandra Loosemore  <sandra@codesourcery.com>
 
 	* doc/cppdiropts.texi, doc/cppwarnopts.texi:  New files, split from...
@@ -6,7 +14,7 @@
 	* doc/invoke.texi (Option Summary): Add missing preprocesor-related
 	options.  Adjust sorting and formatting.
 	(Warning Options): Include cppwarnopts.texi.
-	(Preprocessor Options): Add pointers and list the specific 
+	(Preprocessor Options): Add pointers and list the specific
 	preprocessor options from cppopts.texi first instead of last.
 	(Directory Options): Move/merge documentation of -I, -iquote, and
 	-I- to cppdiropts.texi.  Include that file here.
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 6aa2e4f95b7..19edd25c699 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -169,6 +169,7 @@
 ;;  g  GOT memory operand.
 ;;  m  Vector memory operand
 ;;  c  Constant memory operand
+;;  n  Memory operand without REX prefix
 ;;  s  Sibcall memory operand, not valid for TARGET_X32
 ;;  w  Call memory operand, not valid for TARGET_X32
 ;;  z  Constant call address operand.
@@ -191,6 +192,10 @@
   (and (match_operand 0 "memory_operand")
        (match_test "constant_address_p (XEXP (op, 0))")))
 
+(define_special_memory_constraint "Bn"
+  "@internal Memory operand without REX prefix."
+  (match_operand 0 "norex_memory_operand"))
+
 (define_constraint "Bs"
   "@internal Sibcall memory operand."
   (ior (and (not (match_test "TARGET_X32"))
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 13769f987ff..cf9dc03ba8b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2835,9 +2835,20 @@
   [(set_attr "type" "imovx")
    (set_attr "mode" "SI")])
 
+(define_insn "*extzvqi_mem_rex64"
+  [(set (match_operand:QI 0 "norex_memory_operand" "=Bn")
+	(subreg:QI
+	  (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
+			   (const_int 8)
+			   (const_int 8)) 0))]
+  "TARGET_64BIT && reload_completed"
+  "mov{b}\t{%h1, %0|%0, %h1}"
+  [(set_attr "type" "imov")
+   (set_attr "mode" "QI")])
+
 (define_insn "*extzvqi"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
-        (subreg:QI
+	(subreg:QI
 	  (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
 			   (const_int 8)
 			   (const_int 8)) 0))]
@@ -2863,6 +2874,21 @@
 	(const_string "SI")
 	(const_string "QI")))])
 
+(define_peephole2
+  [(set (match_operand:QI 0 "register_operand")
+	(subreg:QI
+	  (zero_extract:SI (match_operand 1 "ext_register_operand")
+			   (const_int 8)
+			   (const_int 8)) 0))
+   (set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))]
+  "TARGET_64BIT
+   && peep2_reg_dead_p (2, operands[0])"
+  [(set (match_dup 2)
+	(subreg:QI
+	  (zero_extract:SI (match_dup 1)
+			   (const_int 8)
+			   (const_int 8)) 0))])
+
 (define_expand "insv<mode>"
   [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand")
 			     (match_operand:SI 1 "const_int_operand")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index b2d847e991f..a1ea34f4f28 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1037,6 +1037,10 @@
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "const0_operand")))
 
+(define_predicate "norex_memory_operand"
+  (and (match_operand 0 "memory_operand")
+       (not (match_test "x86_extended_reg_mentioned_p (op)"))))
+
 ;; Return true for RTX codes that force SImode address.
 (define_predicate "SImode_address_operand"
   (match_code "subreg,zero_extend,and"))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2f2db1ac9a1..09b2b5bda7b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2016-12-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* gcc.target/i386/pr78904-4.c: New test.
+	* gcc.target/i386/pr78904-5.c: Ditto.
+
 2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-4.c b/gcc/testsuite/gcc.target/i386/pr78904-4.c
new file mode 100644
index 00000000000..d110c2eec86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-4.c
@@ -0,0 +1,21 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+
+typedef __SIZE_TYPE__ size_t;
+
+struct S1
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+};
+
+extern unsigned char t[256];
+
+void foo (struct S1 a, size_t i)
+{
+  t[i] = a.val;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]*%.h," } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-5.c b/gcc/testsuite/gcc.target/i386/pr78904-5.c
new file mode 100644
index 00000000000..5286e67e915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-5.c
@@ -0,0 +1,27 @@
+/* PR target/78904 */
+/* { dg-do assemble { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+typedef __SIZE_TYPE__ size_t;
+
+struct S1
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+};
+
+extern unsigned char t[256];
+
+void foo (struct S1 a, size_t i)
+{
+  t[i] = a.val;
+}
+
+void bar (struct S1 a, size_t i)
+{
+  register size_t _i __asm ("r10") = i;
+
+  asm volatile ("" : "+r" (_i));
+  t[_i] = a.val;
+}