Fix LWP.

2009-12-14  Jakub Jelinek  <jakub@redhat.com>
	    Sebastian Pop  <sebastian.pop@amd.com>

	* config/i386/i386-builtin-types.def (PVOID): Declared.
	(VOID_FTYPE_PVOID): Declared.
	(PVOID_FTYPE_VOID): Declared.
	(UCHAR_FTYPE_USHORT_UINT_USHORT): Removed.
	(VOID_FTYPE_USHORT_UINT_USHORT): Removed.
	* config/i386/i386.c (IX86_BUILTIN_LLWPCB16, IX86_BUILTIN_LLWPCB32,
	IX86_BUILTIN_LLWPCB64, IX86_BUILTIN_SLWPCB16, IX86_BUILTIN_SLWPCB32,
	IX86_BUILTIN_SLWPCB64, IX86_BUILTIN_LWPVAL16, IX86_BUILTIN_LWPINS16):
	Removed.
	(IX86_BUILTIN_LLWPCB, IX86_BUILTIN_SLWPCB): New.
	(bdesc_special_args): Adjust declaration of __builtin_ia32_llwpcb,
	__builtin_ia32_slwpcb, __builtin_ia32_lwpval32,
	__builtin_ia32_lwpval64, __builtin_ia32_lwpins32, and
	__builtin_ia32_lwpins64.
	(ix86_expand_special_args_builtin): Handle VOID_FTYPE_PVOID.
	Do not handle VOID_FTYPE_USHORT_UINT_USHORT and
	UCHAR_FTYPE_USHORT_UINT_USHORT.  Warn when the third operand is
	not an immediate.  Also handle builtin functions with 3 arguments.
	(ix86_expand_builtin): Handle IX86_BUILTIN_LLWPCB and
	IX86_BUILTIN_SLWPCB.
	* config/i386/i386.md (UNSPEC_LLWP_INTRINSIC, UNSPEC_SLWP_INTRINSIC):
	Renamed UNSPECV_LLWP_INTRINSIC and UNSPECV_SLWP_INTRINSIC.
	(memory attribute): Handle lwp.
	(lwp*): Rewrite all the insn patterns for LWP.
	* config/i386/lwpintrin.h (__llwpcb16, __llwpcb32, __llwpcb64,
	__slwpcb16, __slwpcb32, __slwpcb64, __lwpval16, __lwpins16): Removed.
	(__llwpcb, __slwpcb): New.

	testsuite/
	* gcc.target/i386/sse-12.c: Add -mpopcnt and -mlwp.
	* gcc.target/i386/sse-13.c: Same.
	(__builtin_ia32_lwpval32, __builtin_ia32_lwpval64,
	__builtin_ia32_lwpins32, __builtin_ia32_lwpins64): Added testcases.
	* gcc.target/i386/sse-14.c: Add -mpopcnt -mabm -mlwp.
	Added tests for __lwpval32, __lwpins32, __lwpval64, and __lwpins64.
	* gcc.target/i386/sse-22.c: Added tests for popcnt, abm, and lwp.
	* gcc.target/i386/sse-23.c: Same.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155217 138bc75d-0d04-0410-961f-82ee72b054a4

10 files changed, 272 insertions, 187 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d9079c3aa87..f8535bad108 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,44 @@
+2009-12-14  Jakub Jelinek  <jakub@redhat.com>
+	    Sebastian Pop  <sebastian.pop@amd.com>
+
+	* config/i386/i386-builtin-types.def (PVOID): Declared.
+	(VOID_FTYPE_PVOID): Declared.
+	(PVOID_FTYPE_VOID): Declared.
+	(UCHAR_FTYPE_USHORT_UINT_USHORT): Removed.
+	(VOID_FTYPE_USHORT_UINT_USHORT): Removed.
+	* config/i386/i386.c (IX86_BUILTIN_LLWPCB16, IX86_BUILTIN_LLWPCB32,
+	IX86_BUILTIN_LLWPCB64, IX86_BUILTIN_SLWPCB16, IX86_BUILTIN_SLWPCB32,
+	IX86_BUILTIN_SLWPCB64, IX86_BUILTIN_LWPVAL16, IX86_BUILTIN_LWPINS16):
+	Removed.
+	(IX86_BUILTIN_LLWPCB, IX86_BUILTIN_SLWPCB): New.
+	(bdesc_special_args): Adjust declaration of __builtin_ia32_llwpcb,
+	__builtin_ia32_slwpcb, __builtin_ia32_lwpval32,
+	__builtin_ia32_lwpval64, __builtin_ia32_lwpins32, and
+	__builtin_ia32_lwpins64.
+	(ix86_expand_special_args_builtin): Handle VOID_FTYPE_PVOID.
+	Do not handle VOID_FTYPE_USHORT_UINT_USHORT and
+	UCHAR_FTYPE_USHORT_UINT_USHORT.  Warn when the third operand is
+	not an immediate.  Also handle builtin functions with 3 arguments.
+	(ix86_expand_builtin): Handle IX86_BUILTIN_LLWPCB and
+	IX86_BUILTIN_SLWPCB.
+	* config/i386/i386.md (UNSPEC_LLWP_INTRINSIC, UNSPEC_SLWP_INTRINSIC):
+	Renamed UNSPECV_LLWP_INTRINSIC and UNSPECV_SLWP_INTRINSIC.
+	(memory attribute): Handle lwp.
+	(lwp*): Rewrite all the insn patterns for LWP.
+	* config/i386/lwpintrin.h (__llwpcb16, __llwpcb32, __llwpcb64,
+	__slwpcb16, __slwpcb32, __slwpcb64, __lwpval16, __lwpins16): Removed.
+	(__llwpcb, __slwpcb): New.
+
+	testsuite/
+	* gcc.target/i386/sse-12.c: Add -mpopcnt and -mlwp.
+	* gcc.target/i386/sse-13.c: Same.
+	(__builtin_ia32_lwpval32, __builtin_ia32_lwpval64,
+	__builtin_ia32_lwpins32, __builtin_ia32_lwpins64): Added testcases.
+	* gcc.target/i386/sse-14.c: Add -mpopcnt -mabm -mlwp.
+	Added tests for __lwpval32, __lwpins32, __lwpval64, and __lwpins64.
+	* gcc.target/i386/sse-22.c: Added tests for popcnt, abm, and lwp.
+	* gcc.target/i386/sse-23.c: Same.
+
 2009-12-14  Dmitry Gorbachev  <d.g.gorbachev@gmail.com>
 
 	* dominance.c (set_immediate_dominator): Don't mark as inline.
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index e9e4d0c4c83..1fad60f7019 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -104,6 +104,7 @@ DEF_POINTER_TYPE (PCDOUBLE, DOUBLE, CONST)
 DEF_POINTER_TYPE (PCFLOAT, FLOAT, CONST)
 DEF_POINTER_TYPE (PCHAR, CHAR)
 DEF_POINTER_TYPE (PCVOID, VOID, CONST)
+DEF_POINTER_TYPE (PVOID, VOID)
 DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
 DEF_POINTER_TYPE (PFLOAT, FLOAT)
 DEF_POINTER_TYPE (PINT, INT)
@@ -195,6 +196,8 @@ DEF_FUNCTION_TYPE (V8SF, V8SI)
 DEF_FUNCTION_TYPE (V8SI, V4SI)
 DEF_FUNCTION_TYPE (V8SI, V8SF)
 DEF_FUNCTION_TYPE (VOID, PCVOID)
+DEF_FUNCTION_TYPE (VOID, PVOID)
+DEF_FUNCTION_TYPE (PVOID, VOID)
 DEF_FUNCTION_TYPE (VOID, UNSIGNED)
 
 DEF_FUNCTION_TYPE (DI, V2DI, INT)
@@ -301,7 +304,6 @@ DEF_FUNCTION_TYPE (VOID, UNSIGNED, UNSIGNED)
 DEF_FUNCTION_TYPE (INT, V16QI, V16QI, INT)
 DEF_FUNCTION_TYPE (UCHAR, UINT, UINT, UINT)
 DEF_FUNCTION_TYPE (UCHAR, UINT64, UINT, UINT)
-DEF_FUNCTION_TYPE (UCHAR, USHORT, UINT, USHORT)
 DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI)
 DEF_FUNCTION_TYPE (V16QI, V16QI, QI, INT)
 DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT)
@@ -343,7 +345,6 @@ DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, V4SF)
 DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, V8SF)
 DEF_FUNCTION_TYPE (VOID, UINT, UINT, UINT)
 DEF_FUNCTION_TYPE (VOID, UINT64, UINT, UINT)
-DEF_FUNCTION_TYPE (VOID, USHORT, UINT, USHORT)
 DEF_FUNCTION_TYPE (VOID, V16QI, V16QI, PCHAR)
 DEF_FUNCTION_TYPE (VOID, V8QI, V8QI, PCHAR)
 DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0e58a176a82..9b739a6c95b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -21251,16 +21251,10 @@ enum ix86_builtins
   IX86_BUILTIN_VPCOMTRUEQ,
 
   /* LWP instructions.  */
-  IX86_BUILTIN_LLWPCB16,
-  IX86_BUILTIN_LLWPCB32,
-  IX86_BUILTIN_LLWPCB64,
-  IX86_BUILTIN_SLWPCB16,
-  IX86_BUILTIN_SLWPCB32,
-  IX86_BUILTIN_SLWPCB64,
-  IX86_BUILTIN_LWPVAL16,
+  IX86_BUILTIN_LLWPCB,
+  IX86_BUILTIN_SLWPCB,
   IX86_BUILTIN_LWPVAL32,
   IX86_BUILTIN_LWPVAL64,
-  IX86_BUILTIN_LWPINS16,
   IX86_BUILTIN_LWPINS32,
   IX86_BUILTIN_LWPINS64,
 
@@ -21532,20 +21526,12 @@ static const struct builtin_description bdesc_special_args[] =
   { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
   { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
 
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1,   "__builtin_ia32_llwpcb16",   IX86_BUILTIN_LLWPCB16,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1,   "__builtin_ia32_llwpcb32",   IX86_BUILTIN_LLWPCB32,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1,   "__builtin_ia32_llwpcb64",   IX86_BUILTIN_LLWPCB64,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1,   "__builtin_ia32_slwpcb16",   IX86_BUILTIN_SLWPCB16,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1,   "__builtin_ia32_slwpcb32",   IX86_BUILTIN_SLWPCB32,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1,   "__builtin_ia32_slwpcb64",   IX86_BUILTIN_SLWPCB64,    UNKNOWN,     (int) VOID_FTYPE_VOID },
-
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3,   "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16,  UNKNOWN,     (int) VOID_FTYPE_USHORT_UINT_USHORT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3,   "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL64,  UNKNOWN,     (int) VOID_FTYPE_UINT_UINT_UINT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3,   "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64,  UNKNOWN,     (int) VOID_FTYPE_UINT64_UINT_UINT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3,   "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16,  UNKNOWN,     (int) UCHAR_FTYPE_USHORT_UINT_USHORT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3,   "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS64,  UNKNOWN,     (int) UCHAR_FTYPE_UINT_UINT_UINT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3,   "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64,  UNKNOWN,     (int) UCHAR_FTYPE_UINT64_UINT_UINT },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
+  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
 
 };
 
@@ -23734,7 +23720,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
     {
       rtx op;
       enum machine_mode mode;
-    } args[2];
+    } args[3];
   enum insn_code icode = d->icode;
   bool last_arg_constant = false;
   const struct insn_data *insn_p = &insn_data[icode];
@@ -23761,6 +23747,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
     case V4DF_FTYPE_PCV2DF:
     case V4DF_FTYPE_PCDOUBLE:
     case V2DF_FTYPE_PCDOUBLE:
+    case VOID_FTYPE_PVOID:
       nargs = 1;
       klass = load;
       memory = 0;
@@ -23804,15 +23791,14 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
       /* Reserve memory operand for target.  */
       memory = ARRAY_SIZE (args);
       break;
-    case VOID_FTYPE_USHORT_UINT_USHORT:
     case VOID_FTYPE_UINT_UINT_UINT:
     case VOID_FTYPE_UINT64_UINT_UINT:
-    case UCHAR_FTYPE_USHORT_UINT_USHORT:
     case UCHAR_FTYPE_UINT_UINT_UINT:
     case UCHAR_FTYPE_UINT64_UINT_UINT:
       nargs = 3;
-      klass = store;
-      memory = 0;
+      klass = load;
+      memory = ARRAY_SIZE (args);
+      last_arg_constant = true;
       break;
     default:
       gcc_unreachable ();
@@ -23852,7 +23838,14 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
 	  if (!match)
 	    switch (icode)
 	      {
-	     default:
+	      case CODE_FOR_lwp_lwpvalsi3:
+	      case CODE_FOR_lwp_lwpvaldi3:
+	      case CODE_FOR_lwp_lwpinssi3:
+	      case CODE_FOR_lwp_lwpinsdi3:
+		error ("the last argument must be a 32-bit immediate");
+		return const0_rtx;
+
+	      default:
 		error ("the last argument must be an 8-bit immediate");
 		return const0_rtx;
 	      }
@@ -23893,6 +23886,9 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
     case 2:
       pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
       break;
+    case 3:
+      pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
+      break;
     default:
       gcc_unreachable ();
     }
@@ -24205,6 +24201,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 	return target;
       }
 
+    case IX86_BUILTIN_LLWPCB:
+      arg0 = CALL_EXPR_ARG (exp, 0);
+      op0 = expand_normal (arg0);
+      icode = CODE_FOR_lwp_llwpcb;
+      if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
+	op0 = copy_to_mode_reg (Pmode, op0);
+      emit_insn (gen_lwp_llwpcb (op0));
+      return 0;
+
+    case IX86_BUILTIN_SLWPCB:
+      icode = CODE_FOR_lwp_slwpcb;
+      if (!target
+	  || ! (*insn_data[icode].operand[0].predicate) (target, Pmode))
+	target = gen_reg_rtx (Pmode);
+      emit_insn (gen_lwp_slwpcb (target));
+      return target;
+
     default:
       break;
     }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a4e688a8d14..22e6049cd0e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -204,10 +204,6 @@
    (UNSPEC_XOP_TRUEFALSE	152)
    (UNSPEC_XOP_PERMUTE		153)
    (UNSPEC_FRCZ			154)
-   (UNSPEC_LLWP_INTRINSIC	155)
-   (UNSPEC_SLWP_INTRINSIC	156)
-   (UNSPECV_LWPVAL_INTRINSIC	157)
-   (UNSPECV_LWPINS_INTRINSIC	158)
 
    ; For AES support
    (UNSPEC_AESENC		159)
@@ -251,7 +247,11 @@
    (UNSPECV_RDTSC		18)
    (UNSPECV_RDTSCP		19)
    (UNSPECV_RDPMC		20)
-   (UNSPECV_VSWAPMOV	21)
+   (UNSPECV_VSWAPMOV		21)
+   (UNSPECV_LLWP_INTRINSIC	22)
+   (UNSPECV_SLWP_INTRINSIC	23)
+   (UNSPECV_LWPVAL_INTRINSIC	24)
+   (UNSPECV_LWPINS_INTRINSIC	25)
   ])
 
 ;; Constants to represent pcomtrue/pcomfalse variants
@@ -578,7 +578,7 @@
 ;; if the instruction is complex.
 
 (define_attr "memory" "none,load,store,both,unknown"
-  (cond [(eq_attr "type" "other,multi,str")
+  (cond [(eq_attr "type" "other,multi,str,lwp")
 	   (const_string "unknown")
 	 (eq_attr "type" "lea,fcmov,fpspc")
 	   (const_string "none")
@@ -20835,113 +20835,86 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "lwp_llwpcbhi1"
-  [(unspec [(match_operand:HI 0 "register_operand" "r")]
-  	   UNSPEC_LLWP_INTRINSIC)]
+(define_expand "lwp_llwpcb"
+  [(unspec_volatile [(match_operand 0 "register_operand" "r")]
+		    UNSPECV_LLWP_INTRINSIC)]
   "TARGET_LWP"
-  "llwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
-
-(define_insn "lwp_llwpcbsi1"
-  [(unspec [(match_operand:SI 0 "register_operand" "r")]
-  	   UNSPEC_LLWP_INTRINSIC)]
-  "TARGET_LWP"
-  "llwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
+  "")
 
-(define_insn "lwp_llwpcbdi1"
-  [(unspec [(match_operand:DI 0 "register_operand" "r")]
-  	   UNSPEC_LLWP_INTRINSIC)]
+(define_insn "*lwp_llwpcb<mode>1"
+  [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
+		    UNSPECV_LLWP_INTRINSIC)]
   "TARGET_LWP"
   "llwpcb\t%0"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
-
-(define_insn "lwp_slwpcbhi1"
-  [(unspec [(match_operand:HI 0 "register_operand" "r")]
-  	   UNSPEC_SLWP_INTRINSIC)]
-  "TARGET_LWP"
-  "slwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
+   (set_attr "mode" "<MODE>")
+   (set_attr "length" "5")])
 
-(define_insn "lwp_slwpcbsi1"
-  [(unspec [(match_operand:SI 0 "register_operand" "r")]
-  	   UNSPEC_SLWP_INTRINSIC)]
+(define_expand "lwp_slwpcb"
+  [(set (match_operand 0 "register_operand" "=r")
+	(unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
   "TARGET_LWP"
-  "slwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
-
-(define_insn "lwp_slwpcbdi1"
-  [(unspec [(match_operand:DI 0 "register_operand" "r")]
-  	   UNSPEC_SLWP_INTRINSIC)]
+  {
+    if (TARGET_64BIT)
+      emit_insn (gen_lwp_slwpcbdi (operands[0]));
+    else
+      emit_insn (gen_lwp_slwpcbsi (operands[0]));
+    DONE;
+  })
+
+(define_insn "lwp_slwpcb<mode>"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec_volatile:P [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
   "TARGET_LWP"
   "slwpcb\t%0"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
-
-(define_insn "lwp_lwpvalhi3"
-  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
-  	   	     (match_operand:SI 1 "nonimmediate_operand" "rm")
-	   	     (match_operand:HI 2 "const_int_operand" "")]
-  	   	    UNSPECV_LWPVAL_INTRINSIC)]
-  "TARGET_LWP"
-  "lwpval\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
+   (set_attr "mode" "<MODE>")
+   (set_attr "length" "5")])
 
-(define_insn "lwp_lwpvalsi3"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
-    	    	     (match_operand:SI 1 "nonimmediate_operand" "rm")
-	    	     (match_operand:SI 2 "const_int_operand" "")]
+(define_expand "lwp_lwpval<mode>3"
+  [(unspec_volatile [(match_operand:SWI48 1 "register_operand" "r")
+    	    	     (match_operand:SI 2 "nonimmediate_operand" "rm")
+		     (match_operand:SI 3 "const_int_operand" "i")]
 		    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
-  "lwpval\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
+  "/* Avoid unused variable warning.  */
+   (void) operand0;")
 
-(define_insn "lwp_lwpvaldi3"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:SI 2 "const_int_operand" "")]
+(define_insn "*lwp_lwpval<mode>3_1"
+  [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
+    	    	     (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (match_operand:SI 2 "const_int_operand" "i")]
 		    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
   "lwpval\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
-
-(define_insn "lwp_lwpinshi3"
-  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:HI 2 "const_int_operand" "")]
-		    UNSPECV_LWPINS_INTRINSIC)]
-  "TARGET_LWP"
-  "lwpins\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
+   (set_attr "mode" "<MODE>")
+   (set (attr "length")
+        (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
 
-(define_insn "lwp_lwpinssi3"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:SI 2 "const_int_operand" "")]
-		    UNSPECV_LWPINS_INTRINSIC)]
+(define_expand "lwp_lwpins<mode>3"
+  [(set (reg:CCC FLAGS_REG)
+	(unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand" "r")
+			      (match_operand:SI 2 "nonimmediate_operand" "rm")
+			      (match_operand:SI 3 "const_int_operand" "i")]
+			     UNSPECV_LWPINS_INTRINSIC))
+   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+	(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
   "TARGET_LWP"
-  "lwpins\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
+  "")
 
-(define_insn "lwp_lwpinsdi3"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:SI 2 "const_int_operand" "")]
-		    UNSPECV_LWPINS_INTRINSIC)]
+(define_insn "*lwp_lwpins<mode>3_1"
+  [(set (reg:CCC FLAGS_REG)
+	(unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r")
+			      (match_operand:SI 1 "nonimmediate_operand" "rm")
+			      (match_operand:SI 2 "const_int_operand" "i")]
+			     UNSPECV_LWPINS_INTRINSIC))]
   "TARGET_LWP"
   "lwpins\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "<MODE>")
+   (set (attr "length")
+        (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
 
 (include "mmx.md")
 (include "sse.md")
diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h
index e5137ec24f4..954b039e542 100644
--- a/gcc/config/i386/lwpintrin.h
+++ b/gcc/config/i386/lwpintrin.h
@@ -33,77 +33,68 @@
 #else
 
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb16 (void *pcbAddress)
+__llwpcb (void *pcbAddress)
 {
-  __builtin_ia32_llwpcb16 (pcbAddress);
-}
-
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb32 (void *pcbAddress)
-{
-  __builtin_ia32_llwpcb32 (pcbAddress);
-}
-
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb64 (void *pcbAddress)
-{
-  __builtin_ia32_llwpcb64 (pcbAddress);
-}
-
-extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb16 (void)
-{
-  return __builtin_ia32_slwpcb16 ();
-}
-
-extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb32 (void)
-{
-  return __builtin_ia32_slwpcb32 ();
+  __builtin_ia32_llwpcb (pcbAddress);
 }
 
 extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb64 (void)
+__slwpcb (void)
 {
-  return __builtin_ia32_slwpcb64 ();
+  return __builtin_ia32_slwpcb ();
 }
 
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpval16 (unsigned short data2, unsigned int data1, unsigned short flags)
-{
-  __builtin_ia32_lwpval16 (data2, data1, flags);
-}
-/*
+#ifdef __OPTIMIZE__
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __lwpval32 (unsigned int data2, unsigned int data1, unsigned int flags)
 {
   __builtin_ia32_lwpval32 (data2, data1, flags);
 }
 
+#ifdef __x86_64__
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpval64 (unsigned __int64 data2, unsigned int data1, unsigned int flags)
+__lwpval64 (unsigned long long data2, unsigned int data1, unsigned int flags)
 {
   __builtin_ia32_lwpval64 (data2, data1, flags);
 }
+#endif
+#else
+#define __lwpval32(D2, D1, F) \
+  (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
+			    (unsigned int) (F)))
+#ifdef __x86_64__
+#define __lwpval64(D2, D1, F) \
+  (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
+			    (unsigned int) (F)))
+#endif
+#endif
 
-extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpins16 (unsigned short data2, unsigned int data1, unsigned short flags)
-{
-  return __builtin_ia32_lwpins16 (data2, data1, flags);
-}
 
+#ifdef __OPTIMIZE__
 extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __lwpins32 (unsigned int data2, unsigned int data1, unsigned int flags)
 {
   return __builtin_ia32_lwpins32 (data2, data1, flags);
 }
 
+#ifdef __x86_64__
 extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpins64 (unsigned __int64 data2, unsigned int data1, unsigned int flags)
+__lwpins64 (unsigned long long data2, unsigned int data1, unsigned int flags)
 {
   return __builtin_ia32_lwpins64 (data2, data1, flags);
 }
-*/
+#endif
+#else
+#define __lwpins32(D2, D1, F) \
+  (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
+			    (unsigned int) (F)))
+#ifdef __x86_64__
+#define __lwpins64(D2, D1, F) \
+  (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
+			    (unsigned int) (F)))
+#endif
+#endif
+
 #endif /* __LWP__ */
 
 #endif /* _LWPINTRIN_H_INCLUDED */
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 4a314e842c6..77baff0f4b9 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -1,8 +1,8 @@
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, xopintrin.h, mm3dnow.h,
-   abmintrin.h and mm_malloc.h are usable with -O -std=c89
-   -pedantic-errors.  */
+   abmintrin.h, lwpintrin.h, popcntintrin.h and mm_malloc.h are usable
+   with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mabm" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 546a99fdc08..96214e02280 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,13 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mabm" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
 
 #include <mm_malloc.h>
 
 /* Test that the intrinsics compile with optimization.  All of them
    are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h,
-   xopintrin.h, abmintrin.h and mm3dnow.h that reference the proper
-   builtin functions.  Defining away "extern" and "__inline" results
-   in all of them being compiled as proper functions.  */
+   xopintrin.h, abmintrin.h, lwpintrin.h, popcntintrin.h and mm3dnow.h
+   that reference the proper builtin functions.  Defining away
+   "extern" and "__inline" results in all of them being compiled as
+   proper functions.  */
 
 #define extern
 #define __inline
@@ -127,9 +128,15 @@
 #define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
 
 /* xopintrin.h */
-#define  __builtin_ia32_vprotbi(A, N) __builtin_ia32_vprotbi (A,1)
-#define  __builtin_ia32_vprotwi(A, N) __builtin_ia32_vprotwi (A,1)
-#define  __builtin_ia32_vprotdi(A, N) __builtin_ia32_vprotdi (A,1)
-#define  __builtin_ia32_vprotqi(A, N) __builtin_ia32_vprotqi (A,1)
+#define __builtin_ia32_vprotbi(A, N) __builtin_ia32_vprotbi (A,1)
+#define __builtin_ia32_vprotwi(A, N) __builtin_ia32_vprotwi (A,1)
+#define __builtin_ia32_vprotdi(A, N) __builtin_ia32_vprotdi (A,1)
+#define __builtin_ia32_vprotqi(A, N) __builtin_ia32_vprotqi (A,1)
+
+/* lwpintrin.h */
+#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1)
+#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1)
+#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1)
+#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1)
 
 #include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 783cd0af106..c3f72e419c7 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,12 +1,13 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul -mpopcnt -mabm -mlwp" } */
 
 #include <mm_malloc.h>
 
 /* Test that the intrinsics compile without optimization.  All of them are
-   defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h  and mm3dnow.h
-   that reference the proper builtin functions.  Defining away "extern" and
-   "__inline" results in all of them being compiled as proper functions.  */
+   defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h,
+   lwpintrin.h and mm3dnow.h that reference the proper builtin functions.
+   Defining away "extern" and "__inline" results in all of them being compiled
+   as proper functions.  */
 
 #define extern
 #define __inline
@@ -162,3 +163,10 @@ test_1 ( _mm_roti_epi16, __m128i, __m128i, 1)
 test_1 ( _mm_roti_epi32, __m128i, __m128i, 1)
 test_1 ( _mm_roti_epi64, __m128i, __m128i, 1)
 
+/* lwpintrin.h */
+test_2 ( __lwpval32, void, unsigned int, unsigned int, 1)
+test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1)
+test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1)
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 541cad4d439..6d976972d28 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -4,10 +4,12 @@
 
 #include <mm_malloc.h>
 
-/* Test that the intrinsics compile without optimization.  All of them are
-   defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h and mm3dnow.h
-   that reference the proper builtin functions.  Defining away "extern" and
-   "__inline" results in all of them being compiled as proper functions.  */
+/* Test that the intrinsics compile without optimization.  All of them
+   are defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h,
+   xopintrin.h, lwpintrin.h, popcntintrin.h and mm3dnow.h that
+   reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper
+   functions.  */
 
 #define extern
 #define __inline
@@ -37,7 +39,7 @@
 
 
 #ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop")
+#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp")
 #endif
 
 /* Following intrinsics require immediate arguments.  They
@@ -162,10 +164,18 @@ test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
 
 /* xopintrin.h (XOP). */
 #ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("xop")
+#pragma GCC target ("xop,lwp")
 #endif
 #include <x86intrin.h>
 test_1 ( _mm_roti_epi8, __m128i, __m128i, 1)
 test_1 ( _mm_roti_epi16, __m128i, __m128i, 1)
 test_1 ( _mm_roti_epi32, __m128i, __m128i, 1)
 test_1 ( _mm_roti_epi64, __m128i, __m128i, 1)
+
+/* lwpintrin.h (LWP). */
+test_2 ( __lwpval32, void, unsigned int, unsigned int, 1)
+test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1)
+test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1)
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 3e0fa1f5ca4..f74d3a71f6e 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -3,10 +3,12 @@
 
 #include <mm_malloc.h>
 
-/* Test that the intrinsics compile with optimization.  All of them are
-   defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h and mm3dnow.h
-   that reference the proper builtin functions.  Defining away "extern" and
-   "__inline" results in all of them being compiled as proper functions.  */
+/* Test that the intrinsics compile with optimization.  All of them
+   are defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h,
+   xopintrin.h, lwpintrin.h, popcntintrin.h and mm3dnow.h that
+   reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper
+   functions.  */
 
 #define extern
 #define __inline
@@ -93,13 +95,52 @@
 #define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
 #define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
 
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+
 /* xopintrin.h */
 #define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1)
 #define __builtin_ia32_vprotwi(A, B) __builtin_ia32_vprotwi(A,1)
 #define __builtin_ia32_vprotdi(A, B) __builtin_ia32_vprotdi(A,1)
 #define __builtin_ia32_vprotqi(A, B) __builtin_ia32_vprotqi(A,1)
 
-#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop")
+/* lwpintrin.h */
+#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1)
+#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1)
+#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1)
+#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1)
+
+#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp")
 #include <wmmintrin.h>
 #include <smmintrin.h>
 #include <mm3dnow.h>
+#include <x86intrin.h>