sparc.md (movtf_insn_sp32, [...]): Accept loading 0.0 into GENERAL_REGS.

	* config/sparc/sparc.md (movtf_insn_sp32, movtf_insn_vis_sp32,
	movtf_no_e_insn_sp32, movtf_insn_hq_sp64, movtf_insn_hq_vis_sp64,
	movtf_no_e_insn_sp64): Accept loading 0.0 into GENERAL_REGS.
	(movtf_insn_sp64, movtf_insn_vis_sp64): Likewise.
	Accept storing GENERAL_REGS into offsetable memory.
	* config/sparc/sparc.h (PREFERRED_RELOAD_CLASS): Don't allow
	building a TFmode constant other than 0.0L into GENERAL_REGS.

From-SVN: r32972

3 files changed, 30 insertions, 17 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 07f9c415211..202f8a290c3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2000-04-06  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/sparc/sparc.md (movtf_insn_sp32, movtf_insn_vis_sp32,
+	movtf_no_e_insn_sp32, movtf_insn_hq_sp64, movtf_insn_hq_vis_sp64,
+	movtf_no_e_insn_sp64): Accept loading 0.0 into GENERAL_REGS.
+	(movtf_insn_sp64, movtf_insn_vis_sp64): Likewise.
+	Accept storing GENERAL_REGS into offsetable memory.
+	* config/sparc/sparc.h (PREFERRED_RELOAD_CLASS): Don't allow
+	building a TFmode constant other than 0.0L into GENERAL_REGS.
+
 2000-04-06  Clinton Popetz  <cpopetz@cygnus.com>
 
 	* regrename.c (regrename_optimize): Handle no REG_ALLOC_ORDER.
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 477e45d5b37..5b226578d8b 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1454,6 +1454,8 @@ extern char leaf_reg_remap[];
 /* - We can't load constants into FP registers.
    - We can't load FP constants into integer registers when soft-float,
      because there is no soft-float pattern with a r/F constraint.
+   - We can't load FP constants into integer registers for TFmode unless
+     it is 0.0L, because there is no movtf pattern with a r/F constraint.
    - Try and reload integer constants (symbolic or otherwise) back into
      registers directly, rather than having them dumped to memory.  */
 
@@ -1461,7 +1463,9 @@ extern char leaf_reg_remap[];
   (CONSTANT_P (X)					\
    ? ((FP_REG_CLASS_P (CLASS)				\
        || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT	\
-	   && ! TARGET_FPU))				\
+	   && ! TARGET_FPU)				\
+       || (GET_MODE (X) == TFmode			\
+	   && ! fp_zero_operand (X, TFmode)))		\
       ? NO_REGS						\
       : (!FP_REG_CLASS_P (CLASS)			\
          && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)	\
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 458038db51a..9b91c3090a3 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -3705,8 +3705,8 @@
 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
 ;; we must split them all.  :-(
 (define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,o,r,o")
-	(match_operand:TF 1 "input_operand"    "oe,Ge,o,U,ro,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
+	(match_operand:TF 1 "input_operand"    "oe,GeUr,o,roG"))]
   "TARGET_FPU
    && ! TARGET_VIS
    && ! TARGET_ARCH64
@@ -3717,8 +3717,8 @@
   [(set_attr "length" "4")])
 
 (define_insn "*movtf_insn_vis_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,o,r,o")
-	(match_operand:TF 1 "input_operand"    "Goe,Ge,o,U,ro,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
+	(match_operand:TF 1 "input_operand"    "Goe,GeUr,o,roG"))]
   "TARGET_FPU
    && TARGET_VIS
    && ! TARGET_ARCH64
@@ -3734,7 +3734,7 @@
 
 (define_insn "*movtf_no_e_insn_sp32"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
-	(match_operand:TF 1 "input_operand"    "G,o,U,ro,r"))]
+	(match_operand:TF 1 "input_operand"    "G,o,U,roG,r"))]
   "! TARGET_FPU
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
@@ -3746,8 +3746,8 @@
 ;; Now handle the float reg cases directly when arch64,
 ;; hard_quad, and proper reg number alignment are all true.
 (define_insn "*movtf_insn_hq_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r,o")
-        (match_operand:TF 1 "input_operand"    "e,m,e,G,ro,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
+        (match_operand:TF 1 "input_operand"    "e,m,e,Gr,roG"))]
   "TARGET_FPU
    && ! TARGET_VIS
    && TARGET_ARCH64
@@ -3760,14 +3760,13 @@
   ldq\\t%1, %0
   stq\\t%1, %0
   #
-  #
   #"
-  [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
-   (set_attr "length" "1,1,1,2,2,2")])
+  [(set_attr "type" "fpmove,fpload,fpstore,*,*")
+   (set_attr "length" "1,1,1,2,2")])
 
 (define_insn "*movtf_insn_hq_vis_sp64"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
-        (match_operand:TF 1 "input_operand"    "e,m,e,G,ro,r"))]
+        (match_operand:TF 1 "input_operand"    "e,m,e,G,roG,r"))]
   "TARGET_FPU
    && TARGET_VIS
    && TARGET_ARCH64
@@ -3788,8 +3787,8 @@
 ;; Now we allow the integer register cases even when
 ;; only arch64 is true.
 (define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,e,r")
-        (match_operand:TF 1 "input_operand"    "Ge,oe,or"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
+        (match_operand:TF 1 "input_operand"    "oe,Ger,orG"))]
   "TARGET_FPU
    && ! TARGET_VIS
    && TARGET_ARCH64
@@ -3801,8 +3800,8 @@
   [(set_attr "length" "2")])
 
 (define_insn "*movtf_insn_vis_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=eo,e,r")
-        (match_operand:TF 1 "input_operand"    "Ge,o,or"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
+        (match_operand:TF 1 "input_operand"    "Goe,Ger,orG"))]
   "TARGET_FPU
    && TARGET_VIS
    && TARGET_ARCH64
@@ -3815,7 +3814,7 @@
 
 (define_insn "*movtf_no_e_insn_sp64"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
-        (match_operand:TF 1 "input_operand"    "or,rG"))]
+        (match_operand:TF 1 "input_operand"    "orG,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], TFmode)