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| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-05-12 00:52:27 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-05-12 00:52:27 +0000 |
| commit | 7cfc36c0b1eb368f70a4997fe6cdcf22c3f6ad03 (patch) | |
| tree | 324e01ab5bb18d2e469d5a7647977e9787b4eb6d | |
| parent | 11c399adb57bd75a477e7dac5a8d524d185bd8d5 (diff) | |
| download | gcc-7cfc36c0b1eb368f70a4997fe6cdcf22c3f6ad03.tar.gz | |
Add storent<mode> and <code><mode>2: absneg patches for AVX.
2010-05-11 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/sse.md (storent<mode>): New for AVX.
(<code><mode>2: absneg): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/vect256@159302 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog.vect256 | 5 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 15 |
2 files changed, 20 insertions, 0 deletions
diff --git a/gcc/ChangeLog.vect256 b/gcc/ChangeLog.vect256 index 0c7e2530b40..689b742b213 100644 --- a/gcc/ChangeLog.vect256 +++ b/gcc/ChangeLog.vect256 @@ -1,5 +1,10 @@ 2010-05-11 H.J. Lu <hongjiu.lu@intel.com> + * config/i386/sse.md (storent<mode>): New for AVX. + (<code><mode>2: absneg): Likewise. + +2010-05-11 H.J. Lu <hongjiu.lu@intel.com> + * config/i386/i386.h (UNITS_PER_SIMD_WORD_MAX): Use UNITS_PER_SIMD_WORD. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7eb3ad20514..dd4f24389c2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -496,6 +496,14 @@ ; define patterns for other modes that would expand to several insns. (define_expand "storent<mode>" + [(set (match_operand:AVX256MODEF2P 0 "memory_operand" "") + (unspec:AVX256MODEF2P + [(match_operand:AVX256MODEF2P 1 "register_operand" "")] + UNSPEC_MOVNT))] + "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)" + "") + +(define_expand "storent<mode>" [(set (match_operand:SSEMODEF2P 0 "memory_operand" "") (unspec:SSEMODEF2P [(match_operand:SSEMODEF2P 1 "register_operand" "")] @@ -532,6 +540,13 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "<code><mode>2" + [(set (match_operand:AVX256MODEF2P 0 "register_operand" "") + (absneg:AVX256MODEF2P + (match_operand:AVX256MODEF2P 1 "register_operand" "")))] + "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)" + "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") + +(define_expand "<code><mode>2" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") (absneg:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")))] |