Add __attribute__ ((target("general-regs-only")))hjl/pr70738/master

One test fails:

FAIL: gcc.target/i386/pr70738-15.c  (test for errors, line 10)

due to

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71318

10 files changed, 144 insertions, 0 deletions

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 7e9f51148f5..7cf8682ac65 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6381,6 +6381,8 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("clzero",    OPT_mclzero),
     IX86_ATTR_ISA ("pku",	OPT_mpku),
 
+    IX86_ATTR_ISA ("general-regs-only",	OPT_mgeneral_regs_only),
+
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
 
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-10.c b/gcc/testsuite/gcc.target/i386/pr70738-10.c
new file mode 100644
index 00000000000..db45b5c8837
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-10.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2" } */
+
+typedef int int32x2_t __attribute__ ((__vector_size__ ((8))));
+
+__attribute__ ((target("general-regs-only")))
+int32x2_t test (int32x2_t a, int32x2_t b)
+{ /* { dg-error "SSE register return with SSE disabled" } */
+  return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-11.c b/gcc/testsuite/gcc.target/i386/pr70738-11.c
new file mode 100644
index 00000000000..f9240f87d26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mmmx" } */
+
+typedef int int32x2_t __attribute__ ((__vector_size__ ((8))));
+
+__attribute__ ((target("general-regs-only")))
+int32x2_t
+test (int32x2_t a, int32x2_t b) /* { dg-warning "MMX vector argument without MMX enabled" } */
+{ /* { dg-warning "MMX vector return without MMX enabled" } */
+  return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-12.c b/gcc/testsuite/gcc.target/i386/pr70738-12.c
new file mode 100644
index 00000000000..6bc6ea1e825
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-12.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2" } */
+
+typedef int int32x4_t __attribute__ ((__vector_size__ ((16))));
+extern int32x4_t c;
+
+__attribute__ ((target("general-regs-only")))
+void
+test (int32x4_t a, int32x4_t b) /* { dg-warning "SSE vector argument without SSE enabled" } */
+{
+  c = a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-13.c b/gcc/testsuite/gcc.target/i386/pr70738-13.c
new file mode 100644
index 00000000000..99dca2c30d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-13.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-msse2" } */
+
+typedef int int32x4_t __attribute__ ((__vector_size__ ((16))));
+
+__attribute__ ((target("general-regs-only")))
+int32x4_t
+test (int32x4_t a, int32x4_t b) /* { dg-warning "SSE vector argument without SSE enabled" } */
+{ /* { dg-warning "SSE vector return without SSE enabled" } */
+  return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-14.c b/gcc/testsuite/gcc.target/i386/pr70738-14.c
new file mode 100644
index 00000000000..86bb0fbdae7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-14.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2" } */
+
+#include <stdarg.h>
+
+typedef int int32x2_t __attribute__ ((__vector_size__ ((8))));
+
+__attribute__ ((target("general-regs-only")))
+int
+test (int i, ...)
+{
+  va_list argp;
+  va_start (argp, i);
+  int32x2_t x = (int32x2_t) {0, 1};
+  x += va_arg (argp, int32x2_t); /* { dg-error "SSE register argument with SSE disabled" } */
+  return x[0] + x[1];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-15.c b/gcc/testsuite/gcc.target/i386/pr70738-15.c
new file mode 100644
index 00000000000..9a9b350e4ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-15.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2" } */
+
+extern float a, b, c;
+
+__attribute__ ((target("general-regs-only")))
+void
+foo (void)
+{
+  c = a * b; /* { dg-error "SSE register return with SSE disabled" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-16.c b/gcc/testsuite/gcc.target/i386/pr70738-16.c
new file mode 100644
index 00000000000..9e40571af00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-msse2" } */
+
+extern float a, b, c;
+
+__attribute__ ((target("general-regs-only")))
+void
+foo (void)
+{
+  c = a * b;
+}
+
+/* { dg-final { scan-assembler-not "mulss" } } */
+/* { dg-final { scan-assembler "call\[ \t\]__mulsf3" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-17.c b/gcc/testsuite/gcc.target/i386/pr70738-17.c
new file mode 100644
index 00000000000..49c227fc5f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-17.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort ();
+
+__attribute__ ((target("general-regs-only")))
+int
+dec (int a, int b)
+{
+  return a + b;
+}
+
+__attribute__ ((target("general-regs-only")))
+int
+cal (int a, int b)
+{
+  int sum1 = a * b;
+  int sum2 = a / b;
+  int sum = dec (sum1, sum2);
+  return a + b + sum + sum1 + sum2;
+}
+
+int
+main (int argc, char **argv)
+{
+  int ret = cal (2, 1);
+
+  if (ret != 11)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr70738-18.c b/gcc/testsuite/gcc.target/i386/pr70738-18.c
new file mode 100644
index 00000000000..67d32113d09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70738-18.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort ();
+
+__attribute__ ((target("general-regs-only")))
+int
+cal (int a, int b)
+{
+  int sum = a + b;
+  int sum1 = a * b;
+  return (a + b + sum + sum1);
+}
+
+int
+main (int argc, char **argv)
+{
+  int ret = cal (1, 2);
+
+  if (ret != 8)
+    abort ();
+
+  return 0;
+}